Re: cgen/gas: some support for funny-endian instruction sets

["Frank Ch. Eigler" <fche at redhat dot com>]

Hi -

On Mon, Jul 09, 2001 at 09:12:04AM -0700, Doug Evans wrote:
: [...]
: This isn't the definition of "word-bitsize" that a gcc hacker
: would expect.  I think a lot of other people would also find this confusing.
: What's "word-bitsize" on sparc64?  If it's not 64, you've got problems.

The gcc meaning might be relevant, if only the word-bitsize parameter
was actually used for something in cgen in a similar way than it might
be in gcc.  Yes, a differently named parameter would be nice, but so
would elimination of unused parameters.


: [...]
: As I'm sure you know, you can't uniformly chunk up an insn
: in the general case.

Yes, the idea is to extend support to a larger class of processors.


: What problem are you trying to solve?

Specifically the example I posted: a bi-endian processor with a narrow
data bus that imposes the basic endianness, and multi-word instructions.


- FChE

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