Re: How to handle MIPS-like general register 0?

[Ben Elliston <bje at redhat dot com>]

   : What's the recommended way of handling simulator semantics for a
   : general register zero that always reads as 0, and writes as bit-bucket
   : (as for MIPS)?  [...]

   Another way is to add an explicit register-setting statement into each
   iteration of the instruction evaluation loop.  One trades the cost of
   a conditional branch (by intercepting the register-setting hooks) for
   the cost of fixed overhead (always clearing the sucker).

I found that method is much less obvious to the reader as to what's going
on.  In general, pushing as much stuff up to the cpu description as possible
is a good thing.

Ben