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Re: [PATCH, BINUTILS, AARCH64, 6/8] Add Bulk Allocation Tag instructions in Memory Tagging Extension
- From: Sudakshina Das <Sudi dot Das at arm dot com>
- To: Richard Earnshaw <Richard dot Earnshaw at arm dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, "nickc at redhat dot com" <nickc at redhat dot com>, nd <nd at arm dot com>
- Date: Thu, 8 Nov 2018 10:35:00 +0000
- Subject: Re: [PATCH, BINUTILS, AARCH64, 6/8] Add Bulk Allocation Tag instructions in Memory Tagging Extension
- References: <de18a031-af97-839c-3450-23cc7f257cb3@arm.com> <1ba3d8db-0ffa-5a07-a92d-4fac72f5462d@arm.com> <2406802e-6101-c576-7362-2c05a8f89d39@arm.com>
On 02/11/18 16:10, Sudakshina Das wrote:
> Hi Richard
>
> On 30/10/18 10:23, Richard Earnshaw (lists) wrote:
>> On 09/10/2018 18:25, Sudakshina Das wrote:
>>> Hi
>>>
>>> This patch is part of the patch series to add support for ARMv8.5-A
>>> Memory Tagging Extensions.
>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>
>>>
>>> Memory Tagging Extension (MTE) is an optional extension to
>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>
>>> This patch add support to the Bulk Allocation Tag instructions from
>>> MTE. These are the following instructions added in this patch:
>>> - LDGV <Xt>, [<Xn|SP>]!
>>> - STGV <Xt>, [<Xn|SP>]!
>>>
>>> This needed a new kind of operand for the new addressing [<Xn|SP>]!
>>> since this has no offset and only takes a pre-indexed version.
>>> Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
>>> (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
>>> not allow writeback). We also needed new encoding and decoding
>>> functions to be able to do the same.
>>>
>>> where
>>> <Xt> : Is the 64-bit destination GPR.
>>> <Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
>>>
>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>> Added test.
>>>
>>> Is this ok for trunk?
>>>
>>> Thanks
>>> Sudi
>>>
>>> *** include/ChangeLog ***
>>>
>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>
>>> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
>>> (aarch64_insn_class): Add ldstgv_indexed.
>>>
>>> *** opcodes/ChangeLog ***
>>>
>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>
>>> * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
>>> * aarch64-asm.h (ins_addr_simple_2): Declare the above.
>>> * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
>>> * aarch64-dis.h (ext_addr_simple_2): Declare the above.
>>> * aarch64-opc.c (operand_general_constraint_met_p): Add case for
>>> AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
>>> (aarch64_print_operand): Add case for
>>> AARCH64_OPND_ADDR_SIMPLE_2.
>>> * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
>>> (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
>>> * aarch64-asm-2.c: Regenarated.
>>> * aarch64-dis-2.c: Regenerated.
>>> * aarch64-opc-2.c: Regenerated.
>>>
>>> *** gas/ChangeLog ***
>>>
>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>
>>> * config/tc-aarch64.c (parse_operands): Add switch case for
>>> AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
>>> * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for ldgv and
>>> stgv.
>>> * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>
>>>
>>
>> Same issue re mte.
>>
>> I'd also like to see some error tests, eg for missing the mandatory
>> write-back character.
>>
>> R.
>>
>
> *** include/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
> (aarch64_insn_class): Add ldstgv_indexed.
>
> *** opcodes/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
> * aarch64-asm.h (ins_addr_simple_2): Declare the above.
> * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
> * aarch64-dis.h (ext_addr_simple_2): Declare the above.
> * aarch64-opc.c (operand_general_constraint_met_p): Add case for
> AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
> (aarch64_print_operand): Add case for
> AARCH64_OPND_ADDR_SIMPLE_2.
> * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
> (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
> * aarch64-asm-2.c: Regenerated.
> * aarch64-dis-2.c: Regenerated.
> * aarch64-opc-2.c: Regenerated.
>
> *** gas/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * config/tc-aarch64.c (parse_operands): Add switch case for
> AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
> (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv
> and stgv.
> * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
> * testsuite/gas/aarch64/illegal-memtag.s: Likewise
> * testsuite/gas/aarch64/illegal-memtag.l: Likewise
>
New patch. Changelog still applies.
Sudi
> Thanks
> Sudi
>
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index a5eee96233d78bbdcedc552597d056cb442fb245..3fed11cb6c61430f1c4822a1a18b7635c473bebf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3372,6 +3372,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
[base,Wm,(S|U)XTW {#imm}]
Pre-indexed
[base,#imm]!
+ [base]! // in ld/stgv
Post-indexed
[base],#imm
[base],Xm // in SIMD ld/st structure
@@ -3680,10 +3681,11 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
}
/* If at this point neither .preind nor .postind is set, we have a
- bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
+ bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
+ as a shorthand for [Rn,#0]. */
if (operand->addr.preind == 0 && operand->addr.postind == 0)
{
- if (operand->addr.writeback)
+ if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback)
{
/* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address"));
@@ -6137,6 +6139,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_ADDR_SIMPLE:
+ case AARCH64_OPND_ADDR_SIMPLE_2:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
/* [<Xn|SP>{, #<simm>}] */
@@ -6146,7 +6149,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind
- || info->addr.writeback)
+ || (info->addr.writeback
+ && operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
{
set_syntax_error (_("invalid addressing mode"));
goto failure;
@@ -6169,6 +6173,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
}
po_char_or_fail (']');
+ if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
+ po_char_or_fail ('!');
break;
}
@@ -6766,6 +6772,14 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
&& opnds[1].addr.writeback)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break;
+
+ case ldstgv_indexed:
+ /* Load operations must load different registers. */
+ if ((opcode->opcode & (1 << 22))
+ && opnds[0].reg.regno == opnds[1].addr.base_regno)
+ as_warn (_("unpredictable load of register -- `%s'"), str);
+ break;
+
case ldstpair_off:
case ldstnapair_offs:
case ldstpair_indexed:
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 363bbe2eb3b1da373737c7d6efce9eba3b6bb6a1..fa56bfa64c984da329c150b24852a2278d559b85 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -121,3 +121,14 @@ Disassembly of section \.text:
.*: d960001f ldg xzr, \[x0\]
.*: d96ff000 ldg x0, \[x0, #4080\]
.*: d9700000 ldg x0, \[x0, #-4096\]
+.*: d9e0001b ldgv x27, \[x0\]!
+.*: d9e00360 ldgv x0, \[x27\]!
+.*: d9e00379 ldgv x25, \[x27\]!
+.*: d9e003e0 ldgv x0, \[sp\]!
+.*: d9e0001f ldgv xzr, \[x0\]!
+.*: d9a00000 stgv x0, \[x0\]!
+.*: d9a0001b stgv x27, \[x0\]!
+.*: d9a00360 stgv x0, \[x27\]!
+.*: d9a00379 stgv x25, \[x27\]!
+.*: d9a003e0 stgv x0, \[sp\]!
+.*: d9a0001f stgv xzr, \[x0\]!
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 62c9436d78fea63a8ac45126c5f85416a1487822..2c2ff8f44460ee9b818efb4b7b7510846a46c136 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -30,6 +30,14 @@ func:
\op [sp], #-4096
.endm
+ .macro expand_ldg_bulk op
+ \op x27, [x0]!
+ \op x0, [x27]!
+ \op x25, [x27]!
+ \op x0, [sp]!
+ \op xzr, [x0]!
+ .endm
+
# IRG
expand_3_reg irg
irg sp, x0
@@ -98,3 +106,8 @@ func:
ldg xzr, [x0, #0]
ldg x0, [x0, #4080]
ldg x0, [x0, #-4096]
+
+ expand_ldg_bulk ldgv
+
+ stgv x0, [x0]!
+ expand_ldg_bulk stgv
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index dfdf00aba1ea3e21c29ca602de30336b3f00859b..0d499d9ee955d97183dacab50223a692f2e9d080 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -12,6 +12,9 @@
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
+[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
+[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
+[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
@@ -37,3 +40,7 @@
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 35d1b12870bee105ede52d86b392afc68c8190d0..7b7dcd94a1a05dbcf5e603b08e6a95835efc5470 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -20,6 +20,14 @@ func:
stgp x1, x2, [x3, #33]
stgp x1, x2, [x3, #-1025]
+ # LDGV : Warn for Xt == Xn
+ # STGV : Sould not warn for above
+ ldgv x1, [x1]!
+ stgv x1, [x1]!
+ # Error for no writeback
+ ldgv x1, [x2]
+ stgv x1, [x2]
+
# Illegal SP/XZR registers
irg xzr, x2, x3
irg x1, xzr, x3
@@ -46,3 +54,7 @@ func:
stgp x0, x0, [xzr]
ldg sp, [x0, #16]
ldg x0, [xzr, #16]
+ ldgv sp, [x1]!
+ ldgv x0, [xzr]!
+ stgv sp, [x1]!
+ stgv x0, [xzr]!
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c4c573a478944eca1ef0f7bb84dd95d8354a8e78..08402392236c4248e23d030e1601029b538a341e 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -275,6 +275,7 @@ enum aarch64_opnd
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
+ AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
@@ -561,6 +562,7 @@ enum aarch64_insn_class
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
+ ldstgv_indexed,
loadlit,
log_imm,
log_shift,
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 0524f9182eb295c55aa570c1b786b63ef4820e73..fec54489bfd3e32ba24fac9f9a4a629a820024c9 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -59,6 +59,7 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
+AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e53b98a67f9dc9e0b4638695b9c03d55234c5025..e3380cbee96546bc3dd9a9271a4fa3777638beed 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -618,6 +618,17 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
+/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
+bfd_boolean
+aarch64_ins_addr_simple_2 (const aarch64_operand *self,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst,
+ aarch64_operand_error *errors)
+
+{
+ return aarch64_ins_addr_simple (self, info, code, inst, errors);
+}
+
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
bfd_boolean
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index b09a5ee10d3b951b3c93b416b48b8fd91260d1c6..8949852da354ea0296d8fa033d4b5c9d2bf6045b 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -82,6 +82,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
+AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple_2);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index defb53dfd2566149f11052f713bf048ecc30334d..fd542aca9baac6cda4c457c64208f1df8ae87f6f 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -985,6 +985,23 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
+
+
+/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
+bfd_boolean
+aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ info->addr.base_regno = extract_field (FLD_Rn, code, 0);
+ info->addr.writeback = 1;
+ info->addr.preind = 1;
+ return TRUE;
+}
+
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bfd_boolean
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 433336f76848db91da1577b740faea3c2c3bcd68..3bc2cccc7969567a645d2982fd091d67af044c93 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1602,6 +1602,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case ldst_imm9:
case ldstpair_indexed:
+ case ldstgv_indexed:
case asisdlsep:
case asisdlsop:
if (opnd->addr.writeback == 0)
@@ -3556,6 +3557,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "[%s]", name);
break;
+ case AARCH64_OPND_ADDR_SIMPLE_2:
+ name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
+ snprintf (buf, size, "[%s]!", name);
+ break;
+
case AARCH64_OPND_ADDR_REGOFF:
case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1118433a5a03bcaf143dd136582af6661ff1071b..6fb74bfaca0d3067c6d1b07a5d90946887d1b34d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3324,6 +3324,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
+ MEMTAG_INSN ("ldgv", 0xd9e00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
+ MEMTAG_INSN ("stgv", 0xd9a00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
/* Limited Ordering Regions load/store instructions. */
_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
@@ -4648,6 +4650,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_imm26), "26-bit PC-relative address") \
Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
"an address with base register (no offset)") \
+ Y(ADDRESS, addr_simple_2, "ADDR_SIMPLE_2", 0, F(), \
+ "a writeback address with base register (no offset)") \
Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
"an address with register offset") \
Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \