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[PATCH 4/5] x86: CpuXSAVE is a prereq for various other features
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Wed, 25 Apr 2018 04:30:49 -0600
- Subject: [PATCH 4/5] x86: CpuXSAVE is a prereq for various other features
- References: <5AE0566402000078001BE4EA@prv1-mh.provo.novell.com>
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as
XRSTOR should be enabled when enabling these ISA extensions. Leverage
these implications to shorten some of the cpu_flag_init[] entries.
gas/
2018-04-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/xsave.s: Add AVX, LWP, MPX, and PKU
dependency tests.
* testsuite/gas/i386/xsave.d,
testsuite/gas/i386/xsave-intel.d: Adjust expecations.
opcodes/
2018-04-25 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
* i386-init.h: Re-generate.
--- a/gas/testsuite/gas/i386/xsave-intel.d
+++ b/gas/testsuite/gas/i386/xsave-intel.d
@@ -16,4 +16,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f ae 29 xrstor \[ecx\]
[ ]*[a-f0-9]+: 0f ae 21 xsave \[ecx\]
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \[ecx\]
+[a-f0-9]+ <avx>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \[eax\]
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \[eax\]
+[a-f0-9]+ <lwp>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \[eax\]
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \[eax\]
+[a-f0-9]+ <mpx>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \[eax\]
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \[eax\]
+[a-f0-9]+ <pku>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \[eax\]
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \[eax\]
#pass
--- a/gas/testsuite/gas/i386/xsave.d
+++ b/gas/testsuite/gas/i386/xsave.d
@@ -14,4 +14,16 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%ecx\)
[ ]*[a-f0-9]+: 0f ae 21 xsave \(%ecx\)
[ ]*[a-f0-9]+: 0f ae 31 xsaveopt \(%ecx\)
+[a-f0-9]+ <avx>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \(%eax\)
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \(%eax\)
+[a-f0-9]+ <lwp>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \(%eax\)
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \(%eax\)
+[a-f0-9]+ <mpx>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \(%eax\)
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \(%eax\)
+[a-f0-9]+ <pku>:
+[ ]*[a-f0-9]+: 0f ae 20 xsave \(%eax\)
+[ ]*[a-f0-9]+: 0f ae 28 xrstor \(%eax\)
#pass
--- a/gas/testsuite/gas/i386/xsave.s
+++ b/gas/testsuite/gas/i386/xsave.s
@@ -11,3 +11,28 @@ _start:
xrstor [ecx]
xsave [ecx]
xsaveopt [ecx]
+
+ .att_syntax prefix
+avx:
+ .arch generic32
+ .arch .avx
+ xsave (%eax)
+ xrstor (%eax)
+
+lwp:
+ .arch generic32
+ .arch .lwp
+ xsave (%eax)
+ xrstor (%eax)
+
+mpx:
+ .arch generic32
+ .arch .mpx
+ xsave (%eax)
+ xrstor (%eax)
+
+pku:
+ .arch generic32
+ .arch .ospke
+ xsave (%eax)
+ xrstor (%eax)
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -88,7 +88,7 @@ static initializer cpu_flag_init[] =
{ "CPU_AMDFAM10_FLAGS",
"CPU_K8_FLAGS|CpuFISTTP|CPU_SSE4A_FLAGS|CpuABM" },
{ "CPU_BDVER1_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_SSE4_2_FLAGS|CpuSSE4A|CpuABM|CpuFMA4|CpuXOP|CpuLWP|CpuSVME|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" },
+ "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_XOP_FLAGS|CpuABM|CpuLWP|CpuSVME|CpuAES|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" },
{ "CPU_BDVER2_FLAGS",
"CPU_BDVER1_FLAGS|CpuFMA|CpuBMI|CpuTBM|CpuF16C" },
{ "CPU_BDVER3_FLAGS",
@@ -96,11 +96,11 @@ static initializer cpu_flag_init[] =
{ "CPU_BDVER4_FLAGS",
"CPU_BDVER3_FLAGS|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuMWAITX" },
{ "CPU_ZNVER1_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_SSE4_2_FLAGS|CpuSSE4A|CpuABM|CpuSVME|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" },
+ "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuABM|CpuSVME|CpuAES|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" },
{ "CPU_BTVER1_FLAGS",
"CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuABM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" },
{ "CPU_BTVER2_FLAGS",
- "CPU_BTVER1_FLAGS|CPU_SSE4_2_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuAVX|CpuMovbe|CpuXsave|CpuXsaveopt|CpuPRFCHW" },
+ "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuMovbe|CpuXsaveopt|CpuPRFCHW" },
{ "CPU_8087_FLAGS",
"Cpu8087" },
{ "CPU_287_FLAGS",
@@ -148,7 +148,7 @@ static initializer cpu_flag_init[] =
{ "CPU_XOP_FLAGS",
"CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|CpuXOP" },
{ "CPU_LWP_FLAGS",
- "CpuLWP" },
+ "CPU_XSAVE_FLAGS|CpuLWP" },
{ "CPU_BMI_FLAGS",
"CpuBMI" },
{ "CPU_TBM_FLAGS",
@@ -192,7 +192,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ABM_FLAGS",
"CpuABM" },
{ "CPU_AVX_FLAGS",
- "CPU_SSE4_2_FLAGS|CpuAVX" },
+ "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|CpuAVX" },
{ "CPU_AVX2_FLAGS",
"CPU_AVX_FLAGS|CpuAVX2" },
{ "CPU_AVX512F_FLAGS",
@@ -240,7 +240,7 @@ static initializer cpu_flag_init[] =
{ "CPU_SMAP_FLAGS",
"CpuSMAP" },
{ "CPU_MPX_FLAGS",
- "CpuMPX" },
+ "CPU_XSAVE_FLAGS|CpuMPX" },
{ "CPU_SHA_FLAGS",
"CPU_SSE2_FLAGS|CpuSHA" },
{ "CPU_CLFLUSHOPT_FLAGS",
@@ -260,7 +260,7 @@ static initializer cpu_flag_init[] =
{ "CPU_MWAITX_FLAGS",
"CpuMWAITX" },
{ "CPU_OSPKE_FLAGS",
- "CpuOSPKE" },
+ "CPU_XSAVE_FLAGS|CpuOSPKE" },
{ "CPU_RDPID_FLAGS",
"CpuRDPID" },
{ "CPU_PTWRITE_FLAGS",