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Re: [PATCH 3/4] x86/Intel: correct disassembly of fsub*/fdiv*


>>> On 08.03.18 at 13:57, <hjl.tools@gmail.com> wrote:
> On Wed, Mar 7, 2018 at 11:42 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 07.03.18 at 10:49, <JBeulich@suse.com> wrote:
>>> fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
>>> should match (a) the Intel SDM and (b) respective input fed to gas (both
>>> of course with the exception of when we intentionally convert bogus
>>> insns, accompanied by a warning).
>>>
>>> gas/
>>> 2018-03-07  Jan Beulich  <jbeulich@suse.com>
>>>
>>>       * testsuite/gas/i386/intel-intel.d: New.
>>>       * testsuite/gas/i386/i386.exp: Run new test.
>>>
>>> opcodes/
>>> 2018-03-07  Jan Beulich  <jbeulich@suse.com>
>>>
>>>       * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
>>>
>>> ---
>>> The logic behind -M{intel,att}{,-mnemonic} is bogus anyway, so there's
>>> the alternative of getting that straight: There's no such thing like
>>> Intel syntax with AT&T mnemonics (and the instances of ATTMnemonic
>>> without ATTSyntax in the opcode table look all bogus too). Instead there
>>> are only three sensible modes: Intel syntax, AT&T syntax with AT&T
>>> mnemonics, and AT&T syntax with Intel mnemonics. Hence an alternative
>>> fix would be to correct command line option handling, which is quite odd
>>> anyway - to get objdump to produce AT&T syntax with Intel mnemonics one
>>> has to pass "-Mintel-mnemonic -Matt" instead of the more logical
>>> "-Matt -Mintel-mnemonic" (ideally the order wouldn't matter at all).
>>
>> Btw, do you have any comment on this part?
> 
> Sounds reasonable.  Can you submit a patch?

Sure, I'll add that to my (quite long) todo list.

Jan


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