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[PATCH 1/4] x86: correctly encode FSUBP
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Wed, 07 Mar 2018 02:47:59 -0700
- Subject: [PATCH 1/4] x86: correctly encode FSUBP
- Authentication-results: sourceware.org; auth=none
- References: <5A9FC2B402000078001AF423@prv-mh.provo.novell.com>
While the combination of Intel syntax and AT&T mnemonics is bogus
anyway, we nevertheless shouldn't mis-encode such insns.
gas/
2018-03-07 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/fsubp.l, testsuite/gas/i386/fsubp.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
opcodes/
2018-03-07 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (fsubp): Correct encoding.
* i386-tlb.h: Re-generate.
--- /dev/null
+++ b/gas/testsuite/gas/i386/fsubp.l
@@ -0,0 +1,77 @@
+.*: Assembler messages:
+.*:5: Warning:.*
+.*:6: Warning:.*
+.*:8: Warning:.*
+.*:9: Warning:.*
+.*:12: Warning:.*
+.*:13: Warning:.*
+.*:15: Warning:.*
+.*:16: Warning:.*
+.*:21: Warning:.*
+.*:22: Warning:.*
+.*:23: Warning:.*
+.*:24: Warning:.*
+.*:25: Warning:.*
+.*:26: Warning:.*
+.*:28: Warning:.*
+.*:29: Warning:.*
+.*:30: Warning:.*
+.*:31: Warning:.*
+.*:32: Warning:.*
+.*:33: Warning:.*
+GAS LISTING .*
+
+
+ 1 \.text
+ 2 \.att_mnemonic
+ 3 div_a:
+ 4 0000 DEF0 fdivp %st, %st
+ 5 0002 DEF1 fdivp %st\(1\), %st
+.*Warning:.*
+ 6 0004 DEF2 fdivp %st\(2\), %st
+.*Warning:.*
+ 7 0006 DEF8 fdivrp %st, %st
+ 8 0008 DEF9 fdivrp %st\(1\), %st
+.*Warning:.*
+ 9 000a DEFA fdivrp %st\(2\), %st
+.*Warning:.*
+ 10 sub_a:
+ 11 000c DEE0 fsubp %st, %st
+ 12 000e DEE1 fsubp %st\(1\), %st
+.*Warning:.*
+ 13 0010 DEE2 fsubp %st\(2\), %st
+.*Warning:.*
+ 14 0012 DEE8 fsubrp %st, %st
+ 15 0014 DEE9 fsubrp %st\(1\), %st
+.*Warning:.*
+ 16 0016 DEEA fsubrp %st\(2\), %st
+.*Warning:.*
+ 17
+ 18 \.intel_syntax noprefix
+ 19 \.att_mnemonic
+ 20 div_i:
+ 21 0018 DEF8 fdivp st, st
+.*Warning:.*
+ 22 001a DEF9 fdivp st, st\(1\)
+.*Warning:.*
+ 23 001c DEFA fdivp st, st\(2\)
+.*Warning:.*
+ 24 001e DEF0 fdivrp st, st
+.*Warning:.*
+ 25 0020 DEF1 fdivrp st, st\(1\)
+.*Warning:.*
+ 26 0022 DEF2 fdivrp st, st\(2\)
+.*Warning:.*
+ 27 sub_i:
+ 28 0024 DEE8 fsubp st, st
+.*Warning:.*
+ 29 0026 DEE9 fsubp st, st\(1\)
+.*Warning:.*
+ 30 0028 DEEA fsubp st, st\(2\)
+.*Warning:.*
+ 31 002a DEE0 fsubrp st, st
+.*Warning:.*
+ 32 002c DEE1 fsubrp st, st\(1\)
+.*Warning:.*
+ 33 002e DEE2 fsubrp st, st\(2\)
+.*Warning:.*
--- /dev/null
+++ b/gas/testsuite/gas/i386/fsubp.s
@@ -0,0 +1,33 @@
+ .text
+ .att_mnemonic
+div_a:
+ fdivp %st, %st
+ fdivp %st(1), %st
+ fdivp %st(2), %st
+ fdivrp %st, %st
+ fdivrp %st(1), %st
+ fdivrp %st(2), %st
+sub_a:
+ fsubp %st, %st
+ fsubp %st(1), %st
+ fsubp %st(2), %st
+ fsubrp %st, %st
+ fsubrp %st(1), %st
+ fsubrp %st(2), %st
+
+ .intel_syntax noprefix
+ .att_mnemonic
+div_i:
+ fdivp st, st
+ fdivp st, st(1)
+ fdivp st, st(2)
+ fdivrp st, st
+ fdivrp st, st(1)
+ fdivrp st, st(2)
+sub_i:
+ fsubp st, st
+ fsubp st, st(1)
+ fsubp st, st(2)
+ fsubrp st, st
+ fsubrp st, st(1)
+ fsubrp st, st(2)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -40,6 +40,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
set ASFLAGS "$ASFLAGS --32"
run_list_test "float" "-al -mmnemonic=att"
+ run_list_test "fsubp" "-al"
run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc"
run_list_test "inval" "-al"
run_list_test "inval-16" "-al"
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -632,7 +632,7 @@ fsubp, 2, 0xdee0, None, 2, CpuFP, ShortF
fsubp, 1, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
fsubp, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
fsubp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
-fsubp, 2, 0xdee9, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
+fsubp, 2, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
fsubp, 2, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
fsubp, 1, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
fsubp, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }