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Re: [PATCH 2/2] x86: derive DispN from BaseIndex
On Wed, Nov 29, 2017 at 6:21 AM, Jan Beulich <JBeulich@suse.com> wrote:
> x86: derive DispN from BaseIndex
>
> BaseIndex implies - with the exception of string instructions the
> optional presence of a displacement. This is almost completely uniform
> for all instructions (the sole exception being MPX ones, which don't
> allow 16-bit addressing and hence Disp16), so there's no point in
> explicitly stating this in the main opcode table. Drop those explict
> specifications in favor of adding logic to i386-gen, shrinking the
> table size quite a bit and hence making it more readable.
>
> The opcodes/i386-tbl.h changes are due to a few cases where pointless
> Disp* still hadn't been removed from their insns.
>
> opcodes/
> 2017-11-29 Jan Beulich <jbeulich@suse.com>
>
> * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
> New.
> (output_cpu_flags): Update active_cpu_flags.
> (process_i386_opcode_modifier): Update active_isstring.
> (output_operand_type): Rename "macro" parameter to "stage",
> changing its type.
> (process_i386_operand_type): Likewise. Track presence of
> BaseIndex and emit DispN accordingly.
> (output_i386_opcode, process_i386_registers,
> process_i386_initializers): Adjust calls to
> process_i386_operand_type() for its changed parameter type.
> * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
> all insns operands having BaseIndex set.
> * i386-tbl.h: Re-generate.
> ---
> For readability and to meet size constraints I've removed not only the
> re-generated bits, but also the purely mechanical i386-opc.tbl changes
> from the inline patch. The compressed attachment contains them, though.
>
OK if there are no regressions on i686 and x86-64.
Thanks.
--
H.J.