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Re: [PATCH 3/6] Enable Intel VAES instructions
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "Igor V Tsimbalist" <igor dot v dot tsimbalist at intel dot com>
- Cc: "Hongjiu Lu" <hongjiu dot lu at intel dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Mon, 20 Nov 2017 01:13:37 -0700
- Subject: Re: [PATCH 3/6] Enable Intel VAES instructions
- Authentication-results: sourceware.org; auth=none
- References: <D511F25789BA7F4EBA64C8A63891A00291F464AA@IRSMSX102.ger.corp.intel.com>
>>> On 21.10.17 at 11:19, <igor.v.tsimbalist@intel.com> wrote:
>--- /dev/null
>+++ b/gas/testsuite/gas/i386/avx512f_vaes-intel.d
>@@ -0,0 +1,36 @@
>+#as:
>+#objdump: -dw -Mintel
>+#name: i386 AVX512F/VAES insns (Intel disassembly)
>+#source: avx512f_vaes.s
>+
>+.*: +file format .*
>+
>+
>+Disassembly of section \.text:
>+
>+00000000 <_start>:
>+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de f4[ ]*vaesdec zmm6,zmm5,zmm4
>+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b4 f4 c0 1d fe ff[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
>+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 de b2 c0 1f 00 00[ ]*vaesdec zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
Either the Disp32 encodings here and elsewhere are wrong (and
the opcode table entries lack Disp8MemShift attributes) or ...
>--- /dev/null
>+++ b/gas/testsuite/gas/i386/avx512f_vaes-wig.s
>@@ -0,0 +1,37 @@
>+# Check 32bit AVX512F,VAES WIG instructions
>+
>+ .allow_index_reg
>+ .text
>+_start:
>+ vaesdec %zmm4, %zmm5, %zmm6 # AVX512F,VAES
>+ vaesdec -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,VAES
>+ vaesdec 8128(%edx), %zmm5, %zmm6 # AVX512F,VAES Disp8
... Disp8 comments like this one are wrong. I've again noticed
this in the context of verifying the "Disp8MemShift != 0 if and
only if Vec_Disp8 set for the memory operand" equivalence.
Jan