RE: [PUSHED] opcodes/arc: Fix incorrect insn_class for some nps insns

[Claudiu Zissulescu <Claudiu dot Zissulescu at synopsys dot com>]

Thank you Andrew,
Claudiu

> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Tuesday, November 07, 2017 9:34 PM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> Andrew Burgess <andrew.burgess@embecosm.com>
> Subject: [PUSHED] opcodes/arc: Fix incorrect insn_class for some nps insns
> 
> Minor build warning fix for nps400 opcodes, pushed as obvious.
> 
> Thanks,
> Andrew
> 
> --
> 
> A small number of NPS400 instruction incorrectly used NONE as an
> insn_class_t, which would trigger a build warning.  Fixed by changing to
> MISC.
> 
> opcodes/ChangeLog:
> 
> 	* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
> ---
>  opcodes/ChangeLog        | 4 ++++
>  opcodes/arc-nps400-tbl.h | 8 ++++----
>  2 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
> index a40ee75a435..15ef692f0a1 100644
> --- a/opcodes/arc-nps400-tbl.h
> +++ b/opcodes/arc-nps400-tbl.h
> @@ -980,13 +980,13 @@ ASRI_LIKE (0x4, C_NPS_GIC)
>  /* Atomic Operations.  */
> 
>  /* exc<.di><.f> a,a,[xa:b] */
> -{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> +{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> 
>  /* exc<.di><.f> a,a,[sd:b] */
> -{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> +{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> 
>  /* exc<.di><.f> a,a,[xd:b] */
> -{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> +{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON,
> NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
> 
>  /* exc<.di><.f> a,a,[b] */
> -{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, {
> C_DI14, C_NPS_F }},
> +{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, {
> NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, {
> C_DI14, C_NPS_F }},
> --
> 2.13.3