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[PATCH][GAS][AArch64] Add new encoding type macros for Armv8.4-a [Patch (3/6)]
- From: Tamar Christina <tamar dot christina at arm dot com>
- To: binutils at sourceware dot org
- Cc: nd at arm dot com, Richard dot Earnshaw at arm dot com, marcus dot shawcroft at arm dot com
- Date: Wed, 8 Nov 2017 10:12:15 +0000
- Subject: [PATCH][GAS][AArch64] Add new encoding type macros for Armv8.4-a [Patch (3/6)]
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Hi All,
This patch adds the operand encoding types for the new Armv8.2-a back-ported instructions.
These are to be used later when the new instructions are added.
Checked with check-gas on aarch64-none-elf and no regressions.
Ok for Trunk?
Ps. I do not have commit access so if OK can someone apply for me?
Thanks,
Tamar
opcodes/
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
(QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
(QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
(QL_STLW, QL_STLX): New.
--
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5ebd788e1f3e5340d06163e1b4022dda95629003..41f7275bf0883825b7bc4036021f01c0e5587fec 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1995,6 +1995,96 @@
QLF3(V_2S, V_8B, S_B),\
QLF3(V_4S, V_16B, S_B),\
}
+
+/* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D. */
+#define QL_SHA512UPT \
+{ \
+ QLF3(S_Q, S_Q, V_2D), \
+}
+
+/* e.g. SHA512SU0 <Vd.2D>, <Vn>.2D. */
+#define QL_V2SAME2D \
+{ \
+ QLF2(V_2D, V_2D), \
+}
+
+/* e.g. SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D>. */
+#define QL_V3SAME2D \
+{ \
+ QLF3(V_2D, V_2D, V_2D), \
+}
+
+/* e.g. EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B. */
+#define QL_V4SAME16B \
+{ \
+ QLF4(V_16B, V_16B, V_16B, V_16B), \
+}
+
+/* e.g. SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S. */
+#define QL_V4SAME4S \
+{ \
+ QLF4(V_4S, V_4S, V_4S, V_4S), \
+}
+
+/* e.g. XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>. */
+#define QL_XAR \
+{ \
+ QLF4(V_2D, V_2D, V_2D, imm_0_63), \
+}
+
+/* e.g. SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]. */
+#define QL_SM3TT \
+{ \
+ QLF3(V_4S, V_4S, S_S),\
+}
+
+/* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.2H. */
+#define QL_V3FML2S \
+{ \
+ QLF3(V_2S, V_2H, V_2H),\
+}
+
+/* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.4H. */
+#define QL_V3FML4S \
+{ \
+ QLF3(V_4S, V_4H, V_4H),\
+}
+
+/* e.g. FMLAL <Vd>.2S, <Vn>.2H, <Vm>.H[<index>]. */
+#define QL_V2FML2S \
+{ \
+ QLF3(V_2S, V_2H, S_H),\
+}
+
+/* e.g. FMLAL <Vd>.4S, <Vn>.4H, <Vm>.H[<index>]. */
+#define QL_V2FML4S \
+{ \
+ QLF3(V_4S, V_4H, S_H),\
+}
+
+/* e.g. RMIF <Xn>, #<shift>, #<mask>. */
+#define QL_RMIF \
+{ \
+ QLF3(X, imm_0_63, imm_0_15),\
+}
+
+/* e.g. SETF8 <Wn>. */
+#define QL_SETF \
+{ \
+ QLF1(W), \
+}
+
+/* e.g. STLURB <Wt>, [<Xn|SP>{,#<simm>}]. */
+#define QL_STLW \
+{ \
+ QLF2(W, NIL), \
+}
+
+/* e.g. STLURB <Xt>, [<Xn|SP>{,#<simm>}]. */
+#define QL_STLX \
+{ \
+ QLF2(X, NIL), \
+}
/* Opcode table. */