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Re: VLE load/store multiple instructions
- From: Alexander Fedotov <alfedotov at gmail dot com>
- To: Peter Bergner <bergner at vnet dot ibm dot com>
- Cc: Alan Modra <amodra at gmail dot com>, binutils at sourceware dot org
- Date: Sat, 30 Sep 2017 00:42:32 +0300
- Subject: Re: VLE load/store multiple instructions
- Authentication-results: sourceware.org; auth=none
- References: <CAN8C2CoDGGaHJa5=G-g_oe9hSX96Grk5_--uLfguDr7iZxxY4A@mail.gmail.com> <20170927040003.GD25070@bubble.grove.modra.org> <CAN8C2CoT=i3B_Gr+kL5U0geJJJZCrwjYOKsmaygASSjZQ9o3yw@mail.gmail.com> <ad0ca90d-bc03-6a28-e288-1984fb02caee@vnet.ibm.com>
Updated patch: added ChangeLogs and fixed newline warning.
> I'll note that having fixed offsets in your file will make adding or
> removing lines "harder" later, in that you'll have to update the offsets
> for every line after the one you add or delete. Also, is it possible
> one can use VLE in either Big Endian or Little Endian mode?
I suspect that it will never be updated ;)
VLE is Big Endian only.
> If e_lmvgprw is the more common usage over e_ldmvgprw, which your
> comment above seems to imply, then you'll want to add it above
> e_ldmvgprw, rather than after it.
I don't want to change default behavior because somebody might have
existing external tests.
Anyway, Peter, thank you for your comments :)
Alex
On Sat, Sep 30, 2017 at 12:26 AM, Peter Bergner <bergner@vnet.ibm.com> wrote:
> On 9/29/17 3:46 PM, Alexander Fedotov wrote:
>> +00000000 <prolog>:
>> + 0: 18 81 11 00 e_stmvsrrw 0\(r1\)
>> + 4: 18 22 11 04 e_stmvsprw 4\(r2\)
>> + 8: 18 03 11 08 e_stmvgprw 8\(r3\)
>> + c: 18 a4 11 0c e_stmvcsrrw 12\(r4\)
>> + 10: 18 c5 11 10 e_stmvdsrrw 16\(r5\)
>> +00000014 <epilog>:
>> + 14: 18 26 10 14 e_ldmvsprw 20\(r6\)
>> + 18: 18 07 10 18 e_ldmvgprw 24\(r7\)
>> + 1c: 18 88 10 1c e_ldmvsrrw 28\(r8\)
>> + 20: 18 a9 10 20 e_ldmvcsrrw 32\(r9\)
>> + 24: 18 ca 10 24 e_ldmvdsrrw 36\(r10\)
>> +00000028 <epilog_alt>:
>> + 28: 18 2b 10 28 e_ldmvsprw 40\(r11\)
>> + 2c: 18 0c 10 2c e_ldmvgprw 44\(r12\)
>> + 30: 18 8d 10 30 e_ldmvsrrw 48\(r13\)
>> + 34: 18 ae 10 34 e_ldmvcsrrw 52\(r14\)
>> + 38: 18 cf 10 38 e_ldmvdsrrw 56\(r15\)
>> \ No newline at end of file
>
> I'll note that having fixed offsets in your file will make adding or
> removing lines "harder" later, in that you'll have to update the offsets
> for every line after the one you add or delete. Also, is it possible
> one can use VLE in either Big Endian or Little Endian mode? If so, your
> fixed instruction hex values will only match one of them. If you look
> at what we do in power9.d, you'll see we match offsets with ".*" and
> we allow matching with either BE or LE instruction encodings, so our
> tests work on both BE and LE. For example:
>
> .*: (7d a3 04 74|74 04 a3 7d) cnttzd r3,r13
> .*: (7d c4 04 75|75 04 c4 7d) cnttzd\. r4,r14
> .*: (7d e5 04 34|34 04 e5 7d) cnttzw r5,r15
> .*: (7e 06 04 35|35 04 06 7e) cnttzw\. r6,r16
> .*: (7d 54 ae 12|12 ae 54 7d) modsd r10,r20,r21
> .*: (7d 75 b6 16|16 b6 75 7d) modsw r11,r21,r22
>
> Just a friendly suggestion, so take or ignore it. :-)
>
>
>>>> In current PPC opcodes we have only e_ldm*. But it seems that a lot of
>>>> developers uses e_lm* in their software and it fails with GAS. Other
>>>> compilers also recognizes only e_lm*.
>
> ...
>
>> {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
>> +{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
>
> If e_lmvgprw is the more common usage over e_ldmvgprw, which your
> comment above seems to imply, then you'll want to add it above
> e_ldmvgprw, rather than after it. That way, objdump will disassemble
> the instruction to e_lmvgprw rather than e_ldmvgprw.
>
>
> Peter
>
--
Best regards,
AF
From 13312ebb96ee064ce18836dbc084ead71669d265 Mon Sep 17 00:00:00 2001
From: Alexander Fedotov <alfedotov@gmail.com>
Date: Sat, 30 Sep 2017 00:32:26 +0300
Subject: [PATCH] add aliases VLE load multiple instructions
---
gas/ChangeLog | 8 ++++++++
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/vle-mult-ld-st-insns.d | 26 ++++++++++++++++++++++++
gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s | 30 ++++++++++++++++++++++++++++
opcodes/ChangeLog | 6 ++++++
opcodes/ppc-opc.c | 5 +++++
6 files changed, 76 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/vle-mult-ld-st-insns.d
create mode 100644 gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s
diff --git a/gas/ChangeLog b/gas/ChangeLog
index acf75a9..758b099 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2017-09-29 Alexander Fedotov <alfedotov@gmail.com>
+
+ * testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
+ support for the VLE multiple load/store instructions.
+ * testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
+ driver.
+ * testsuite/gas/ppc/ppc.exp: Run it.
+
2017-09-27 Nick Clifton <nickc@redhat.com>
PR 22179
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cdcd8a1..b12fbd3 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -60,6 +60,7 @@ if { [istarget powerpc*-*-*] } then {
run_dump_test "vle-simple-4"
run_dump_test "vle-simple-5"
run_dump_test "vle-simple-6"
+ run_dump_test "vle-mult-ld-st-insns"
#fail expected until get_powerpc_dialect() patch not applied
setup_xfail "*-*-*"
diff --git a/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.d b/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.d
new file mode 100644
index 0000000..bac4399
--- /dev/null
+++ b/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.d
@@ -0,0 +1,26 @@
+#as: -a32 -mvle -mregnames
+#objdump: -dr -Mvle
+#name: VLE Instructions for improving interrupt handler efficiency
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <prolog>:
+ 0: 18 81 11 00 e_stmvsrrw 0\(r1\)
+ 4: 18 22 11 04 e_stmvsprw 4\(r2\)
+ 8: 18 03 11 08 e_stmvgprw 8\(r3\)
+ c: 18 a4 11 0c e_stmvcsrrw 12\(r4\)
+ 10: 18 c5 11 10 e_stmvdsrrw 16\(r5\)
+00000014 <epilog>:
+ 14: 18 26 10 14 e_ldmvsprw 20\(r6\)
+ 18: 18 07 10 18 e_ldmvgprw 24\(r7\)
+ 1c: 18 88 10 1c e_ldmvsrrw 28\(r8\)
+ 20: 18 a9 10 20 e_ldmvcsrrw 32\(r9\)
+ 24: 18 ca 10 24 e_ldmvdsrrw 36\(r10\)
+00000028 <epilog_alt>:
+ 28: 18 2b 10 28 e_ldmvsprw 40\(r11\)
+ 2c: 18 0c 10 2c e_ldmvgprw 44\(r12\)
+ 30: 18 8d 10 30 e_ldmvsrrw 48\(r13\)
+ 34: 18 ae 10 34 e_ldmvcsrrw 52\(r14\)
+ 38: 18 cf 10 38 e_ldmvdsrrw 56\(r15\)
diff --git a/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s b/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s
new file mode 100644
index 0000000..b635e32
--- /dev/null
+++ b/gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s
@@ -0,0 +1,30 @@
+# New VLE Instructions for Improving Interrupt Handler Efficiency (EB696.pdf)
+
+# e_lmvgprw, e_stmvgprw - load/store multiple volatile GPRs (r0, r3:r12)
+# e_lmvsprw, e_stmvsprw - load/store multiple volatile SPRs (CR, LR, CTR, and XER)
+# e_lmvsrrw, e_stmvsrrw - load/store multiple volatile SRRs (SRR0, SRR1)
+# e_lmvcsrrw, e_stmvcsrrw - load/store multiple volatile CSRRs (CSRR0, CSRR1)
+# e_lmvdsrrw, e_stmvdsrrw - load/store multiple volatile DSRRs (DSRR0, DSRR1)
+# e_lmvmcsrrw, e_stmvmcsrrw - load/store multiple volatile MCSRRs (MCSRR0, MCSRR1)
+
+ .text
+prolog:
+ e_stmvsrrw 0x00 (r1)
+ e_stmvsprw 0x04 (r2)
+ e_stmvgprw 0x08 (r3)
+ e_stmvcsrrw 0x0c (r4)
+ e_stmvdsrrw 0x10 (r5)
+
+epilog:
+ e_ldmvsprw 0x14 (r6)
+ e_ldmvgprw 0x18 (r7)
+ e_ldmvsrrw 0x1c (r8)
+ e_ldmvcsrrw 0x20 (r9)
+ e_ldmvdsrrw 0x24 (r10)
+
+epilog_alt:
+ e_lmvsprw 0x28 (r11)
+ e_lmvgprw 0x2c (r12)
+ e_lmvsrrw 0x30 (r13)
+ e_lmvcsrrw 0x34 (r14)
+ e_lmvdsrrw 0x38 (r15)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9280b2c..acddaf6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-09-29 Alexander Fedotov <alfedotov@gmail.com>
+
+ * ppc-opc.c (vle_opcodes): Add e_ldmvsprw, e_lmvgprw,
+ e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as aliases for corresponding
+ e_ldm* instructions.
+
2017-09-27 Nick Clifton <nickc@redhat.com>
PR 22179
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 5edb1ad..6de277a 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -8316,14 +8316,19 @@ const struct powerpc_opcode vle_opcodes[] = {
{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
--
2.7.4