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Re: [PATCH] PowerPC VLE changes
This patch separates EFS2 instructions from SPE2
Forgot to say about of patches apply order:
1. 2.28-vle.patch
2. 2.28-lsp.patch
3. 2.28-spe2.patch
4. 2.28-efs2.patch
Alex
On Fri, Jun 23, 2017 at 11:56 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> This patch for SPE2 instructions support
>
>
> On Fri, Jun 23, 2017 at 11:54 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
>> This patch for LSP instructions support
>>
>> On Fri, Jun 23, 2017 at 11:51 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
>>> Hello Alan
>>>
>>> We want to upstream our changes for VLE, LSP, SPE2 and other stuff.
>>> All of them are based on 2.28 release.
>>>
>>> Best regards,
>>> Alexander
>>
>>
>>
>> --
>> Best regards,
>> AF
>
>
>
> --
> Best regards,
> AF
--
Best regards,
AF
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.d binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.d 2017-06-23 23:58:43.111735000 +0300
@@ -0,0 +1,19 @@
+#as: -mvle
+#objdump: -d -Mvle -Mefs2
+#name: Validate EFS2 instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 01 12 b0 efsmax r0,r1,r2
+ 4: 10 01 12 b1 efsmin r0,r1,r2
+ 8: 10 01 12 b8 efdmax r0,r1,r2
+ c: 10 01 12 b9 efdmin r0,r1,r2
+ 10: 10 01 02 c7 efssqrt r0,r1
+ 14: 10 04 12 d1 efscfh r0,r2
+ 18: 10 04 12 d5 efscth r0,r2
+ 1c: 10 01 02 e7 efdsqrt r0,r1
+ 20: 10 04 12 f1 efdcfh r0,r2
+ 24: 10 04 12 f5 efdcth r0,r2
\ No newline at end of file
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.s binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.s
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs2.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs2.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,18 @@
+# PA EFS2 instructions in accordance with EFP2_rev.1.4_spec
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+
+ efsmax rD, rA, rB
+ efsmin rD, rA, rB
+ efdmax rD, rA, rB
+ efdmin rD, rA, rB
+ efssqrt rD, rA
+ efscfh rD, rB
+ efscth rD, rB
+ efdsqrt rD, rA
+ efdcfh rD, rB
+ efdcth rD, rB
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.d binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.d 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.d 2017-06-23 23:58:43.111735000 +0300
@@ -0,0 +1,25 @@
+#as: -mvle
+#objdump: -d -Mefs -Mvle -Mefs2
+#name: Validate EFS instructions
+
+.*: +file format elf.*-powerpc.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 10 00 12 d1 efscfsi r0,r2
+ 4: 10 00 12 d5 efsctsi r0,r2
+ 8: 10 00 12 f1 efdcfsi r0,r2
+ c: 10 00 12 f5 efdctsi r0,r2
+ 10: 10 01 12 c2 efsmadd r0,r1,r2
+ 14: 10 01 12 c3 efsmsub r0,r1,r2
+ 18: 10 01 12 ca efsnmadd r0,r1,r2
+ 1c: 10 01 12 cb efsnmsub r0,r1,r2
+ 20: 10 01 12 e2 efdmadd r0,r1,r2
+ 24: 10 01 12 e3 efdmsub r0,r1,r2
+ 28: 10 01 12 ea efdnmadd r0,r1,r2
+ 2c: 10 01 12 eb efdnmsub r0,r1,r2
+ 30: 10 01 12 f0 efdcfuid r0,r2
+ 34: 10 01 12 f1 efdcfsid r0,r2
+ 38: 10 01 12 f8 efdctuidz r0,r2
+ 3c: 10 01 12 fa efdctsidz r0,r2
\ No newline at end of file
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.s binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.s
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/efs.s 1970-01-01 03:00:00.000000000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/efs.s 2017-06-23 17:44:50.947719000 +0300
@@ -0,0 +1,33 @@
+# PA EFS 1.0 and 1.1 instructions
+# CMPE200GCC-62
+ .section ".text"
+
+ .equ rA,1
+ .equ rB,2
+ .equ rD,0
+
+;# EFS 1.0 instructions in accordance with EFP2_rev.1.4_spec
+ efscfsi rD, rB
+ efsctsi rD, rB
+ efdcfsi rD, rB
+ efdctsi rD, rB
+
+;# EFS 1.1 instructions in accordance with EFP2_rev.1.4_spec
+ efsmadd rD, rA, rB
+ efsmsub rD, rA, rB
+ efsnmadd rD, rA, rB
+ efsnmsub rD, rA, rB
+ efdmadd rD, rA, rB
+ efdmsub rD, rA, rB
+ efdnmadd rD, rA, rB
+ efdnmsub rD, rA, rB
+
+;# moved EFS opcodes in accordance with EFP2_rev.1.4_spec
+ efdcfuid rD, rB
+ efdcfsid rD, rB
+ efdctuidz rD, rB
+ efdctsidz rD, rB
+
+
+
+
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp binutils-2.28-efs2/gas/testsuite/gas/ppc/ppc.exp
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/ppc.exp 2017-06-23 17:54:18.847627054 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/ppc.exp 2017-06-24 00:04:26.643735001 +0300
@@ -61,6 +61,8 @@
run_dump_test "vle-simple-6"
run_dump_test "lsp"
run_dump_test "lsp-checks"
+ run_dump_test "efs"
+ run_dump_test "efs2"
run_dump_test "spe2"
run_dump_test "spe2-checks"
run_dump_test "spe"
diff -ruN binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d binutils-2.28-efs2/gas/testsuite/gas/ppc/spe2.d
--- binutils-2.28-spe2/gas/testsuite/gas/ppc/spe2.d 2017-06-23 17:44:50.951717000 +0300
+++ binutils-2.28-efs2/gas/testsuite/gas/ppc/spe2.d 2017-06-24 00:04:37.627735001 +0300
@@ -1,5 +1,5 @@
#as: -mvle -mspe2
-#objdump: -d -Mspe2
+#objdump: -d -Mspe2 -Mefs2
#name: Validate SPE2 instructions
.*: +file format elf.*-powerpc.*
diff -ruN binutils-2.28-spe2/include/opcode/ppc.h binutils-2.28-efs2/include/opcode/ppc.h
--- binutils-2.28-spe2/include/opcode/ppc.h 2017-06-23 17:55:36.864599055 +0300
+++ binutils-2.28-efs2/include/opcode/ppc.h 2017-06-24 00:05:19.075735001 +0300
@@ -225,6 +225,9 @@
/* Opcode is only supported by Freescale SPE2 APU. */
#define PPC_OPCODE_SPE2 0x4000000000000000ull
+/* Opcode is supported by EFS2. */
+#define PPC_OPCODE_EFS2 0x2000000000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff -ruN binutils-2.28-spe2/opcodes/ppc-dis.c binutils-2.28-efs2/opcodes/ppc-dis.c
--- binutils-2.28-spe2/opcodes/ppc-dis.c 2017-06-23 17:56:52.074975055 +0300
+++ binutils-2.28-efs2/opcodes/ppc-dis.c 2017-06-24 00:05:55.467735001 +0300
@@ -108,7 +108,8 @@
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4 | PPC_OPCODE_VLE),
+ | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4 | PPC_OPCODE_VLE
+ | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
0 },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
@@ -145,6 +146,8 @@
0 },
{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
0 },
+ { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
+ 0 },
{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
@@ -212,7 +215,7 @@
0 },
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
PPC_OPCODE_SPE },
- { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_SPE,
+ { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
PPC_OPCODE_SPE2 },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
@@ -220,7 +223,7 @@
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_LSP | PPC_OPCODE_SPE2),
+ | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
diff -ruN binutils-2.28-spe2/opcodes/ppc-opc.c binutils-2.28-efs2/opcodes/ppc-opc.c
--- binutils-2.28-spe2/opcodes/ppc-opc.c 2017-06-23 23:38:05.522746700 +0300
+++ binutils-2.28-efs2/opcodes/ppc-opc.c 2017-06-24 00:23:55.371735001 +0300
@@ -3252,6 +3252,7 @@
#define PPCSPE2 PPC_OPCODE_SPE2
#define PPCISEL PPC_OPCODE_ISEL
#define PPCEFS PPC_OPCODE_EFS
+#define PPCEFS2 PPC_OPCODE_EFS2
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCTMR PPC_OPCODE_TMR
@@ -3601,6 +3602,7 @@
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
@@ -3614,10 +3616,12 @@
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
+{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
+{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
@@ -3627,19 +3631,43 @@
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
+{"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
+{"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
+{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
+{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
+{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
+{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
+{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
@@ -3647,10 +3675,12 @@
{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
@@ -3662,30 +3692,41 @@
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
-{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}},
+{"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}},
{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
+{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}},
{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
-{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}},
+{"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
+{"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}},
{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
+{"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
+{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
-{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
-{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}},
+{"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}},
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
@@ -8672,42 +8713,6 @@
{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}},
-{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"evfsmax", VX (4, 672), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmin", VX (4, 673), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddsub", VX (4, 674), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubadd", VX (4, 675), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssum", VX (4, 676), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsdiff", VX (4, 677), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssumdiff", VX (4, 678), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsdiffsum", VX (4, 679), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddx", VX (4, 680), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubx", VX (4, 681), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsaddsubx", VX (4, 682), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfssubaddx", VX (4, 683), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmulx", VX (4, 684), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmule", VX (4, 686), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"evfsmulo", VX (4, 687), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmax", VX (4, 688), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmin", VX (4, 689), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efdmax", VX (4, 696), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efdmin", VX (4, 697), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
-{"efsmadd", VX (4, 706), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efsmsub", VX (4, 707), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"efsnmadd", VX (4, 714), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efsnmsub", VX (4, 715), VX_MASK, PPCSPE2, 0, {RS, RA, RB}},
-{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efdmadd", VX (4, 738), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdmsub", VX (4, 739), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}},
-{"efdnmadd", VX (4, 746), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdnmsub", VX (4, 747), VX_MASK, PPCSPE2, E500|E500MC, {RD, RA, RB}},
-{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
-{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCSPE2, 0, {RD, RB}},
{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}},
{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},