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Re: [PATCH] X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly
On Tue, May 30, 2017 at 02:04:06AM -0600, Jan Beulich wrote:
> But that still permits for the shift count to be larger than the bits
> in the operand for 8- and 16-bit operands.
Hm, lemme guess, the countMask thing is an afterthought when they did
32-bit. If it had to be consistent, it should've been done for the
smaller operands too. :-\
> However, I still don't see how the wording in the SDM could really be
> taken to mean there's a difference between SAL and SHL: For one,
> it also says "The shift arithmetic left (SAL) and shift logical left (SHL)
> instructions perform the same operation". And then both being
> specified as encoded by /4 there can't possibly be any difference.
If I had to guess it probably is even the one and same instruction for
/4 and /6 that the hardware executes.
> Imo the "Flags Affected" section really should be making SAR the
> exception rather than SHL and SHR.
Do you mean this:
"The SHR instruction clears the most significant bit (see Figure 7-8 in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1); the SAR instruction sets or clears the most significant bit
to correspond to the sign (most significant bit) of the original value
in the destination operand."
> But especially the instruction pages of the SDM are well known anyway
> to be full of not very precise statements ...
It's better they have pseudocode too. :)
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