This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly


>>> On 30.05.17 at 09:42, <bp@suse.de> wrote:
> On Mon, May 29, 2017 at 03:35:34PM -0700, H.J. Lu wrote:
>> From IA SDM:
>> 
>> The CF flag contains the value of the last bit shifted out of the
>> destination operand; it is undefined for SHL and SHR
>> instructions where the count is greater than or equal to the size (in
>> bits) of the destination operand. The OF flag is
>> affected only for 1-bit shifts (see “Description” above); otherwise,
>> it is undefined. The SF, ZF, and PF flags are set
>> according to the result. If the count is 0, the flags are not
>> affected. For a non-zero count, the AF flag is undefined.
>> 
>> What does AMD manual say?
> 
> Well, I *think* that's a mistake in the SDM - sounds like they forgot
> to remove that sentence about the undefined bit in CF because it says
> earlier:
> 
> "The destination operand can be a register or a memory location. The
> count operand can be an immediate value or the CL register. The count is
> masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The
> count range is limited to 0 to 31 (or 63 if 64-bit mode and REX.W is
> used)."
> 
> and thus it contradicts itself here as the count can't really get
> greater than or equal.
> 
> So basically the hardware limits the shift count to only valid sizes.
> 
> That's also in the pseudo code:
> 
> 	IF 64-Bit Mode and using REX.W
> 	THEN
> 		countMASK ← 3FH;
> 	ELSE
> 		countMASK ← 1FH;
> 	FI
> 
> 	tempCOUNT ← (COUNT AND countMASK);

But that still permits for the shift count to be larger than the bits
in the operand for 8- and 16-bit operands.

However, I still don't see how the wording in the SDM could really be
taken to mean there's a difference between SAL and SHL: For one,
it also says "The shift arithmetic left (SAL) and shift logical left (SHL)
instructions perform the same operation". And then both being
specified as encoded by /4 there can't possibly be any difference.
Imo the "Flags Affected" section really should be making SAR the
exception rather than SHL and SHR. But especially the instruction
pages of the SDM are well known anyway to be full of not very
precise statements ...

Jan


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]