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Re: [PATCH] X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly
On Mon, May 29, 2017 at 03:35:34PM -0700, H.J. Lu wrote:
> From IA SDM:
> The CF flag contains the value of the last bit shifted out of the
> destination operand; it is undefined for SHL and SHR
> instructions where the count is greater than or equal to the size (in
> bits) of the destination operand. The OF flag is
> affected only for 1-bit shifts (see “Description” above); otherwise,
> it is undefined. The SF, ZF, and PF flags are set
> according to the result. If the count is 0, the flags are not
> affected. For a non-zero count, the AF flag is undefined.
> What does AMD manual say?
Well, I *think* that's a mistake in the SDM - sounds like they forgot
to remove that sentence about the undefined bit in CF because it says
"The destination operand can be a register or a memory location. The
count operand can be an immediate value or the CL register. The count is
masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The
count range is limited to 0 to 31 (or 63 if 64-bit mode and REX.W is
and thus it contradicts itself here as the count can't really get
greater than or equal.
So basically the hardware limits the shift count to only valid sizes.
That's also in the pseudo code:
IF 64-Bit Mode and using REX.W
countMASK ← 3FH;
countMASK ← 1FH;
tempCOUNT ← (COUNT AND countMASK);
Otherwise, we would've heard already about differences between those
instructions and would have explicit assembler support, as Jan says.
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