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[AArch64] Additional SVE instructions
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: binutils at sourceware dot org
- Cc: richard dot earnshaw at arm dot com
- Date: Fri, 24 Feb 2017 15:06:39 +0000
- Subject: [AArch64] Additional SVE instructions
- Authentication-results: sourceware.org; auth=none
This patch supports some additions to the SVE architecture prior to
its public release.
Tested on aarch64-linux-gnu. OK for trunk and 2.28?
Thanks,
Richard
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 46b1e70..969c18c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -837,7 +837,7 @@ elt_size:
element_size = 64;
break;
case 'q':
- if (width == 1)
+ if (reg_type == REG_TYPE_ZN || width == 1)
{
type = NT_q;
element_size = 128;
@@ -5431,6 +5431,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->qualifier = AARCH64_OPND_QLF_S_D;
break;
+ case AARCH64_OPND_SVE_Zm3_INDEX:
+ case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
reg_type = REG_TYPE_ZN;
goto vector_reg_index;
@@ -5567,6 +5570,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_IMM_ROT1:
case AARCH64_OPND_IMM_ROT2:
case AARCH64_OPND_IMM_ROT3:
+ case AARCH64_OPND_SVE_IMM_ROT1:
+ case AARCH64_OPND_SVE_IMM_ROT2:
po_imm_nc_or_fail ();
info->imm.value = val;
break;
@@ -6090,6 +6095,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
/* No qualifier. */
break;
+ case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
@@ -8436,8 +8442,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
AARCH64_ARCH_NONE},
{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
- AARCH64_FEATURE (AARCH64_FEATURE_FP
- | AARCH64_FEATURE_SIMD, 0)},
+ AARCH64_FEATURE (AARCH64_FEATURE_F16
+ | AARCH64_FEATURE_SIMD
+ | AARCH64_FEATURE_COMPNUM, 0)},
{"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
AARCH64_FEATURE (AARCH64_FEATURE_F16
| AARCH64_FEATURE_SIMD, 0)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 71d8072..f5be0d4 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -158,8 +158,9 @@ automatically cause those extensions to be disabled.
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
-@item @code{sve} @tab ARMv8-A @tab No
- @tab Enable the Scalable Vector Extensions. This implies @code{simd}.
+@item @code{sve} @tab ARMv8.2-A @tab No
+ @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
+ @code{simd} and @code{compnum}.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 58739b3..6e614c3 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -2,13 +2,15 @@
.*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
.*: Error: operand mismatch -- `fmov z1,#1\.0'
.*: Info: did you mean this\?
-.*: Info: fmov z1\.s, #1\.000000000000000000e\+00
+.*: Info: fmov z1\.h, #1\.000000000000000000e\+00
.*: Info: other valid variant\(s\):
+.*: Info: fmov z1\.s, #1\.000000000000000000e\+00
.*: Info: fmov z1\.d, #1\.000000000000000000e\+00
.*: Error: operand mismatch -- `fmov z1,#0\.0'
.*: Info: did you mean this\?
-.*: Info: fmov z1\.s, #0\.0
+.*: Info: fmov z1\.h, #0\.0
.*: Info: other valid variant\(s\):
+.*: Info: fmov z1\.s, #0\.0
.*: Info: fmov z1\.d, #0\.0
.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/'
.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/,z2\.s'
@@ -144,6 +146,7 @@
.*: Info: mov z0\.h, h0
.*: Info: mov z0\.s, s0
.*: Info: mov z0\.d, d0
+.*: Info: mov z0\.q, q0
.*: Error: operand mismatch -- `mov z0,z1'
.*: Info: did you mean this\?
.*: Info: mov z0\.d, z1\.d
@@ -942,3 +945,266 @@
.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[-1\]'
.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[8\]'
.*: Error: constant expression required at operand 2 -- `dup z0\.d,z1\.d\[x0\]'
+.*: Error: operand mismatch -- `fabd z0\.b,p0/m,z0\.b,z0\.b'
+.*: Info: did you mean this\?
+.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
+.*: Info: other valid variant\(s\):
+.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
+.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
+.*: Error: operand mismatch -- `fabd z0\.q,p0/m,z0\.q,z0\.q'
+.*: Info: did you mean this\?
+.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
+.*: Info: other valid variant\(s\):
+.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
+.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
+.*: Error: operand mismatch -- `fcadd z0\.b,p0/m,z0\.b,z0\.b,#90'
+.*: Info: did you mean this\?
+.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-180'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-90'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#0'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#89'
+.*: Error: unexpected characters following instruction at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#180'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#360'
+.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#450'
+.*: Error: operand mismatch -- `fcadd z0\.h,p0/z,z0\.h,z0\.h,#90'
+.*: Info: did you mean this\?
+.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: operand 3 must be the same register as operand 1 -- `fcadd z0\.h,p0/m,z1\.h,z0\.h,#90'
+.*: Error: operand mismatch -- `fcadd z0\.q,p0/m,z0\.q,z0\.q,#90'
+.*: Info: did you mean this\?
+.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: operand mismatch -- `fcmla z0\.b,p0/m,z0\.b,z0\.b,#90'
+.*: Info: did you mean this\?
+.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-180'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-90'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#89'
+.*: Error: unexpected characters following instruction at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#360'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#450'
+.*: Error: operand mismatch -- `fcmla z0\.h,p0/z,z0\.h,z0\.h,#90'
+.*: Info: did you mean this\?
+.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: operand mismatch -- `fcmla z0\.q,p0/m,z0\.q,z0\.q,#90'
+.*: Info: did you mean this\?
+.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: Info: other valid variant\(s\):
+.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: Error: operand mismatch -- `fcmla z0\.b,z1\.b,z2\.b\[0\],#0'
+.*: Info: did you mean this\?
+.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[-1\],#0'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[4\],#0'
+.*: Error: z0-z7 expected at operand 3 -- `fcmla z0\.h,z1\.h,z8\.h\[0\],#0'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-180'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-90'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#89'
+.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#90\.0'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#360'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#450'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[-1\],#0'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[2\],#0'
+.*: Error: z0-z15 expected at operand 3 -- `fcmla z0\.s,z1\.s,z16\.s\[0\],#0'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-180'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-90'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#89'
+.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#90\.0'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#360'
+.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#450'
+.*: Error: operand mismatch -- `fcmla z0\.q,z1\.q,z2\.q\[0\],#0'
+.*: Info: did you mean this\?
+.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
+.*: Error: operand mismatch -- `fmla z0\.b,z1\.b,z2\.b\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[-1\]'
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[8\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.h,z1\.h,z8\.h\[0\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[-1\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[4\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.s,z1\.s,z8\.s\[0\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[-1\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[2\]'
+.*: Error: z0-z15 expected at operand 3 -- `fmla z0\.d,z1\.d,z16\.d\[0\]'
+.*: Error: operand mismatch -- `fmla z0\.q,z1\.q,z2\.q\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: operand mismatch -- `fmls z0\.b,z1\.b,z2\.b\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[-1\]'
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[8\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.h,z1\.h,z8\.h\[0\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[-1\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[4\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.s,z1\.s,z8\.s\[0\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[-1\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[2\]'
+.*: Error: z0-z15 expected at operand 3 -- `fmls z0\.d,z1\.d,z16\.d\[0\]'
+.*: Error: operand mismatch -- `fmls z0\.q,z1\.q,z2\.q\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: operand mismatch -- `fmul z0\.b,z1\.b,z2\.b\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[-1\]'
+.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[8\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.h,z1\.h,z8\.h\[0\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[-1\]'
+.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[4\]'
+.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.s,z1\.s,z8\.s\[0\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[-1\]'
+.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[2\]'
+.*: Error: z0-z15 expected at operand 3 -- `fmul z0\.d,z1\.d,z16\.d\[0\]'
+.*: Error: operand mismatch -- `fmul z0\.q,z1\.q,z2\.q\[0\]'
+.*: Info: did you mean this\?
+.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
+.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0/m,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: p0-p7 expected at operand 2 -- `ld1rqb {z0\.b},p8/z,\[x0,#0\]'
+.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-144\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-15\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-14\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-13\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-12\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-11\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-10\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-9\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-8\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-7\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-6\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-5\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-4\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-3\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-2\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-1\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#1\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#2\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#3\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#4\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#5\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#6\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#7\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#8\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#9\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#10\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#11\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#12\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#13\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#14\]'
+.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#15\]'
+.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#128\]'
+.*: Error: operand mismatch -- `ld1rqb {z0\.h},p0/z,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: operand mismatch -- `ld1rqb {z0\.s},p0/z,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: operand mismatch -- `ld1rqb {z0\.d},p0/z,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: operand mismatch -- `ld1rqb {z0\.q},p0/z,\[x0,#0\]'
+.*: Info: did you mean this\?
+.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,xzr\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#2\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#3\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,xzr,lsl#1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#2\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#3\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,xzr,lsl#2\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#3\]'
+.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,xzr,lsl#3\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#1\]'
+.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#2\]'
+.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b
+.*: Info: other valid variant\(s\):
+.*: Info: sdot z0\.d, z1\.h, z2\.h
+.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.d, z1\.h, z2\.h
+.*: Info: other valid variant\(s\):
+.*: Info: sdot z0\.s, z1\.b, z2\.b
+.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b
+.*: Info: other valid variant\(s\):
+.*: Info: sdot z0\.d, z1\.h, z2\.h
+.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.d, z1\.h, z2\.h
+.*: Info: other valid variant\(s\):
+.*: Info: sdot z0\.s, z1\.b, z2\.b
+.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b\[0\]'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h\[0\]'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s\[0\]'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d\[0\]'
+.*: Info: did you mean this\?
+.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b
+.*: Info: other valid variant\(s\):
+.*: Info: udot z0\.d, z1\.h, z2\.h
+.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.d, z1\.h, z2\.h
+.*: Info: other valid variant\(s\):
+.*: Info: udot z0\.s, z1\.b, z2\.b
+.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b
+.*: Info: other valid variant\(s\):
+.*: Info: udot z0\.d, z1\.h, z2\.h
+.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.d, z1\.h, z2\.h
+.*: Info: other valid variant\(s\):
+.*: Info: udot z0\.s, z1\.b, z2\.b
+.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b\[0\]'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h\[0\]'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s\[0\]'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
+.*: Info: did you mean this\?
+.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index 0912c52..148dbc8 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1161,3 +1161,166 @@
dup z0.d, z1.d[7] // OK
dup z0.d, z1.d[8]
dup z0.d, z1.d[x0]
+
+ fabd z0.b, p0/m, z0.b, z0.b
+ fabd z0.q, p0/m, z0.q, z0.q
+
+ fcadd z0.b, p0/m, z0.b, z0.b, #90
+ fcadd z0.h, p0/m, z0.h, z0.h, #-180
+ fcadd z0.h, p0/m, z0.h, z0.h, #-90
+ fcadd z0.h, p0/m, z0.h, z0.h, #0
+ fcadd z0.h, p0/m, z0.h, z0.h, #89
+ fcadd z0.h, p0/m, z0.h, z0.h, #90.0
+ fcadd z0.h, p0/m, z0.h, z0.h, #180
+ fcadd z0.h, p0/m, z0.h, z0.h, #360
+ fcadd z0.h, p0/m, z0.h, z0.h, #450
+ fcadd z0.h, p0/z, z0.h, z0.h, #90
+ fcadd z0.h, p0/m, z1.h, z0.h, #90
+ fcadd z0.q, p0/m, z0.q, z0.q, #90
+
+ fcmla z0.b, p0/m, z0.b, z0.b, #90
+ fcmla z0.h, p0/m, z0.h, z0.h, #-180
+ fcmla z0.h, p0/m, z0.h, z0.h, #-90
+ fcmla z0.h, p0/m, z0.h, z0.h, #89
+ fcmla z0.h, p0/m, z0.h, z0.h, #90.0
+ fcmla z0.h, p0/m, z0.h, z0.h, #360
+ fcmla z0.h, p0/m, z0.h, z0.h, #450
+ fcmla z0.h, p0/z, z0.h, z0.h, #90
+ fcmla z0.q, p0/m, z0.q, z0.q, #90
+
+ fcmla z0.b, z1.b, z2.b[0], #0
+ fcmla z0.h, z1.h, z2.h[-1], #0
+ fcmla z0.h, z1.h, z2.h[4], #0
+ fcmla z0.h, z1.h, z8.h[0], #0
+ fcmla z0.h, z1.h, z2.h[0], #-180
+ fcmla z0.h, z1.h, z2.h[0], #-90
+ fcmla z0.h, z1.h, z2.h[0], #89
+ fcmla z0.h, z1.h, z2.h[0], #90.0
+ fcmla z0.h, z1.h, z2.h[0], #360
+ fcmla z0.h, z1.h, z2.h[0], #450
+ fcmla z0.s, z1.s, z2.s[-1], #0
+ fcmla z0.s, z1.s, z2.s[2], #0
+ fcmla z0.s, z1.s, z16.s[0], #0
+ fcmla z0.s, z1.s, z2.s[0], #-180
+ fcmla z0.s, z1.s, z2.s[0], #-90
+ fcmla z0.s, z1.s, z2.s[0], #89
+ fcmla z0.s, z1.s, z2.s[0], #90.0
+ fcmla z0.s, z1.s, z2.s[0], #360
+ fcmla z0.s, z1.s, z2.s[0], #450
+ fcmla z0.q, z1.q, z2.q[0], #0
+
+ fmla z0.b, z1.b, z2.b[0]
+ fmla z0.h, z1.h, z2.h[-1]
+ fmla z0.h, z1.h, z2.h[8]
+ fmla z0.h, z1.h, z8.h[0]
+ fmla z0.s, z1.s, z2.s[-1]
+ fmla z0.s, z1.s, z2.s[4]
+ fmla z0.s, z1.s, z8.s[0]
+ fmla z0.d, z1.d, z2.d[-1]
+ fmla z0.d, z1.d, z2.d[2]
+ fmla z0.d, z1.d, z16.d[0]
+ fmla z0.q, z1.q, z2.q[0]
+
+ fmls z0.b, z1.b, z2.b[0]
+ fmls z0.h, z1.h, z2.h[-1]
+ fmls z0.h, z1.h, z2.h[8]
+ fmls z0.h, z1.h, z8.h[0]
+ fmls z0.s, z1.s, z2.s[-1]
+ fmls z0.s, z1.s, z2.s[4]
+ fmls z0.s, z1.s, z8.s[0]
+ fmls z0.d, z1.d, z2.d[-1]
+ fmls z0.d, z1.d, z2.d[2]
+ fmls z0.d, z1.d, z16.d[0]
+ fmls z0.q, z1.q, z2.q[0]
+
+ fmul z0.b, z1.b, z2.b[0]
+ fmul z0.h, z1.h, z2.h[-1]
+ fmul z0.h, z1.h, z2.h[8]
+ fmul z0.h, z1.h, z8.h[0]
+ fmul z0.s, z1.s, z2.s[-1]
+ fmul z0.s, z1.s, z2.s[4]
+ fmul z0.s, z1.s, z8.s[0]
+ fmul z0.d, z1.d, z2.d[-1]
+ fmul z0.d, z1.d, z2.d[2]
+ fmul z0.d, z1.d, z16.d[0]
+ fmul z0.q, z1.q, z2.q[0]
+
+ ld1rqb {z0.b}, p0, [x0, #0]
+ ld1rqb {z0.b}, p0/m, [x0, #0]
+ ld1rqb {z0.b}, p8/z, [x0, #0]
+ ld1rqb {z0.b}, p0/z, [x0, #-144]
+ ld1rqb {z0.b}, p0/z, [x0, #-15]
+ ld1rqb {z0.b}, p0/z, [x0, #-14]
+ ld1rqb {z0.b}, p0/z, [x0, #-13]
+ ld1rqb {z0.b}, p0/z, [x0, #-12]
+ ld1rqb {z0.b}, p0/z, [x0, #-11]
+ ld1rqb {z0.b}, p0/z, [x0, #-10]
+ ld1rqb {z0.b}, p0/z, [x0, #-9]
+ ld1rqb {z0.b}, p0/z, [x0, #-8]
+ ld1rqb {z0.b}, p0/z, [x0, #-7]
+ ld1rqb {z0.b}, p0/z, [x0, #-6]
+ ld1rqb {z0.b}, p0/z, [x0, #-5]
+ ld1rqb {z0.b}, p0/z, [x0, #-4]
+ ld1rqb {z0.b}, p0/z, [x0, #-3]
+ ld1rqb {z0.b}, p0/z, [x0, #-2]
+ ld1rqb {z0.b}, p0/z, [x0, #-1]
+ ld1rqb {z0.b}, p0/z, [x0, #1]
+ ld1rqb {z0.b}, p0/z, [x0, #2]
+ ld1rqb {z0.b}, p0/z, [x0, #3]
+ ld1rqb {z0.b}, p0/z, [x0, #4]
+ ld1rqb {z0.b}, p0/z, [x0, #5]
+ ld1rqb {z0.b}, p0/z, [x0, #6]
+ ld1rqb {z0.b}, p0/z, [x0, #7]
+ ld1rqb {z0.b}, p0/z, [x0, #8]
+ ld1rqb {z0.b}, p0/z, [x0, #9]
+ ld1rqb {z0.b}, p0/z, [x0, #10]
+ ld1rqb {z0.b}, p0/z, [x0, #11]
+ ld1rqb {z0.b}, p0/z, [x0, #12]
+ ld1rqb {z0.b}, p0/z, [x0, #13]
+ ld1rqb {z0.b}, p0/z, [x0, #14]
+ ld1rqb {z0.b}, p0/z, [x0, #15]
+ ld1rqb {z0.b}, p0/z, [x0, #128]
+ ld1rqb {z0.h}, p0/z, [x0, #0]
+ ld1rqb {z0.s}, p0/z, [x0, #0]
+ ld1rqb {z0.d}, p0/z, [x0, #0]
+ ld1rqb {z0.q}, p0/z, [x0, #0]
+
+ ld1rqb {z0.b}, p0/z, [x0, xzr]
+ ld1rqb {z0.b}, p0/z, [x0, x1, lsl #1]
+ ld1rqb {z0.b}, p0/z, [x0, x1, lsl #2]
+ ld1rqb {z0.b}, p0/z, [x0, x1, lsl #3]
+
+ ld1rqh {z0.h}, p0/z, [x0, xzr, lsl #1]
+ ld1rqh {z0.h}, p0/z, [x0, x1]
+ ld1rqh {z0.h}, p0/z, [x0, x1, lsl #2]
+ ld1rqh {z0.h}, p0/z, [x0, x1, lsl #3]
+
+ ld1rqw {z0.s}, p0/z, [x0, xzr, lsl #2]
+ ld1rqw {z0.s}, p0/z, [x0, x1]
+ ld1rqw {z0.s}, p0/z, [x0, x1, lsl #1]
+ ld1rqw {z0.s}, p0/z, [x0, x1, lsl #3]
+
+ ld1rqd {z0.d}, p0/z, [x0, xzr, lsl #3]
+ ld1rqd {z0.d}, p0/z, [x0, x1]
+ ld1rqd {z0.d}, p0/z, [x0, x1, lsl #1]
+ ld1rqd {z0.d}, p0/z, [x0, x1, lsl #2]
+
+ sdot z0.b, z1.b, z2.b
+ sdot z0.h, z1.h, z2.h
+ sdot z0.s, z1.s, z2.s
+ sdot z0.d, z1.d, z2.d
+
+ sdot z0.b, z1.b, z2.b[0]
+ sdot z0.h, z1.h, z2.h[0]
+ sdot z0.s, z1.s, z2.s[0]
+ sdot z0.d, z1.d, z2.d[0]
+
+ udot z0.b, z1.b, z2.b
+ udot z0.h, z1.h, z2.h
+ udot z0.s, z1.s, z2.s
+ udot z0.d, z1.d, z2.d
+
+ udot z0.b, z1.b, z2.b[0]
+ udot z0.h, z1.h, z2.h[0]
+ udot z0.s, z1.s, z2.s[0]
+ udot z0.d, z1.d, z2.d[0]
diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index 4b976ef..5c7c519 100644
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -1,4 +1,4 @@
-#as: -march=armv8-a+sve
+#as: -march=armv8-a+sve -I$srcdir/$subdir
#objdump: -dr
.* file format .*
@@ -6,6 +6,24 @@
Disassembly of section .*:
0+ <.*>:
+.*: 2579c000 fmov z0\.h, #2\.0+e\+00
+.*: 2579c000 fmov z0\.h, #2\.0+e\+00
+.*: 2579c001 fmov z1\.h, #2\.0+e\+00
+.*: 2579c001 fmov z1\.h, #2\.0+e\+00
+.*: 2579c01f fmov z31\.h, #2\.0+e\+00
+.*: 2579c01f fmov z31\.h, #2\.0+e\+00
+.*: 2579c600 fmov z0\.h, #1\.60+e\+01
+.*: 2579c600 fmov z0\.h, #1\.60+e\+01
+.*: 2579c900 fmov z0\.h, #1\.8750+e-01
+.*: 2579c900 fmov z0\.h, #1\.8750+e-01
+.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
+.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
+.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
+.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
+.*: 2579d800 fmov z0\.h, #-1\.250+e-01
+.*: 2579d800 fmov z0\.h, #-1\.250+e-01
+.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
+.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
@@ -42,6 +60,28 @@ Disassembly of section .*:
.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
+.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
+.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
+.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
+.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
+.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
+.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
+.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
+.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
+.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
+.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
+.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
+.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
+.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
+.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
+.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
+.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
+.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
+.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
+.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
+.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
+.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
+.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
@@ -136,6 +176,16 @@ Disassembly of section .*:
.*: 05282040 mov z0\.d, d2
.*: 052823e0 mov z0\.d, d31
.*: 052823e0 mov z0\.d, d31
+.*: 05302000 mov z0\.q, q0
+.*: 05302000 mov z0\.q, q0
+.*: 05302001 mov z1\.q, q0
+.*: 05302001 mov z1\.q, q0
+.*: 0530201f mov z31\.q, q0
+.*: 0530201f mov z31\.q, q0
+.*: 05302040 mov z0\.q, q2
+.*: 05302040 mov z0\.q, q2
+.*: 053023e0 mov z0\.q, q31
+.*: 053023e0 mov z0\.q, q31
.*: 05203800 mov z0\.b, w0
.*: 05203800 mov z0\.b, w0
.*: 05203801 mov z1\.b, w0
@@ -314,6 +364,22 @@ Disassembly of section .*:
.*: 052f23e0 mov z0\.b, z31\.b\[7\]
.*: 05312000 mov z0\.b, z0\.b\[8\]
.*: 05312000 mov z0\.b, z0\.b\[8\]
+.*: 05702000 mov z0\.q, z0\.q\[1\]
+.*: 05702000 mov z0\.q, z0\.q\[1\]
+.*: 05702001 mov z1\.q, z0\.q\[1\]
+.*: 05702001 mov z1\.q, z0\.q\[1\]
+.*: 0570201f mov z31\.q, z0\.q\[1\]
+.*: 0570201f mov z31\.q, z0\.q\[1\]
+.*: 05702040 mov z0\.q, z2\.q\[1\]
+.*: 05702040 mov z0\.q, z2\.q\[1\]
+.*: 057023e0 mov z0\.q, z31\.q\[1\]
+.*: 057023e0 mov z0\.q, z31\.q\[1\]
+.*: 05302000 mov z0\.q, q0
+.*: 05302000 mov z0\.q, q0
+.*: 05b02000 mov z0\.q, z0\.q\[2\]
+.*: 05b02000 mov z0\.q, z0\.q\[2\]
+.*: 05f02000 mov z0\.q, z0\.q\[3\]
+.*: 05f02000 mov z0\.q, z0\.q\[3\]
.*: 05c000e0 mov z0\.s, #0xff
.*: 05c000e0 mov z0\.s, #0xff
.*: 05c000e0 mov z0\.s, #0xff
@@ -7645,6 +7711,22 @@ Disassembly of section .*:
.*: 052f23e0 mov z0\.b, z31\.b\[7\]
.*: 05312000 mov z0\.b, z0\.b\[8\]
.*: 05312000 mov z0\.b, z0\.b\[8\]
+.*: 05702000 mov z0\.q, z0\.q\[1\]
+.*: 05702000 mov z0\.q, z0\.q\[1\]
+.*: 05702001 mov z1\.q, z0\.q\[1\]
+.*: 05702001 mov z1\.q, z0\.q\[1\]
+.*: 0570201f mov z31\.q, z0\.q\[1\]
+.*: 0570201f mov z31\.q, z0\.q\[1\]
+.*: 05702040 mov z0\.q, z2\.q\[1\]
+.*: 05702040 mov z0\.q, z2\.q\[1\]
+.*: 057023e0 mov z0\.q, z31\.q\[1\]
+.*: 057023e0 mov z0\.q, z31\.q\[1\]
+.*: 05302000 mov z0\.q, q0
+.*: 05302000 mov z0\.q, q0
+.*: 05b02000 mov z0\.q, z0\.q\[2\]
+.*: 05b02000 mov z0\.q, z0\.q\[2\]
+.*: 05f02000 mov z0\.q, z0\.q\[3\]
+.*: 05f02000 mov z0\.q, z0\.q\[3\]
.*: 2538c000 mov z0\.b, #0
.*: 2538c000 mov z0\.b, #0
.*: 2538c000 mov z0\.b, #0
@@ -8092,6 +8174,22 @@ Disassembly of section .*:
.*: 05300400 ext z0\.b, z0\.b, z0\.b, #129
.*: 053f1c00 ext z0\.b, z0\.b, z0\.b, #255
.*: 053f1c00 ext z0\.b, z0\.b, z0\.b, #255
+.*: 65488000 fabd z0\.h, p0/m, z0\.h, z0\.h
+.*: 65488000 fabd z0\.h, p0/m, z0\.h, z0\.h
+.*: 65488001 fabd z1\.h, p0/m, z1\.h, z0\.h
+.*: 65488001 fabd z1\.h, p0/m, z1\.h, z0\.h
+.*: 6548801f fabd z31\.h, p0/m, z31\.h, z0\.h
+.*: 6548801f fabd z31\.h, p0/m, z31\.h, z0\.h
+.*: 65488800 fabd z0\.h, p2/m, z0\.h, z0\.h
+.*: 65488800 fabd z0\.h, p2/m, z0\.h, z0\.h
+.*: 65489c00 fabd z0\.h, p7/m, z0\.h, z0\.h
+.*: 65489c00 fabd z0\.h, p7/m, z0\.h, z0\.h
+.*: 65488003 fabd z3\.h, p0/m, z3\.h, z0\.h
+.*: 65488003 fabd z3\.h, p0/m, z3\.h, z0\.h
+.*: 65488080 fabd z0\.h, p0/m, z0\.h, z4\.h
+.*: 65488080 fabd z0\.h, p0/m, z0\.h, z4\.h
+.*: 654883e0 fabd z0\.h, p0/m, z0\.h, z31\.h
+.*: 654883e0 fabd z0\.h, p0/m, z0\.h, z31\.h
.*: 65888000 fabd z0\.s, p0/m, z0\.s, z0\.s
.*: 65888000 fabd z0\.s, p0/m, z0\.s, z0\.s
.*: 65888001 fabd z1\.s, p0/m, z1\.s, z0\.s
@@ -8124,6 +8222,20 @@ Disassembly of section .*:
.*: 65c88080 fabd z0\.d, p0/m, z0\.d, z4\.d
.*: 65c883e0 fabd z0\.d, p0/m, z0\.d, z31\.d
.*: 65c883e0 fabd z0\.d, p0/m, z0\.d, z31\.d
+.*: 045ca000 fabs z0\.h, p0/m, z0\.h
+.*: 045ca000 fabs z0\.h, p0/m, z0\.h
+.*: 045ca001 fabs z1\.h, p0/m, z0\.h
+.*: 045ca001 fabs z1\.h, p0/m, z0\.h
+.*: 045ca01f fabs z31\.h, p0/m, z0\.h
+.*: 045ca01f fabs z31\.h, p0/m, z0\.h
+.*: 045ca800 fabs z0\.h, p2/m, z0\.h
+.*: 045ca800 fabs z0\.h, p2/m, z0\.h
+.*: 045cbc00 fabs z0\.h, p7/m, z0\.h
+.*: 045cbc00 fabs z0\.h, p7/m, z0\.h
+.*: 045ca060 fabs z0\.h, p0/m, z3\.h
+.*: 045ca060 fabs z0\.h, p0/m, z3\.h
+.*: 045ca3e0 fabs z0\.h, p0/m, z31\.h
+.*: 045ca3e0 fabs z0\.h, p0/m, z31\.h
.*: 049ca000 fabs z0\.s, p0/m, z0\.s
.*: 049ca000 fabs z0\.s, p0/m, z0\.s
.*: 049ca001 fabs z1\.s, p0/m, z0\.s
@@ -8152,6 +8264,24 @@ Disassembly of section .*:
.*: 04dca060 fabs z0\.d, p0/m, z3\.d
.*: 04dca3e0 fabs z0\.d, p0/m, z31\.d
.*: 04dca3e0 fabs z0\.d, p0/m, z31\.d
+.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540c070 facge p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540c070 facge p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
+.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
+.*: 6544c010 facge p0\.h, p0/z, z0\.h, z4\.h
+.*: 6544c010 facge p0\.h, p0/z, z0\.h, z4\.h
+.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
+.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
@@ -8188,6 +8318,24 @@ Disassembly of section .*:
.*: 65c4c010 facge p0\.d, p0/z, z0\.d, z4\.d
.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
+.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540e070 facgt p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540e070 facgt p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 6544e010 facgt p0\.h, p0/z, z0\.h, z4\.h
+.*: 6544e010 facgt p0\.h, p0/z, z0\.h, z4\.h
+.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
.*: 6580e011 facgt p1\.s, p0/z, z0\.s, z0\.s
@@ -8224,6 +8372,20 @@ Disassembly of section .*:
.*: 65c4e010 facgt p0\.d, p0/z, z0\.d, z4\.d
.*: 65dfe010 facgt p0\.d, p0/z, z0\.d, z31\.d
.*: 65dfe010 facgt p0\.d, p0/z, z0\.d, z31\.d
+.*: 65400000 fadd z0\.h, z0\.h, z0\.h
+.*: 65400000 fadd z0\.h, z0\.h, z0\.h
+.*: 65400001 fadd z1\.h, z0\.h, z0\.h
+.*: 65400001 fadd z1\.h, z0\.h, z0\.h
+.*: 6540001f fadd z31\.h, z0\.h, z0\.h
+.*: 6540001f fadd z31\.h, z0\.h, z0\.h
+.*: 65400040 fadd z0\.h, z2\.h, z0\.h
+.*: 65400040 fadd z0\.h, z2\.h, z0\.h
+.*: 654003e0 fadd z0\.h, z31\.h, z0\.h
+.*: 654003e0 fadd z0\.h, z31\.h, z0\.h
+.*: 65430000 fadd z0\.h, z0\.h, z3\.h
+.*: 65430000 fadd z0\.h, z0\.h, z3\.h
+.*: 655f0000 fadd z0\.h, z0\.h, z31\.h
+.*: 655f0000 fadd z0\.h, z0\.h, z31\.h
.*: 65800000 fadd z0\.s, z0\.s, z0\.s
.*: 65800000 fadd z0\.s, z0\.s, z0\.s
.*: 65800001 fadd z1\.s, z0\.s, z0\.s
@@ -8252,6 +8414,22 @@ Disassembly of section .*:
.*: 65c30000 fadd z0\.d, z0\.d, z3\.d
.*: 65df0000 fadd z0\.d, z0\.d, z31\.d
.*: 65df0000 fadd z0\.d, z0\.d, z31\.d
+.*: 65408000 fadd z0\.h, p0/m, z0\.h, z0\.h
+.*: 65408000 fadd z0\.h, p0/m, z0\.h, z0\.h
+.*: 65408001 fadd z1\.h, p0/m, z1\.h, z0\.h
+.*: 65408001 fadd z1\.h, p0/m, z1\.h, z0\.h
+.*: 6540801f fadd z31\.h, p0/m, z31\.h, z0\.h
+.*: 6540801f fadd z31\.h, p0/m, z31\.h, z0\.h
+.*: 65408800 fadd z0\.h, p2/m, z0\.h, z0\.h
+.*: 65408800 fadd z0\.h, p2/m, z0\.h, z0\.h
+.*: 65409c00 fadd z0\.h, p7/m, z0\.h, z0\.h
+.*: 65409c00 fadd z0\.h, p7/m, z0\.h, z0\.h
+.*: 65408003 fadd z3\.h, p0/m, z3\.h, z0\.h
+.*: 65408003 fadd z3\.h, p0/m, z3\.h, z0\.h
+.*: 65408080 fadd z0\.h, p0/m, z0\.h, z4\.h
+.*: 65408080 fadd z0\.h, p0/m, z0\.h, z4\.h
+.*: 654083e0 fadd z0\.h, p0/m, z0\.h, z31\.h
+.*: 654083e0 fadd z0\.h, p0/m, z0\.h, z31\.h
.*: 65808000 fadd z0\.s, p0/m, z0\.s, z0\.s
.*: 65808000 fadd z0\.s, p0/m, z0\.s, z0\.s
.*: 65808001 fadd z1\.s, p0/m, z1\.s, z0\.s
@@ -8284,6 +8462,34 @@ Disassembly of section .*:
.*: 65c08080 fadd z0\.d, p0/m, z0\.d, z4\.d
.*: 65c083e0 fadd z0\.d, p0/m, z0\.d, z31\.d
.*: 65c083e0 fadd z0\.d, p0/m, z0\.d, z31\.d
+.*: 65588000 fadd z0\.h, p0/m, z0\.h, #0\.5
+.*: 65588000 fadd z0\.h, p0/m, z0\.h, #0\.5
+.*: 65588000 fadd z0\.h, p0/m, z0\.h, #0\.5
+.*: 65588000 fadd z0\.h, p0/m, z0\.h, #0\.5
+.*: 65588001 fadd z1\.h, p0/m, z1\.h, #0\.5
+.*: 65588001 fadd z1\.h, p0/m, z1\.h, #0\.5
+.*: 65588001 fadd z1\.h, p0/m, z1\.h, #0\.5
+.*: 65588001 fadd z1\.h, p0/m, z1\.h, #0\.5
+.*: 6558801f fadd z31\.h, p0/m, z31\.h, #0\.5
+.*: 6558801f fadd z31\.h, p0/m, z31\.h, #0\.5
+.*: 6558801f fadd z31\.h, p0/m, z31\.h, #0\.5
+.*: 6558801f fadd z31\.h, p0/m, z31\.h, #0\.5
+.*: 65588800 fadd z0\.h, p2/m, z0\.h, #0\.5
+.*: 65588800 fadd z0\.h, p2/m, z0\.h, #0\.5
+.*: 65588800 fadd z0\.h, p2/m, z0\.h, #0\.5
+.*: 65588800 fadd z0\.h, p2/m, z0\.h, #0\.5
+.*: 65589c00 fadd z0\.h, p7/m, z0\.h, #0\.5
+.*: 65589c00 fadd z0\.h, p7/m, z0\.h, #0\.5
+.*: 65589c00 fadd z0\.h, p7/m, z0\.h, #0\.5
+.*: 65589c00 fadd z0\.h, p7/m, z0\.h, #0\.5
+.*: 65588003 fadd z3\.h, p0/m, z3\.h, #0\.5
+.*: 65588003 fadd z3\.h, p0/m, z3\.h, #0\.5
+.*: 65588003 fadd z3\.h, p0/m, z3\.h, #0\.5
+.*: 65588003 fadd z3\.h, p0/m, z3\.h, #0\.5
+.*: 65588020 fadd z0\.h, p0/m, z0\.h, #1\.0
+.*: 65588020 fadd z0\.h, p0/m, z0\.h, #1\.0
+.*: 65588020 fadd z0\.h, p0/m, z0\.h, #1\.0
+.*: 65588020 fadd z0\.h, p0/m, z0\.h, #1\.0
.*: 65988000 fadd z0\.s, p0/m, z0\.s, #0\.5
.*: 65988000 fadd z0\.s, p0/m, z0\.s, #0\.5
.*: 65988000 fadd z0\.s, p0/m, z0\.s, #0\.5
@@ -8340,6 +8546,22 @@ Disassembly of section .*:
.*: 65d88020 fadd z0\.d, p0/m, z0\.d, #1\.0
.*: 65d88020 fadd z0\.d, p0/m, z0\.d, #1\.0
.*: 65d88020 fadd z0\.d, p0/m, z0\.d, #1\.0
+.*: 65582000 fadda h0, p0, h0, z0\.h
+.*: 65582000 fadda h0, p0, h0, z0\.h
+.*: 65582001 fadda h1, p0, h1, z0\.h
+.*: 65582001 fadda h1, p0, h1, z0\.h
+.*: 6558201f fadda h31, p0, h31, z0\.h
+.*: 6558201f fadda h31, p0, h31, z0\.h
+.*: 65582800 fadda h0, p2, h0, z0\.h
+.*: 65582800 fadda h0, p2, h0, z0\.h
+.*: 65583c00 fadda h0, p7, h0, z0\.h
+.*: 65583c00 fadda h0, p7, h0, z0\.h
+.*: 65582003 fadda h3, p0, h3, z0\.h
+.*: 65582003 fadda h3, p0, h3, z0\.h
+.*: 65582080 fadda h0, p0, h0, z4\.h
+.*: 65582080 fadda h0, p0, h0, z4\.h
+.*: 655823e0 fadda h0, p0, h0, z31\.h
+.*: 655823e0 fadda h0, p0, h0, z31\.h
.*: 65982000 fadda s0, p0, s0, z0\.s
.*: 65982000 fadda s0, p0, s0, z0\.s
.*: 65982001 fadda s1, p0, s1, z0\.s
@@ -8372,6 +8594,20 @@ Disassembly of section .*:
.*: 65d82080 fadda d0, p0, d0, z4\.d
.*: 65d823e0 fadda d0, p0, d0, z31\.d
.*: 65d823e0 fadda d0, p0, d0, z31\.d
+.*: 65402000 faddv h0, p0, z0\.h
+.*: 65402000 faddv h0, p0, z0\.h
+.*: 65402001 faddv h1, p0, z0\.h
+.*: 65402001 faddv h1, p0, z0\.h
+.*: 6540201f faddv h31, p0, z0\.h
+.*: 6540201f faddv h31, p0, z0\.h
+.*: 65402800 faddv h0, p2, z0\.h
+.*: 65402800 faddv h0, p2, z0\.h
+.*: 65403c00 faddv h0, p7, z0\.h
+.*: 65403c00 faddv h0, p7, z0\.h
+.*: 65402060 faddv h0, p0, z3\.h
+.*: 65402060 faddv h0, p0, z3\.h
+.*: 654023e0 faddv h0, p0, z31\.h
+.*: 654023e0 faddv h0, p0, z31\.h
.*: 65802000 faddv s0, p0, z0\.s
.*: 65802000 faddv s0, p0, z0\.s
.*: 65802001 faddv s1, p0, z0\.s
@@ -8400,6 +8636,202 @@ Disassembly of section .*:
.*: 65c02060 faddv d0, p0, z3\.d
.*: 65c023e0 faddv d0, p0, z31\.d
.*: 65c023e0 faddv d0, p0, z31\.d
+.*: 64408000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: 64408000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: 64408001 fcadd z1\.h, p0/m, z1\.h, z0\.h, #90
+.*: 64408001 fcadd z1\.h, p0/m, z1\.h, z0\.h, #90
+.*: 6440801f fcadd z31\.h, p0/m, z31\.h, z0\.h, #90
+.*: 6440801f fcadd z31\.h, p0/m, z31\.h, z0\.h, #90
+.*: 64408800 fcadd z0\.h, p2/m, z0\.h, z0\.h, #90
+.*: 64408800 fcadd z0\.h, p2/m, z0\.h, z0\.h, #90
+.*: 64409c00 fcadd z0\.h, p7/m, z0\.h, z0\.h, #90
+.*: 64409c00 fcadd z0\.h, p7/m, z0\.h, z0\.h, #90
+.*: 64408003 fcadd z3\.h, p0/m, z3\.h, z0\.h, #90
+.*: 64408003 fcadd z3\.h, p0/m, z3\.h, z0\.h, #90
+.*: 64408080 fcadd z0\.h, p0/m, z0\.h, z4\.h, #90
+.*: 64408080 fcadd z0\.h, p0/m, z0\.h, z4\.h, #90
+.*: 644083e0 fcadd z0\.h, p0/m, z0\.h, z31\.h, #90
+.*: 644083e0 fcadd z0\.h, p0/m, z0\.h, z31\.h, #90
+.*: 64418000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #270
+.*: 64418000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #270
+.*: 64808000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: 64808000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: 64808001 fcadd z1\.s, p0/m, z1\.s, z0\.s, #90
+.*: 64808001 fcadd z1\.s, p0/m, z1\.s, z0\.s, #90
+.*: 6480801f fcadd z31\.s, p0/m, z31\.s, z0\.s, #90
+.*: 6480801f fcadd z31\.s, p0/m, z31\.s, z0\.s, #90
+.*: 64808800 fcadd z0\.s, p2/m, z0\.s, z0\.s, #90
+.*: 64808800 fcadd z0\.s, p2/m, z0\.s, z0\.s, #90
+.*: 64809c00 fcadd z0\.s, p7/m, z0\.s, z0\.s, #90
+.*: 64809c00 fcadd z0\.s, p7/m, z0\.s, z0\.s, #90
+.*: 64808003 fcadd z3\.s, p0/m, z3\.s, z0\.s, #90
+.*: 64808003 fcadd z3\.s, p0/m, z3\.s, z0\.s, #90
+.*: 64808080 fcadd z0\.s, p0/m, z0\.s, z4\.s, #90
+.*: 64808080 fcadd z0\.s, p0/m, z0\.s, z4\.s, #90
+.*: 648083e0 fcadd z0\.s, p0/m, z0\.s, z31\.s, #90
+.*: 648083e0 fcadd z0\.s, p0/m, z0\.s, z31\.s, #90
+.*: 64818000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #270
+.*: 64818000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #270
+.*: 64c08000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: 64c08000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: 64c08001 fcadd z1\.d, p0/m, z1\.d, z0\.d, #90
+.*: 64c08001 fcadd z1\.d, p0/m, z1\.d, z0\.d, #90
+.*: 64c0801f fcadd z31\.d, p0/m, z31\.d, z0\.d, #90
+.*: 64c0801f fcadd z31\.d, p0/m, z31\.d, z0\.d, #90
+.*: 64c08800 fcadd z0\.d, p2/m, z0\.d, z0\.d, #90
+.*: 64c08800 fcadd z0\.d, p2/m, z0\.d, z0\.d, #90
+.*: 64c09c00 fcadd z0\.d, p7/m, z0\.d, z0\.d, #90
+.*: 64c09c00 fcadd z0\.d, p7/m, z0\.d, z0\.d, #90
+.*: 64c08003 fcadd z3\.d, p0/m, z3\.d, z0\.d, #90
+.*: 64c08003 fcadd z3\.d, p0/m, z3\.d, z0\.d, #90
+.*: 64c08080 fcadd z0\.d, p0/m, z0\.d, z4\.d, #90
+.*: 64c08080 fcadd z0\.d, p0/m, z0\.d, z4\.d, #90
+.*: 64c083e0 fcadd z0\.d, p0/m, z0\.d, z31\.d, #90
+.*: 64c083e0 fcadd z0\.d, p0/m, z0\.d, z31\.d, #90
+.*: 64c18000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #270
+.*: 64c18000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #270
+.*: 64400000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #0
+.*: 64400000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #0
+.*: 64400001 fcmla z1\.h, p0/m, z0\.h, z0\.h, #0
+.*: 64400001 fcmla z1\.h, p0/m, z0\.h, z0\.h, #0
+.*: 6440001f fcmla z31\.h, p0/m, z0\.h, z0\.h, #0
+.*: 6440001f fcmla z31\.h, p0/m, z0\.h, z0\.h, #0
+.*: 64400800 fcmla z0\.h, p2/m, z0\.h, z0\.h, #0
+.*: 64400800 fcmla z0\.h, p2/m, z0\.h, z0\.h, #0
+.*: 64401c00 fcmla z0\.h, p7/m, z0\.h, z0\.h, #0
+.*: 64401c00 fcmla z0\.h, p7/m, z0\.h, z0\.h, #0
+.*: 64400060 fcmla z0\.h, p0/m, z3\.h, z0\.h, #0
+.*: 64400060 fcmla z0\.h, p0/m, z3\.h, z0\.h, #0
+.*: 644003e0 fcmla z0\.h, p0/m, z31\.h, z0\.h, #0
+.*: 644003e0 fcmla z0\.h, p0/m, z31\.h, z0\.h, #0
+.*: 64440000 fcmla z0\.h, p0/m, z0\.h, z4\.h, #0
+.*: 64440000 fcmla z0\.h, p0/m, z0\.h, z4\.h, #0
+.*: 645f0000 fcmla z0\.h, p0/m, z0\.h, z31\.h, #0
+.*: 645f0000 fcmla z0\.h, p0/m, z0\.h, z31\.h, #0
+.*: 64402000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: 64402000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
+.*: 64404000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #180
+.*: 64404000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #180
+.*: 64406000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #270
+.*: 64406000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #270
+.*: 64800000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #0
+.*: 64800000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #0
+.*: 64800001 fcmla z1\.s, p0/m, z0\.s, z0\.s, #0
+.*: 64800001 fcmla z1\.s, p0/m, z0\.s, z0\.s, #0
+.*: 6480001f fcmla z31\.s, p0/m, z0\.s, z0\.s, #0
+.*: 6480001f fcmla z31\.s, p0/m, z0\.s, z0\.s, #0
+.*: 64800800 fcmla z0\.s, p2/m, z0\.s, z0\.s, #0
+.*: 64800800 fcmla z0\.s, p2/m, z0\.s, z0\.s, #0
+.*: 64801c00 fcmla z0\.s, p7/m, z0\.s, z0\.s, #0
+.*: 64801c00 fcmla z0\.s, p7/m, z0\.s, z0\.s, #0
+.*: 64800060 fcmla z0\.s, p0/m, z3\.s, z0\.s, #0
+.*: 64800060 fcmla z0\.s, p0/m, z3\.s, z0\.s, #0
+.*: 648003e0 fcmla z0\.s, p0/m, z31\.s, z0\.s, #0
+.*: 648003e0 fcmla z0\.s, p0/m, z31\.s, z0\.s, #0
+.*: 64840000 fcmla z0\.s, p0/m, z0\.s, z4\.s, #0
+.*: 64840000 fcmla z0\.s, p0/m, z0\.s, z4\.s, #0
+.*: 649f0000 fcmla z0\.s, p0/m, z0\.s, z31\.s, #0
+.*: 649f0000 fcmla z0\.s, p0/m, z0\.s, z31\.s, #0
+.*: 64802000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: 64802000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
+.*: 64804000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #180
+.*: 64804000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #180
+.*: 64806000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #270
+.*: 64806000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #270
+.*: 64c00000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c00000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c00001 fcmla z1\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c00001 fcmla z1\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c0001f fcmla z31\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c0001f fcmla z31\.d, p0/m, z0\.d, z0\.d, #0
+.*: 64c00800 fcmla z0\.d, p2/m, z0\.d, z0\.d, #0
+.*: 64c00800 fcmla z0\.d, p2/m, z0\.d, z0\.d, #0
+.*: 64c01c00 fcmla z0\.d, p7/m, z0\.d, z0\.d, #0
+.*: 64c01c00 fcmla z0\.d, p7/m, z0\.d, z0\.d, #0
+.*: 64c00060 fcmla z0\.d, p0/m, z3\.d, z0\.d, #0
+.*: 64c00060 fcmla z0\.d, p0/m, z3\.d, z0\.d, #0
+.*: 64c003e0 fcmla z0\.d, p0/m, z31\.d, z0\.d, #0
+.*: 64c003e0 fcmla z0\.d, p0/m, z31\.d, z0\.d, #0
+.*: 64c40000 fcmla z0\.d, p0/m, z0\.d, z4\.d, #0
+.*: 64c40000 fcmla z0\.d, p0/m, z0\.d, z4\.d, #0
+.*: 64df0000 fcmla z0\.d, p0/m, z0\.d, z31\.d, #0
+.*: 64df0000 fcmla z0\.d, p0/m, z0\.d, z31\.d, #0
+.*: 64c02000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: 64c02000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
+.*: 64c04000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #180
+.*: 64c04000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #180
+.*: 64c06000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #270
+.*: 64c06000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #270
+.*: 64a01000 fcmla z0\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a01000 fcmla z0\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a01001 fcmla z1\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a01001 fcmla z1\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a0101f fcmla z31\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a0101f fcmla z31\.h, z0\.h, z0\.h\[0\], #0
+.*: 64a01040 fcmla z0\.h, z2\.h, z0\.h\[0\], #0
+.*: 64a01040 fcmla z0\.h, z2\.h, z0\.h\[0\], #0
+.*: 64a013e0 fcmla z0\.h, z31\.h, z0\.h\[0\], #0
+.*: 64a013e0 fcmla z0\.h, z31\.h, z0\.h\[0\], #0
+.*: 64a31000 fcmla z0\.h, z0\.h, z3\.h\[0\], #0
+.*: 64a31000 fcmla z0\.h, z0\.h, z3\.h\[0\], #0
+.*: 64a71000 fcmla z0\.h, z0\.h, z7\.h\[0\], #0
+.*: 64a71000 fcmla z0\.h, z0\.h, z7\.h\[0\], #0
+.*: 64a81000 fcmla z0\.h, z0\.h, z0\.h\[1\], #0
+.*: 64a81000 fcmla z0\.h, z0\.h, z0\.h\[1\], #0
+.*: 64ad1000 fcmla z0\.h, z0\.h, z5\.h\[1\], #0
+.*: 64ad1000 fcmla z0\.h, z0\.h, z5\.h\[1\], #0
+.*: 64b01000 fcmla z0\.h, z0\.h, z0\.h\[2\], #0
+.*: 64b01000 fcmla z0\.h, z0\.h, z0\.h\[2\], #0
+.*: 64b31000 fcmla z0\.h, z0\.h, z3\.h\[2\], #0
+.*: 64b31000 fcmla z0\.h, z0\.h, z3\.h\[2\], #0
+.*: 64b81000 fcmla z0\.h, z0\.h, z0\.h\[3\], #0
+.*: 64b81000 fcmla z0\.h, z0\.h, z0\.h\[3\], #0
+.*: 64be1000 fcmla z0\.h, z0\.h, z6\.h\[3\], #0
+.*: 64be1000 fcmla z0\.h, z0\.h, z6\.h\[3\], #0
+.*: 64a01400 fcmla z0\.h, z0\.h, z0\.h\[0\], #90
+.*: 64a01400 fcmla z0\.h, z0\.h, z0\.h\[0\], #90
+.*: 64a01800 fcmla z0\.h, z0\.h, z0\.h\[0\], #180
+.*: 64a01800 fcmla z0\.h, z0\.h, z0\.h\[0\], #180
+.*: 64a01c00 fcmla z0\.h, z0\.h, z0\.h\[0\], #270
+.*: 64a01c00 fcmla z0\.h, z0\.h, z0\.h\[0\], #270
+.*: 64e01000 fcmla z0\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e01000 fcmla z0\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e01001 fcmla z1\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e01001 fcmla z1\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e0101f fcmla z31\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e0101f fcmla z31\.s, z0\.s, z0\.s\[0\], #0
+.*: 64e01040 fcmla z0\.s, z2\.s, z0\.s\[0\], #0
+.*: 64e01040 fcmla z0\.s, z2\.s, z0\.s\[0\], #0
+.*: 64e013e0 fcmla z0\.s, z31\.s, z0\.s\[0\], #0
+.*: 64e013e0 fcmla z0\.s, z31\.s, z0\.s\[0\], #0
+.*: 64e31000 fcmla z0\.s, z0\.s, z3\.s\[0\], #0
+.*: 64e31000 fcmla z0\.s, z0\.s, z3\.s\[0\], #0
+.*: 64ef1000 fcmla z0\.s, z0\.s, z15\.s\[0\], #0
+.*: 64ef1000 fcmla z0\.s, z0\.s, z15\.s\[0\], #0
+.*: 64f01000 fcmla z0\.s, z0\.s, z0\.s\[1\], #0
+.*: 64f01000 fcmla z0\.s, z0\.s, z0\.s\[1\], #0
+.*: 64fb1000 fcmla z0\.s, z0\.s, z11\.s\[1\], #0
+.*: 64fb1000 fcmla z0\.s, z0\.s, z11\.s\[1\], #0
+.*: 64e01400 fcmla z0\.s, z0\.s, z0\.s\[0\], #90
+.*: 64e01400 fcmla z0\.s, z0\.s, z0\.s\[0\], #90
+.*: 64e01800 fcmla z0\.s, z0\.s, z0\.s\[0\], #180
+.*: 64e01800 fcmla z0\.s, z0\.s, z0\.s\[0\], #180
+.*: 64e01c00 fcmla z0\.s, z0\.s, z0\.s\[0\], #270
+.*: 64e01c00 fcmla z0\.s, z0\.s, z0\.s\[0\], #270
+.*: 65522000 fcmeq p0\.h, p0/z, z0\.h, #0\.0
+.*: 65522000 fcmeq p0\.h, p0/z, z0\.h, #0\.0
+.*: 65522001 fcmeq p1\.h, p0/z, z0\.h, #0\.0
+.*: 65522001 fcmeq p1\.h, p0/z, z0\.h, #0\.0
+.*: 6552200f fcmeq p15\.h, p0/z, z0\.h, #0\.0
+.*: 6552200f fcmeq p15\.h, p0/z, z0\.h, #0\.0
+.*: 65522800 fcmeq p0\.h, p2/z, z0\.h, #0\.0
+.*: 65522800 fcmeq p0\.h, p2/z, z0\.h, #0\.0
+.*: 65523c00 fcmeq p0\.h, p7/z, z0\.h, #0\.0
+.*: 65523c00 fcmeq p0\.h, p7/z, z0\.h, #0\.0
+.*: 65522060 fcmeq p0\.h, p0/z, z3\.h, #0\.0
+.*: 65522060 fcmeq p0\.h, p0/z, z3\.h, #0\.0
+.*: 655223e0 fcmeq p0\.h, p0/z, z31\.h, #0\.0
+.*: 655223e0 fcmeq p0\.h, p0/z, z31\.h, #0\.0
.*: 65922000 fcmeq p0\.s, p0/z, z0\.s, #0\.0
.*: 65922000 fcmeq p0\.s, p0/z, z0\.s, #0\.0
.*: 65922001 fcmeq p1\.s, p0/z, z0\.s, #0\.0
@@ -8428,6 +8860,24 @@ Disassembly of section .*:
.*: 65d22060 fcmeq p0\.d, p0/z, z3\.d, #0\.0
.*: 65d223e0 fcmeq p0\.d, p0/z, z31\.d, #0\.0
.*: 65d223e0 fcmeq p0\.d, p0/z, z31\.d, #0\.0
+.*: 65406000 fcmeq p0\.h, p0/z, z0\.h, z0\.h
+.*: 65406000 fcmeq p0\.h, p0/z, z0\.h, z0\.h
+.*: 65406001 fcmeq p1\.h, p0/z, z0\.h, z0\.h
+.*: 65406001 fcmeq p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540600f fcmeq p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540600f fcmeq p15\.h, p0/z, z0\.h, z0\.h
+.*: 65406800 fcmeq p0\.h, p2/z, z0\.h, z0\.h
+.*: 65406800 fcmeq p0\.h, p2/z, z0\.h, z0\.h
+.*: 65407c00 fcmeq p0\.h, p7/z, z0\.h, z0\.h
+.*: 65407c00 fcmeq p0\.h, p7/z, z0\.h, z0\.h
+.*: 65406060 fcmeq p0\.h, p0/z, z3\.h, z0\.h
+.*: 65406060 fcmeq p0\.h, p0/z, z3\.h, z0\.h
+.*: 654063e0 fcmeq p0\.h, p0/z, z31\.h, z0\.h
+.*: 654063e0 fcmeq p0\.h, p0/z, z31\.h, z0\.h
+.*: 65446000 fcmeq p0\.h, p0/z, z0\.h, z4\.h
+.*: 65446000 fcmeq p0\.h, p0/z, z0\.h, z4\.h
+.*: 655f6000 fcmeq p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f6000 fcmeq p0\.h, p0/z, z0\.h, z31\.h
.*: 65806000 fcmeq p0\.s, p0/z, z0\.s, z0\.s
.*: 65806000 fcmeq p0\.s, p0/z, z0\.s, z0\.s
.*: 65806001 fcmeq p1\.s, p0/z, z0\.s, z0\.s
@@ -8464,6 +8914,20 @@ Disassembly of section .*:
.*: 65c46000 fcmeq p0\.d, p0/z, z0\.d, z4\.d
.*: 65df6000 fcmeq p0\.d, p0/z, z0\.d, z31\.d
.*: 65df6000 fcmeq p0\.d, p0/z, z0\.d, z31\.d
+.*: 65502000 fcmge p0\.h, p0/z, z0\.h, #0\.0
+.*: 65502000 fcmge p0\.h, p0/z, z0\.h, #0\.0
+.*: 65502001 fcmge p1\.h, p0/z, z0\.h, #0\.0
+.*: 65502001 fcmge p1\.h, p0/z, z0\.h, #0\.0
+.*: 6550200f fcmge p15\.h, p0/z, z0\.h, #0\.0
+.*: 6550200f fcmge p15\.h, p0/z, z0\.h, #0\.0
+.*: 65502800 fcmge p0\.h, p2/z, z0\.h, #0\.0
+.*: 65502800 fcmge p0\.h, p2/z, z0\.h, #0\.0
+.*: 65503c00 fcmge p0\.h, p7/z, z0\.h, #0\.0
+.*: 65503c00 fcmge p0\.h, p7/z, z0\.h, #0\.0
+.*: 65502060 fcmge p0\.h, p0/z, z3\.h, #0\.0
+.*: 65502060 fcmge p0\.h, p0/z, z3\.h, #0\.0
+.*: 655023e0 fcmge p0\.h, p0/z, z31\.h, #0\.0
+.*: 655023e0 fcmge p0\.h, p0/z, z31\.h, #0\.0
.*: 65902000 fcmge p0\.s, p0/z, z0\.s, #0\.0
.*: 65902000 fcmge p0\.s, p0/z, z0\.s, #0\.0
.*: 65902001 fcmge p1\.s, p0/z, z0\.s, #0\.0
@@ -8492,6 +8956,24 @@ Disassembly of section .*:
.*: 65d02060 fcmge p0\.d, p0/z, z3\.d, #0\.0
.*: 65d023e0 fcmge p0\.d, p0/z, z31\.d, #0\.0
.*: 65d023e0 fcmge p0\.d, p0/z, z31\.d, #0\.0
+.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
+.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
+.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
+.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
+.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
+.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
+.*: 65404060 fcmge p0\.h, p0/z, z3\.h, z0\.h
+.*: 65404060 fcmge p0\.h, p0/z, z3\.h, z0\.h
+.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
+.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
+.*: 65444000 fcmge p0\.h, p0/z, z0\.h, z4\.h
+.*: 65444000 fcmge p0\.h, p0/z, z0\.h, z4\.h
+.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
@@ -8528,6 +9010,20 @@ Disassembly of section .*:
.*: 65c44000 fcmge p0\.d, p0/z, z0\.d, z4\.d
.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
+.*: 65502010 fcmgt p0\.h, p0/z, z0\.h, #0\.0
+.*: 65502010 fcmgt p0\.h, p0/z, z0\.h, #0\.0
+.*: 65502011 fcmgt p1\.h, p0/z, z0\.h, #0\.0
+.*: 65502011 fcmgt p1\.h, p0/z, z0\.h, #0\.0
+.*: 6550201f fcmgt p15\.h, p0/z, z0\.h, #0\.0
+.*: 6550201f fcmgt p15\.h, p0/z, z0\.h, #0\.0
+.*: 65502810 fcmgt p0\.h, p2/z, z0\.h, #0\.0
+.*: 65502810 fcmgt p0\.h, p2/z, z0\.h, #0\.0
+.*: 65503c10 fcmgt p0\.h, p7/z, z0\.h, #0\.0
+.*: 65503c10 fcmgt p0\.h, p7/z, z0\.h, #0\.0
+.*: 65502070 fcmgt p0\.h, p0/z, z3\.h, #0\.0
+.*: 65502070 fcmgt p0\.h, p0/z, z3\.h, #0\.0
+.*: 655023f0 fcmgt p0\.h, p0/z, z31\.h, #0\.0
+.*: 655023f0 fcmgt p0\.h, p0/z, z31\.h, #0\.0
.*: 65902010 fcmgt p0\.s, p0/z, z0\.s, #0\.0
.*: 65902010 fcmgt p0\.s, p0/z, z0\.s, #0\.0
.*: 65902011 fcmgt p1\.s, p0/z, z0\.s, #0\.0
@@ -8556,6 +9052,24 @@ Disassembly of section .*:
.*: 65d02070 fcmgt p0\.d, p0/z, z3\.d, #0\.0
.*: 65d023f0 fcmgt p0\.d, p0/z, z31\.d, #0\.0
.*: 65d023f0 fcmgt p0\.d, p0/z, z31\.d, #0\.0
+.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 65404070 fcmgt p0\.h, p0/z, z3\.h, z0\.h
+.*: 65404070 fcmgt p0\.h, p0/z, z3\.h, z0\.h
+.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 65444010 fcmgt p0\.h, p0/z, z0\.h, z4\.h
+.*: 65444010 fcmgt p0\.h, p0/z, z0\.h, z4\.h
+.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
@@ -8592,6 +9106,20 @@ Disassembly of section .*:
.*: 65c44010 fcmgt p0\.d, p0/z, z0\.d, z4\.d
.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
+.*: 65512010 fcmle p0\.h, p0/z, z0\.h, #0\.0
+.*: 65512010 fcmle p0\.h, p0/z, z0\.h, #0\.0
+.*: 65512011 fcmle p1\.h, p0/z, z0\.h, #0\.0
+.*: 65512011 fcmle p1\.h, p0/z, z0\.h, #0\.0
+.*: 6551201f fcmle p15\.h, p0/z, z0\.h, #0\.0
+.*: 6551201f fcmle p15\.h, p0/z, z0\.h, #0\.0
+.*: 65512810 fcmle p0\.h, p2/z, z0\.h, #0\.0
+.*: 65512810 fcmle p0\.h, p2/z, z0\.h, #0\.0
+.*: 65513c10 fcmle p0\.h, p7/z, z0\.h, #0\.0
+.*: 65513c10 fcmle p0\.h, p7/z, z0\.h, #0\.0
+.*: 65512070 fcmle p0\.h, p0/z, z3\.h, #0\.0
+.*: 65512070 fcmle p0\.h, p0/z, z3\.h, #0\.0
+.*: 655123f0 fcmle p0\.h, p0/z, z31\.h, #0\.0
+.*: 655123f0 fcmle p0\.h, p0/z, z31\.h, #0\.0
.*: 65912010 fcmle p0\.s, p0/z, z0\.s, #0\.0
.*: 65912010 fcmle p0\.s, p0/z, z0\.s, #0\.0
.*: 65912011 fcmle p1\.s, p0/z, z0\.s, #0\.0
@@ -8620,6 +9148,20 @@ Disassembly of section .*:
.*: 65d12070 fcmle p0\.d, p0/z, z3\.d, #0\.0
.*: 65d123f0 fcmle p0\.d, p0/z, z31\.d, #0\.0
.*: 65d123f0 fcmle p0\.d, p0/z, z31\.d, #0\.0
+.*: 65512000 fcmlt p0\.h, p0/z, z0\.h, #0\.0
+.*: 65512000 fcmlt p0\.h, p0/z, z0\.h, #0\.0
+.*: 65512001 fcmlt p1\.h, p0/z, z0\.h, #0\.0
+.*: 65512001 fcmlt p1\.h, p0/z, z0\.h, #0\.0
+.*: 6551200f fcmlt p15\.h, p0/z, z0\.h, #0\.0
+.*: 6551200f fcmlt p15\.h, p0/z, z0\.h, #0\.0
+.*: 65512800 fcmlt p0\.h, p2/z, z0\.h, #0\.0
+.*: 65512800 fcmlt p0\.h, p2/z, z0\.h, #0\.0
+.*: 65513c00 fcmlt p0\.h, p7/z, z0\.h, #0\.0
+.*: 65513c00 fcmlt p0\.h, p7/z, z0\.h, #0\.0
+.*: 65512060 fcmlt p0\.h, p0/z, z3\.h, #0\.0
+.*: 65512060 fcmlt p0\.h, p0/z, z3\.h, #0\.0
+.*: 655123e0 fcmlt p0\.h, p0/z, z31\.h, #0\.0
+.*: 655123e0 fcmlt p0\.h, p0/z, z31\.h, #0\.0
.*: 65912000 fcmlt p0\.s, p0/z, z0\.s, #0\.0
.*: 65912000 fcmlt p0\.s, p0/z, z0\.s, #0\.0
.*: 65912001 fcmlt p1\.s, p0/z, z0\.s, #0\.0
@@ -8648,6 +9190,20 @@ Disassembly of section .*:
.*: 65d12060 fcmlt p0\.d, p0/z, z3\.d, #0\.0
.*: 65d123e0 fcmlt p0\.d, p0/z, z31\.d, #0\.0
.*: 65d123e0 fcmlt p0\.d, p0/z, z31\.d, #0\.0
+.*: 65532000 fcmne p0\.h, p0/z, z0\.h, #0\.0
+.*: 65532000 fcmne p0\.h, p0/z, z0\.h, #0\.0
+.*: 65532001 fcmne p1\.h, p0/z, z0\.h, #0\.0
+.*: 65532001 fcmne p1\.h, p0/z, z0\.h, #0\.0
+.*: 6553200f fcmne p15\.h, p0/z, z0\.h, #0\.0
+.*: 6553200f fcmne p15\.h, p0/z, z0\.h, #0\.0
+.*: 65532800 fcmne p0\.h, p2/z, z0\.h, #0\.0
+.*: 65532800 fcmne p0\.h, p2/z, z0\.h, #0\.0
+.*: 65533c00 fcmne p0\.h, p7/z, z0\.h, #0\.0
+.*: 65533c00 fcmne p0\.h, p7/z, z0\.h, #0\.0
+.*: 65532060 fcmne p0\.h, p0/z, z3\.h, #0\.0
+.*: 65532060 fcmne p0\.h, p0/z, z3\.h, #0\.0
+.*: 655323e0 fcmne p0\.h, p0/z, z31\.h, #0\.0
+.*: 655323e0 fcmne p0\.h, p0/z, z31\.h, #0\.0
.*: 65932000 fcmne p0\.s, p0/z, z0\.s, #0\.0
.*: 65932000 fcmne p0\.s, p0/z, z0\.s, #0\.0
.*: 65932001 fcmne p1\.s, p0/z, z0\.s, #0\.0
@@ -8676,6 +9232,24 @@ Disassembly of section .*:
.*: 65d32060 fcmne p0\.d, p0/z, z3\.d, #0\.0
.*: 65d323e0 fcmne p0\.d, p0/z, z31\.d, #0\.0
.*: 65d323e0 fcmne p0\.d, p0/z, z31\.d, #0\.0
+.*: 65406010 fcmne p0\.h, p0/z, z0\.h, z0\.h
+.*: 65406010 fcmne p0\.h, p0/z, z0\.h, z0\.h
+.*: 65406011 fcmne p1\.h, p0/z, z0\.h, z0\.h
+.*: 65406011 fcmne p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540601f fcmne p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540601f fcmne p15\.h, p0/z, z0\.h, z0\.h
+.*: 65406810 fcmne p0\.h, p2/z, z0\.h, z0\.h
+.*: 65406810 fcmne p0\.h, p2/z, z0\.h, z0\.h
+.*: 65407c10 fcmne p0\.h, p7/z, z0\.h, z0\.h
+.*: 65407c10 fcmne p0\.h, p7/z, z0\.h, z0\.h
+.*: 65406070 fcmne p0\.h, p0/z, z3\.h, z0\.h
+.*: 65406070 fcmne p0\.h, p0/z, z3\.h, z0\.h
+.*: 654063f0 fcmne p0\.h, p0/z, z31\.h, z0\.h
+.*: 654063f0 fcmne p0\.h, p0/z, z31\.h, z0\.h
+.*: 65446010 fcmne p0\.h, p0/z, z0\.h, z4\.h
+.*: 65446010 fcmne p0\.h, p0/z, z0\.h, z4\.h
+.*: 655f6010 fcmne p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f6010 fcmne p0\.h, p0/z, z0\.h, z31\.h
.*: 65806010 fcmne p0\.s, p0/z, z0\.s, z0\.s
.*: 65806010 fcmne p0\.s, p0/z, z0\.s, z0\.s
.*: 65806011 fcmne p1\.s, p0/z, z0\.s, z0\.s
@@ -8712,6 +9286,24 @@ Disassembly of section .*:
.*: 65c46010 fcmne p0\.d, p0/z, z0\.d, z4\.d
.*: 65df6010 fcmne p0\.d, p0/z, z0\.d, z31\.d
.*: 65df6010 fcmne p0\.d, p0/z, z0\.d, z31\.d
+.*: 6540c000 fcmuo p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c000 fcmuo p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c001 fcmuo p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c001 fcmuo p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c00f fcmuo p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c00f fcmuo p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c800 fcmuo p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540c800 fcmuo p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540dc00 fcmuo p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540dc00 fcmuo p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540c060 fcmuo p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540c060 fcmuo p0\.h, p0/z, z3\.h, z0\.h
+.*: 6540c3e0 fcmuo p0\.h, p0/z, z31\.h, z0\.h
+.*: 6540c3e0 fcmuo p0\.h, p0/z, z31\.h, z0\.h
+.*: 6544c000 fcmuo p0\.h, p0/z, z0\.h, z4\.h
+.*: 6544c000 fcmuo p0\.h, p0/z, z0\.h, z4\.h
+.*: 655fc000 fcmuo p0\.h, p0/z, z0\.h, z31\.h
+.*: 655fc000 fcmuo p0\.h, p0/z, z0\.h, z31\.h
.*: 6580c000 fcmuo p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c000 fcmuo p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c001 fcmuo p1\.s, p0/z, z0\.s, z0\.s
@@ -8748,6 +9340,28 @@ Disassembly of section .*:
.*: 65c4c000 fcmuo p0\.d, p0/z, z0\.d, z4\.d
.*: 65dfc000 fcmuo p0\.d, p0/z, z0\.d, z31\.d
.*: 65dfc000 fcmuo p0\.d, p0/z, z0\.d, z31\.d
+.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
+.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
+.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
+.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
+.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
+.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
+.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
+.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
+.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
+.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
+.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
+.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
+.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
+.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
+.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
+.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
+.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
+.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
+.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
+.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
+.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
+.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
@@ -8876,6 +9490,48 @@ Disassembly of section .*:
.*: 65cba060 fcvt z0\.d, p0/m, z3\.s
.*: 65cba3e0 fcvt z0\.d, p0/m, z31\.s
.*: 65cba3e0 fcvt z0\.d, p0/m, z31\.s
+.*: 655aa000 fcvtzs z0\.h, p0/m, z0\.h
+.*: 655aa000 fcvtzs z0\.h, p0/m, z0\.h
+.*: 655aa001 fcvtzs z1\.h, p0/m, z0\.h
+.*: 655aa001 fcvtzs z1\.h, p0/m, z0\.h
+.*: 655aa01f fcvtzs z31\.h, p0/m, z0\.h
+.*: 655aa01f fcvtzs z31\.h, p0/m, z0\.h
+.*: 655aa800 fcvtzs z0\.h, p2/m, z0\.h
+.*: 655aa800 fcvtzs z0\.h, p2/m, z0\.h
+.*: 655abc00 fcvtzs z0\.h, p7/m, z0\.h
+.*: 655abc00 fcvtzs z0\.h, p7/m, z0\.h
+.*: 655aa060 fcvtzs z0\.h, p0/m, z3\.h
+.*: 655aa060 fcvtzs z0\.h, p0/m, z3\.h
+.*: 655aa3e0 fcvtzs z0\.h, p0/m, z31\.h
+.*: 655aa3e0 fcvtzs z0\.h, p0/m, z31\.h
+.*: 655ca000 fcvtzs z0\.s, p0/m, z0\.h
+.*: 655ca000 fcvtzs z0\.s, p0/m, z0\.h
+.*: 655ca001 fcvtzs z1\.s, p0/m, z0\.h
+.*: 655ca001 fcvtzs z1\.s, p0/m, z0\.h
+.*: 655ca01f fcvtzs z31\.s, p0/m, z0\.h
+.*: 655ca01f fcvtzs z31\.s, p0/m, z0\.h
+.*: 655ca800 fcvtzs z0\.s, p2/m, z0\.h
+.*: 655ca800 fcvtzs z0\.s, p2/m, z0\.h
+.*: 655cbc00 fcvtzs z0\.s, p7/m, z0\.h
+.*: 655cbc00 fcvtzs z0\.s, p7/m, z0\.h
+.*: 655ca060 fcvtzs z0\.s, p0/m, z3\.h
+.*: 655ca060 fcvtzs z0\.s, p0/m, z3\.h
+.*: 655ca3e0 fcvtzs z0\.s, p0/m, z31\.h
+.*: 655ca3e0 fcvtzs z0\.s, p0/m, z31\.h
+.*: 655ea000 fcvtzs z0\.d, p0/m, z0\.h
+.*: 655ea000 fcvtzs z0\.d, p0/m, z0\.h
+.*: 655ea001 fcvtzs z1\.d, p0/m, z0\.h
+.*: 655ea001 fcvtzs z1\.d, p0/m, z0\.h
+.*: 655ea01f fcvtzs z31\.d, p0/m, z0\.h
+.*: 655ea01f fcvtzs z31\.d, p0/m, z0\.h
+.*: 655ea800 fcvtzs z0\.d, p2/m, z0\.h
+.*: 655ea800 fcvtzs z0\.d, p2/m, z0\.h
+.*: 655ebc00 fcvtzs z0\.d, p7/m, z0\.h
+.*: 655ebc00 fcvtzs z0\.d, p7/m, z0\.h
+.*: 655ea060 fcvtzs z0\.d, p0/m, z3\.h
+.*: 655ea060 fcvtzs z0\.d, p0/m, z3\.h
+.*: 655ea3e0 fcvtzs z0\.d, p0/m, z31\.h
+.*: 655ea3e0 fcvtzs z0\.d, p0/m, z31\.h
.*: 659ca000 fcvtzs z0\.s, p0/m, z0\.s
.*: 659ca000 fcvtzs z0\.s, p0/m, z0\.s
.*: 659ca001 fcvtzs z1\.s, p0/m, z0\.s
@@ -8932,6 +9588,48 @@ Disassembly of section .*:
.*: 65dea060 fcvtzs z0\.d, p0/m, z3\.d
.*: 65dea3e0 fcvtzs z0\.d, p0/m, z31\.d
.*: 65dea3e0 fcvtzs z0\.d, p0/m, z31\.d
+.*: 655ba000 fcvtzu z0\.h, p0/m, z0\.h
+.*: 655ba000 fcvtzu z0\.h, p0/m, z0\.h
+.*: 655ba001 fcvtzu z1\.h, p0/m, z0\.h
+.*: 655ba001 fcvtzu z1\.h, p0/m, z0\.h
+.*: 655ba01f fcvtzu z31\.h, p0/m, z0\.h
+.*: 655ba01f fcvtzu z31\.h, p0/m, z0\.h
+.*: 655ba800 fcvtzu z0\.h, p2/m, z0\.h
+.*: 655ba800 fcvtzu z0\.h, p2/m, z0\.h
+.*: 655bbc00 fcvtzu z0\.h, p7/m, z0\.h
+.*: 655bbc00 fcvtzu z0\.h, p7/m, z0\.h
+.*: 655ba060 fcvtzu z0\.h, p0/m, z3\.h
+.*: 655ba060 fcvtzu z0\.h, p0/m, z3\.h
+.*: 655ba3e0 fcvtzu z0\.h, p0/m, z31\.h
+.*: 655ba3e0 fcvtzu z0\.h, p0/m, z31\.h
+.*: 655da000 fcvtzu z0\.s, p0/m, z0\.h
+.*: 655da000 fcvtzu z0\.s, p0/m, z0\.h
+.*: 655da001 fcvtzu z1\.s, p0/m, z0\.h
+.*: 655da001 fcvtzu z1\.s, p0/m, z0\.h
+.*: 655da01f fcvtzu z31\.s, p0/m, z0\.h
+.*: 655da01f fcvtzu z31\.s, p0/m, z0\.h
+.*: 655da800 fcvtzu z0\.s, p2/m, z0\.h
+.*: 655da800 fcvtzu z0\.s, p2/m, z0\.h
+.*: 655dbc00 fcvtzu z0\.s, p7/m, z0\.h
+.*: 655dbc00 fcvtzu z0\.s, p7/m, z0\.h
+.*: 655da060 fcvtzu z0\.s, p0/m, z3\.h
+.*: 655da060 fcvtzu z0\.s, p0/m, z3\.h
+.*: 655da3e0 fcvtzu z0\.s, p0/m, z31\.h
+.*: 655da3e0 fcvtzu z0\.s, p0/m, z31\.h
+.*: 655fa000 fcvtzu z0\.d, p0/m, z0\.h
+.*: 655fa000 fcvtzu z0\.d, p0/m, z0\.h
+.*: 655fa001 fcvtzu z1\.d, p0/m, z0\.h
+.*: 655fa001 fcvtzu z1\.d, p0/m, z0\.h
+.*: 655fa01f fcvtzu z31\.d, p0/m, z0\.h
+.*: 655fa01f fcvtzu z31\.d, p0/m, z0\.h
+.*: 655fa800 fcvtzu z0\.d, p2/m, z0\.h
+.*: 655fa800 fcvtzu z0\.d, p2/m, z0\.h
+.*: 655fbc00 fcvtzu z0\.d, p7/m, z0\.h
+.*: 655fbc00 fcvtzu z0\.d, p7/m, z0\.h
+.*: 655fa060 fcvtzu z0\.d, p0/m, z3\.h
+.*: 655fa060 fcvtzu z0\.d, p0/m, z3\.h
+.*: 655fa3e0 fcvtzu z0\.d, p0/m, z31\.h
+.*: 655fa3e0 fcvtzu z0\.d, p0/m, z31\.h
.*: 659da000 fcvtzu z0\.s, p0/m, z0\.s
.*: 659da000 fcvtzu z0\.s, p0/m, z0\.s
.*: 659da001 fcvtzu z1\.s, p0/m, z0\.s
@@ -8988,6 +9686,22 @@ Disassembly of section .*:
.*: 65dfa060 fcvtzu z0\.d, p0/m, z3\.d
.*: 65dfa3e0 fcvtzu z0\.d, p0/m, z31\.d
.*: 65dfa3e0 fcvtzu z0\.d, p0/m, z31\.d
+.*: 654d8000 fdiv z0\.h, p0/m, z0\.h, z0\.h
+.*: 654d8000 fdiv z0\.h, p0/m, z0\.h, z0\.h
+.*: 654d8001 fdiv z1\.h, p0/m, z1\.h, z0\.h
+.*: 654d8001 fdiv z1\.h, p0/m, z1\.h, z0\.h
+.*: 654d801f fdiv z31\.h, p0/m, z31\.h, z0\.h
+.*: 654d801f fdiv z31\.h, p0/m, z31\.h, z0\.h
+.*: 654d8800 fdiv z0\.h, p2/m, z0\.h, z0\.h
+.*: 654d8800 fdiv z0\.h, p2/m, z0\.h, z0\.h
+.*: 654d9c00 fdiv z0\.h, p7/m, z0\.h, z0\.h
+.*: 654d9c00 fdiv z0\.h, p7/m, z0\.h, z0\.h
+.*: 654d8003 fdiv z3\.h, p0/m, z3\.h, z0\.h
+.*: 654d8003 fdiv z3\.h, p0/m, z3\.h, z0\.h
+.*: 654d8080 fdiv z0\.h, p0/m, z0\.h, z4\.h
+.*: 654d8080 fdiv z0\.h, p0/m, z0\.h, z4\.h
+.*: 654d83e0 fdiv z0\.h, p0/m, z0\.h, z31\.h
+.*: 654d83e0 fdiv z0\.h, p0/m, z0\.h, z31\.h
.*: 658d8000 fdiv z0\.s, p0/m, z0\.s, z0\.s
.*: 658d8000 fdiv z0\.s, p0/m, z0\.s, z0\.s
.*: 658d8001 fdiv z1\.s, p0/m, z1\.s, z0\.s
@@ -9020,6 +9734,22 @@ Disassembly of section .*:
.*: 65cd8080 fdiv z0\.d, p0/m, z0\.d, z4\.d
.*: 65cd83e0 fdiv z0\.d, p0/m, z0\.d, z31\.d
.*: 65cd83e0 fdiv z0\.d, p0/m, z0\.d, z31\.d
+.*: 654c8000 fdivr z0\.h, p0/m, z0\.h, z0\.h
+.*: 654c8000 fdivr z0\.h, p0/m, z0\.h, z0\.h
+.*: 654c8001 fdivr z1\.h, p0/m, z1\.h, z0\.h
+.*: 654c8001 fdivr z1\.h, p0/m, z1\.h, z0\.h
+.*: 654c801f fdivr z31\.h, p0/m, z31\.h, z0\.h
+.*: 654c801f fdivr z31\.h, p0/m, z31\.h, z0\.h
+.*: 654c8800 fdivr z0\.h, p2/m, z0\.h, z0\.h
+.*: 654c8800 fdivr z0\.h, p2/m, z0\.h, z0\.h
+.*: 654c9c00 fdivr z0\.h, p7/m, z0\.h, z0\.h
+.*: 654c9c00 fdivr z0\.h, p7/m, z0\.h, z0\.h
+.*: 654c8003 fdivr z3\.h, p0/m, z3\.h, z0\.h
+.*: 654c8003 fdivr z3\.h, p0/m, z3\.h, z0\.h
+.*: 654c8080 fdivr z0\.h, p0/m, z0\.h, z4\.h
+.*: 654c8080 fdivr z0\.h, p0/m, z0\.h, z4\.h
+.*: 654c83e0 fdivr z0\.h, p0/m, z0\.h, z31\.h
+.*: 654c83e0 fdivr z0\.h, p0/m, z0\.h, z31\.h
.*: 658c8000 fdivr z0\.s, p0/m, z0\.s, z0\.s
.*: 658c8000 fdivr z0\.s, p0/m, z0\.s, z0\.s
.*: 658c8001 fdivr z1\.s, p0/m, z1\.s, z0\.s
@@ -9052,6 +9782,24 @@ Disassembly of section .*:
.*: 65cc8080 fdivr z0\.d, p0/m, z0\.d, z4\.d
.*: 65cc83e0 fdivr z0\.d, p0/m, z0\.d, z31\.d
.*: 65cc83e0 fdivr z0\.d, p0/m, z0\.d, z31\.d
+.*: 2579c000 fmov z0\.h, #2\.0+e\+00
+.*: 2579c000 fmov z0\.h, #2\.0+e\+00
+.*: 2579c001 fmov z1\.h, #2\.0+e\+00
+.*: 2579c001 fmov z1\.h, #2\.0+e\+00
+.*: 2579c01f fmov z31\.h, #2\.0+e\+00
+.*: 2579c01f fmov z31\.h, #2\.0+e\+00
+.*: 2579c600 fmov z0\.h, #1\.60+e\+01
+.*: 2579c600 fmov z0\.h, #1\.60+e\+01
+.*: 2579c900 fmov z0\.h, #1\.8750+e-01
+.*: 2579c900 fmov z0\.h, #1\.8750+e-01
+.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
+.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
+.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
+.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
+.*: 2579d800 fmov z0\.h, #-1\.250+e-01
+.*: 2579d800 fmov z0\.h, #-1\.250+e-01
+.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
+.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
@@ -9088,6 +9836,16 @@ Disassembly of section .*:
.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
+.*: 0460b800 fexpa z0\.h, z0\.h
+.*: 0460b800 fexpa z0\.h, z0\.h
+.*: 0460b801 fexpa z1\.h, z0\.h
+.*: 0460b801 fexpa z1\.h, z0\.h
+.*: 0460b81f fexpa z31\.h, z0\.h
+.*: 0460b81f fexpa z31\.h, z0\.h
+.*: 0460b840 fexpa z0\.h, z2\.h
+.*: 0460b840 fexpa z0\.h, z2\.h
+.*: 0460bbe0 fexpa z0\.h, z31\.h
+.*: 0460bbe0 fexpa z0\.h, z31\.h
.*: 04a0b800 fexpa z0\.s, z0\.s
.*: 04a0b800 fexpa z0\.s, z0\.s
.*: 04a0b801 fexpa z1\.s, z0\.s
@@ -9108,6 +9866,24 @@ Disassembly of section .*:
.*: 04e0b840 fexpa z0\.d, z2\.d
.*: 04e0bbe0 fexpa z0\.d, z31\.d
.*: 04e0bbe0 fexpa z0\.d, z31\.d
+.*: 65608000 fmad z0\.h, p0/m, z0\.h, z0\.h
+.*: 65608000 fmad z0\.h, p0/m, z0\.h, z0\.h
+.*: 65608001 fmad z1\.h, p0/m, z0\.h, z0\.h
+.*: 65608001 fmad z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560801f fmad z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560801f fmad z31\.h, p0/m, z0\.h, z0\.h
+.*: 65608800 fmad z0\.h, p2/m, z0\.h, z0\.h
+.*: 65608800 fmad z0\.h, p2/m, z0\.h, z0\.h
+.*: 65609c00 fmad z0\.h, p7/m, z0\.h, z0\.h
+.*: 65609c00 fmad z0\.h, p7/m, z0\.h, z0\.h
+.*: 65608060 fmad z0\.h, p0/m, z3\.h, z0\.h
+.*: 65608060 fmad z0\.h, p0/m, z3\.h, z0\.h
+.*: 656083e0 fmad z0\.h, p0/m, z31\.h, z0\.h
+.*: 656083e0 fmad z0\.h, p0/m, z31\.h, z0\.h
+.*: 65648000 fmad z0\.h, p0/m, z0\.h, z4\.h
+.*: 65648000 fmad z0\.h, p0/m, z0\.h, z4\.h
+.*: 657f8000 fmad z0\.h, p0/m, z0\.h, z31\.h
+.*: 657f8000 fmad z0\.h, p0/m, z0\.h, z31\.h
.*: 65a08000 fmad z0\.s, p0/m, z0\.s, z0\.s
.*: 65a08000 fmad z0\.s, p0/m, z0\.s, z0\.s
.*: 65a08001 fmad z1\.s, p0/m, z0\.s, z0\.s
@@ -9144,6 +9920,22 @@ Disassembly of section .*:
.*: 65e48000 fmad z0\.d, p0/m, z0\.d, z4\.d
.*: 65ff8000 fmad z0\.d, p0/m, z0\.d, z31\.d
.*: 65ff8000 fmad z0\.d, p0/m, z0\.d, z31\.d
+.*: 65468000 fmax z0\.h, p0/m, z0\.h, z0\.h
+.*: 65468000 fmax z0\.h, p0/m, z0\.h, z0\.h
+.*: 65468001 fmax z1\.h, p0/m, z1\.h, z0\.h
+.*: 65468001 fmax z1\.h, p0/m, z1\.h, z0\.h
+.*: 6546801f fmax z31\.h, p0/m, z31\.h, z0\.h
+.*: 6546801f fmax z31\.h, p0/m, z31\.h, z0\.h
+.*: 65468800 fmax z0\.h, p2/m, z0\.h, z0\.h
+.*: 65468800 fmax z0\.h, p2/m, z0\.h, z0\.h
+.*: 65469c00 fmax z0\.h, p7/m, z0\.h, z0\.h
+.*: 65469c00 fmax z0\.h, p7/m, z0\.h, z0\.h
+.*: 65468003 fmax z3\.h, p0/m, z3\.h, z0\.h
+.*: 65468003 fmax z3\.h, p0/m, z3\.h, z0\.h
+.*: 65468080 fmax z0\.h, p0/m, z0\.h, z4\.h
+.*: 65468080 fmax z0\.h, p0/m, z0\.h, z4\.h
+.*: 654683e0 fmax z0\.h, p0/m, z0\.h, z31\.h
+.*: 654683e0 fmax z0\.h, p0/m, z0\.h, z31\.h
.*: 65868000 fmax z0\.s, p0/m, z0\.s, z0\.s
.*: 65868000 fmax z0\.s, p0/m, z0\.s, z0\.s
.*: 65868001 fmax z1\.s, p0/m, z1\.s, z0\.s
@@ -9176,6 +9968,34 @@ Disassembly of section .*:
.*: 65c68080 fmax z0\.d, p0/m, z0\.d, z4\.d
.*: 65c683e0 fmax z0\.d, p0/m, z0\.d, z31\.d
.*: 65c683e0 fmax z0\.d, p0/m, z0\.d, z31\.d
+.*: 655e8000 fmax z0\.h, p0/m, z0\.h, #0\.0
+.*: 655e8000 fmax z0\.h, p0/m, z0\.h, #0\.0
+.*: 655e8000 fmax z0\.h, p0/m, z0\.h, #0\.0
+.*: 655e8000 fmax z0\.h, p0/m, z0\.h, #0\.0
+.*: 655e8001 fmax z1\.h, p0/m, z1\.h, #0\.0
+.*: 655e8001 fmax z1\.h, p0/m, z1\.h, #0\.0
+.*: 655e8001 fmax z1\.h, p0/m, z1\.h, #0\.0
+.*: 655e8001 fmax z1\.h, p0/m, z1\.h, #0\.0
+.*: 655e801f fmax z31\.h, p0/m, z31\.h, #0\.0
+.*: 655e801f fmax z31\.h, p0/m, z31\.h, #0\.0
+.*: 655e801f fmax z31\.h, p0/m, z31\.h, #0\.0
+.*: 655e801f fmax z31\.h, p0/m, z31\.h, #0\.0
+.*: 655e8800 fmax z0\.h, p2/m, z0\.h, #0\.0
+.*: 655e8800 fmax z0\.h, p2/m, z0\.h, #0\.0
+.*: 655e8800 fmax z0\.h, p2/m, z0\.h, #0\.0
+.*: 655e8800 fmax z0\.h, p2/m, z0\.h, #0\.0
+.*: 655e9c00 fmax z0\.h, p7/m, z0\.h, #0\.0
+.*: 655e9c00 fmax z0\.h, p7/m, z0\.h, #0\.0
+.*: 655e9c00 fmax z0\.h, p7/m, z0\.h, #0\.0
+.*: 655e9c00 fmax z0\.h, p7/m, z0\.h, #0\.0
+.*: 655e8003 fmax z3\.h, p0/m, z3\.h, #0\.0
+.*: 655e8003 fmax z3\.h, p0/m, z3\.h, #0\.0
+.*: 655e8003 fmax z3\.h, p0/m, z3\.h, #0\.0
+.*: 655e8003 fmax z3\.h, p0/m, z3\.h, #0\.0
+.*: 655e8020 fmax z0\.h, p0/m, z0\.h, #1\.0
+.*: 655e8020 fmax z0\.h, p0/m, z0\.h, #1\.0
+.*: 655e8020 fmax z0\.h, p0/m, z0\.h, #1\.0
+.*: 655e8020 fmax z0\.h, p0/m, z0\.h, #1\.0
.*: 659e8000 fmax z0\.s, p0/m, z0\.s, #0\.0
.*: 659e8000 fmax z0\.s, p0/m, z0\.s, #0\.0
.*: 659e8000 fmax z0\.s, p0/m, z0\.s, #0\.0
@@ -9232,6 +10052,22 @@ Disassembly of section .*:
.*: 65de8020 fmax z0\.d, p0/m, z0\.d, #1\.0
.*: 65de8020 fmax z0\.d, p0/m, z0\.d, #1\.0
.*: 65de8020 fmax z0\.d, p0/m, z0\.d, #1\.0
+.*: 65448000 fmaxnm z0\.h, p0/m, z0\.h, z0\.h
+.*: 65448000 fmaxnm z0\.h, p0/m, z0\.h, z0\.h
+.*: 65448001 fmaxnm z1\.h, p0/m, z1\.h, z0\.h
+.*: 65448001 fmaxnm z1\.h, p0/m, z1\.h, z0\.h
+.*: 6544801f fmaxnm z31\.h, p0/m, z31\.h, z0\.h
+.*: 6544801f fmaxnm z31\.h, p0/m, z31\.h, z0\.h
+.*: 65448800 fmaxnm z0\.h, p2/m, z0\.h, z0\.h
+.*: 65448800 fmaxnm z0\.h, p2/m, z0\.h, z0\.h
+.*: 65449c00 fmaxnm z0\.h, p7/m, z0\.h, z0\.h
+.*: 65449c00 fmaxnm z0\.h, p7/m, z0\.h, z0\.h
+.*: 65448003 fmaxnm z3\.h, p0/m, z3\.h, z0\.h
+.*: 65448003 fmaxnm z3\.h, p0/m, z3\.h, z0\.h
+.*: 65448080 fmaxnm z0\.h, p0/m, z0\.h, z4\.h
+.*: 65448080 fmaxnm z0\.h, p0/m, z0\.h, z4\.h
+.*: 654483e0 fmaxnm z0\.h, p0/m, z0\.h, z31\.h
+.*: 654483e0 fmaxnm z0\.h, p0/m, z0\.h, z31\.h
.*: 65848000 fmaxnm z0\.s, p0/m, z0\.s, z0\.s
.*: 65848000 fmaxnm z0\.s, p0/m, z0\.s, z0\.s
.*: 65848001 fmaxnm z1\.s, p0/m, z1\.s, z0\.s
@@ -9264,6 +10100,34 @@ Disassembly of section .*:
.*: 65c48080 fmaxnm z0\.d, p0/m, z0\.d, z4\.d
.*: 65c483e0 fmaxnm z0\.d, p0/m, z0\.d, z31\.d
.*: 65c483e0 fmaxnm z0\.d, p0/m, z0\.d, z31\.d
+.*: 655c8000 fmaxnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655c8000 fmaxnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655c8000 fmaxnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655c8000 fmaxnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655c8001 fmaxnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655c8001 fmaxnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655c8001 fmaxnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655c8001 fmaxnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655c801f fmaxnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655c801f fmaxnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655c801f fmaxnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655c801f fmaxnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655c8800 fmaxnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655c8800 fmaxnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655c8800 fmaxnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655c8800 fmaxnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655c9c00 fmaxnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655c9c00 fmaxnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655c9c00 fmaxnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655c9c00 fmaxnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655c8003 fmaxnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655c8003 fmaxnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655c8003 fmaxnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655c8003 fmaxnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655c8020 fmaxnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655c8020 fmaxnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655c8020 fmaxnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655c8020 fmaxnm z0\.h, p0/m, z0\.h, #1\.0
.*: 659c8000 fmaxnm z0\.s, p0/m, z0\.s, #0\.0
.*: 659c8000 fmaxnm z0\.s, p0/m, z0\.s, #0\.0
.*: 659c8000 fmaxnm z0\.s, p0/m, z0\.s, #0\.0
@@ -9320,6 +10184,20 @@ Disassembly of section .*:
.*: 65dc8020 fmaxnm z0\.d, p0/m, z0\.d, #1\.0
.*: 65dc8020 fmaxnm z0\.d, p0/m, z0\.d, #1\.0
.*: 65dc8020 fmaxnm z0\.d, p0/m, z0\.d, #1\.0
+.*: 65442000 fmaxnmv h0, p0, z0\.h
+.*: 65442000 fmaxnmv h0, p0, z0\.h
+.*: 65442001 fmaxnmv h1, p0, z0\.h
+.*: 65442001 fmaxnmv h1, p0, z0\.h
+.*: 6544201f fmaxnmv h31, p0, z0\.h
+.*: 6544201f fmaxnmv h31, p0, z0\.h
+.*: 65442800 fmaxnmv h0, p2, z0\.h
+.*: 65442800 fmaxnmv h0, p2, z0\.h
+.*: 65443c00 fmaxnmv h0, p7, z0\.h
+.*: 65443c00 fmaxnmv h0, p7, z0\.h
+.*: 65442060 fmaxnmv h0, p0, z3\.h
+.*: 65442060 fmaxnmv h0, p0, z3\.h
+.*: 654423e0 fmaxnmv h0, p0, z31\.h
+.*: 654423e0 fmaxnmv h0, p0, z31\.h
.*: 65842000 fmaxnmv s0, p0, z0\.s
.*: 65842000 fmaxnmv s0, p0, z0\.s
.*: 65842001 fmaxnmv s1, p0, z0\.s
@@ -9348,6 +10226,20 @@ Disassembly of section .*:
.*: 65c42060 fmaxnmv d0, p0, z3\.d
.*: 65c423e0 fmaxnmv d0, p0, z31\.d
.*: 65c423e0 fmaxnmv d0, p0, z31\.d
+.*: 65462000 fmaxv h0, p0, z0\.h
+.*: 65462000 fmaxv h0, p0, z0\.h
+.*: 65462001 fmaxv h1, p0, z0\.h
+.*: 65462001 fmaxv h1, p0, z0\.h
+.*: 6546201f fmaxv h31, p0, z0\.h
+.*: 6546201f fmaxv h31, p0, z0\.h
+.*: 65462800 fmaxv h0, p2, z0\.h
+.*: 65462800 fmaxv h0, p2, z0\.h
+.*: 65463c00 fmaxv h0, p7, z0\.h
+.*: 65463c00 fmaxv h0, p7, z0\.h
+.*: 65462060 fmaxv h0, p0, z3\.h
+.*: 65462060 fmaxv h0, p0, z3\.h
+.*: 654623e0 fmaxv h0, p0, z31\.h
+.*: 654623e0 fmaxv h0, p0, z31\.h
.*: 65862000 fmaxv s0, p0, z0\.s
.*: 65862000 fmaxv s0, p0, z0\.s
.*: 65862001 fmaxv s1, p0, z0\.s
@@ -9376,6 +10268,22 @@ Disassembly of section .*:
.*: 65c62060 fmaxv d0, p0, z3\.d
.*: 65c623e0 fmaxv d0, p0, z31\.d
.*: 65c623e0 fmaxv d0, p0, z31\.d
+.*: 65478000 fmin z0\.h, p0/m, z0\.h, z0\.h
+.*: 65478000 fmin z0\.h, p0/m, z0\.h, z0\.h
+.*: 65478001 fmin z1\.h, p0/m, z1\.h, z0\.h
+.*: 65478001 fmin z1\.h, p0/m, z1\.h, z0\.h
+.*: 6547801f fmin z31\.h, p0/m, z31\.h, z0\.h
+.*: 6547801f fmin z31\.h, p0/m, z31\.h, z0\.h
+.*: 65478800 fmin z0\.h, p2/m, z0\.h, z0\.h
+.*: 65478800 fmin z0\.h, p2/m, z0\.h, z0\.h
+.*: 65479c00 fmin z0\.h, p7/m, z0\.h, z0\.h
+.*: 65479c00 fmin z0\.h, p7/m, z0\.h, z0\.h
+.*: 65478003 fmin z3\.h, p0/m, z3\.h, z0\.h
+.*: 65478003 fmin z3\.h, p0/m, z3\.h, z0\.h
+.*: 65478080 fmin z0\.h, p0/m, z0\.h, z4\.h
+.*: 65478080 fmin z0\.h, p0/m, z0\.h, z4\.h
+.*: 654783e0 fmin z0\.h, p0/m, z0\.h, z31\.h
+.*: 654783e0 fmin z0\.h, p0/m, z0\.h, z31\.h
.*: 65878000 fmin z0\.s, p0/m, z0\.s, z0\.s
.*: 65878000 fmin z0\.s, p0/m, z0\.s, z0\.s
.*: 65878001 fmin z1\.s, p0/m, z1\.s, z0\.s
@@ -9408,6 +10316,34 @@ Disassembly of section .*:
.*: 65c78080 fmin z0\.d, p0/m, z0\.d, z4\.d
.*: 65c783e0 fmin z0\.d, p0/m, z0\.d, z31\.d
.*: 65c783e0 fmin z0\.d, p0/m, z0\.d, z31\.d
+.*: 655f8000 fmin z0\.h, p0/m, z0\.h, #0\.0
+.*: 655f8000 fmin z0\.h, p0/m, z0\.h, #0\.0
+.*: 655f8000 fmin z0\.h, p0/m, z0\.h, #0\.0
+.*: 655f8000 fmin z0\.h, p0/m, z0\.h, #0\.0
+.*: 655f8001 fmin z1\.h, p0/m, z1\.h, #0\.0
+.*: 655f8001 fmin z1\.h, p0/m, z1\.h, #0\.0
+.*: 655f8001 fmin z1\.h, p0/m, z1\.h, #0\.0
+.*: 655f8001 fmin z1\.h, p0/m, z1\.h, #0\.0
+.*: 655f801f fmin z31\.h, p0/m, z31\.h, #0\.0
+.*: 655f801f fmin z31\.h, p0/m, z31\.h, #0\.0
+.*: 655f801f fmin z31\.h, p0/m, z31\.h, #0\.0
+.*: 655f801f fmin z31\.h, p0/m, z31\.h, #0\.0
+.*: 655f8800 fmin z0\.h, p2/m, z0\.h, #0\.0
+.*: 655f8800 fmin z0\.h, p2/m, z0\.h, #0\.0
+.*: 655f8800 fmin z0\.h, p2/m, z0\.h, #0\.0
+.*: 655f8800 fmin z0\.h, p2/m, z0\.h, #0\.0
+.*: 655f9c00 fmin z0\.h, p7/m, z0\.h, #0\.0
+.*: 655f9c00 fmin z0\.h, p7/m, z0\.h, #0\.0
+.*: 655f9c00 fmin z0\.h, p7/m, z0\.h, #0\.0
+.*: 655f9c00 fmin z0\.h, p7/m, z0\.h, #0\.0
+.*: 655f8003 fmin z3\.h, p0/m, z3\.h, #0\.0
+.*: 655f8003 fmin z3\.h, p0/m, z3\.h, #0\.0
+.*: 655f8003 fmin z3\.h, p0/m, z3\.h, #0\.0
+.*: 655f8003 fmin z3\.h, p0/m, z3\.h, #0\.0
+.*: 655f8020 fmin z0\.h, p0/m, z0\.h, #1\.0
+.*: 655f8020 fmin z0\.h, p0/m, z0\.h, #1\.0
+.*: 655f8020 fmin z0\.h, p0/m, z0\.h, #1\.0
+.*: 655f8020 fmin z0\.h, p0/m, z0\.h, #1\.0
.*: 659f8000 fmin z0\.s, p0/m, z0\.s, #0\.0
.*: 659f8000 fmin z0\.s, p0/m, z0\.s, #0\.0
.*: 659f8000 fmin z0\.s, p0/m, z0\.s, #0\.0
@@ -9464,6 +10400,22 @@ Disassembly of section .*:
.*: 65df8020 fmin z0\.d, p0/m, z0\.d, #1\.0
.*: 65df8020 fmin z0\.d, p0/m, z0\.d, #1\.0
.*: 65df8020 fmin z0\.d, p0/m, z0\.d, #1\.0
+.*: 65458000 fminnm z0\.h, p0/m, z0\.h, z0\.h
+.*: 65458000 fminnm z0\.h, p0/m, z0\.h, z0\.h
+.*: 65458001 fminnm z1\.h, p0/m, z1\.h, z0\.h
+.*: 65458001 fminnm z1\.h, p0/m, z1\.h, z0\.h
+.*: 6545801f fminnm z31\.h, p0/m, z31\.h, z0\.h
+.*: 6545801f fminnm z31\.h, p0/m, z31\.h, z0\.h
+.*: 65458800 fminnm z0\.h, p2/m, z0\.h, z0\.h
+.*: 65458800 fminnm z0\.h, p2/m, z0\.h, z0\.h
+.*: 65459c00 fminnm z0\.h, p7/m, z0\.h, z0\.h
+.*: 65459c00 fminnm z0\.h, p7/m, z0\.h, z0\.h
+.*: 65458003 fminnm z3\.h, p0/m, z3\.h, z0\.h
+.*: 65458003 fminnm z3\.h, p0/m, z3\.h, z0\.h
+.*: 65458080 fminnm z0\.h, p0/m, z0\.h, z4\.h
+.*: 65458080 fminnm z0\.h, p0/m, z0\.h, z4\.h
+.*: 654583e0 fminnm z0\.h, p0/m, z0\.h, z31\.h
+.*: 654583e0 fminnm z0\.h, p0/m, z0\.h, z31\.h
.*: 65858000 fminnm z0\.s, p0/m, z0\.s, z0\.s
.*: 65858000 fminnm z0\.s, p0/m, z0\.s, z0\.s
.*: 65858001 fminnm z1\.s, p0/m, z1\.s, z0\.s
@@ -9496,6 +10448,34 @@ Disassembly of section .*:
.*: 65c58080 fminnm z0\.d, p0/m, z0\.d, z4\.d
.*: 65c583e0 fminnm z0\.d, p0/m, z0\.d, z31\.d
.*: 65c583e0 fminnm z0\.d, p0/m, z0\.d, z31\.d
+.*: 655d8000 fminnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655d8000 fminnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655d8000 fminnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655d8000 fminnm z0\.h, p0/m, z0\.h, #0\.0
+.*: 655d8001 fminnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655d8001 fminnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655d8001 fminnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655d8001 fminnm z1\.h, p0/m, z1\.h, #0\.0
+.*: 655d801f fminnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655d801f fminnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655d801f fminnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655d801f fminnm z31\.h, p0/m, z31\.h, #0\.0
+.*: 655d8800 fminnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655d8800 fminnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655d8800 fminnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655d8800 fminnm z0\.h, p2/m, z0\.h, #0\.0
+.*: 655d9c00 fminnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655d9c00 fminnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655d9c00 fminnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655d9c00 fminnm z0\.h, p7/m, z0\.h, #0\.0
+.*: 655d8003 fminnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655d8003 fminnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655d8003 fminnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655d8003 fminnm z3\.h, p0/m, z3\.h, #0\.0
+.*: 655d8020 fminnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655d8020 fminnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655d8020 fminnm z0\.h, p0/m, z0\.h, #1\.0
+.*: 655d8020 fminnm z0\.h, p0/m, z0\.h, #1\.0
.*: 659d8000 fminnm z0\.s, p0/m, z0\.s, #0\.0
.*: 659d8000 fminnm z0\.s, p0/m, z0\.s, #0\.0
.*: 659d8000 fminnm z0\.s, p0/m, z0\.s, #0\.0
@@ -9552,6 +10532,20 @@ Disassembly of section .*:
.*: 65dd8020 fminnm z0\.d, p0/m, z0\.d, #1\.0
.*: 65dd8020 fminnm z0\.d, p0/m, z0\.d, #1\.0
.*: 65dd8020 fminnm z0\.d, p0/m, z0\.d, #1\.0
+.*: 65452000 fminnmv h0, p0, z0\.h
+.*: 65452000 fminnmv h0, p0, z0\.h
+.*: 65452001 fminnmv h1, p0, z0\.h
+.*: 65452001 fminnmv h1, p0, z0\.h
+.*: 6545201f fminnmv h31, p0, z0\.h
+.*: 6545201f fminnmv h31, p0, z0\.h
+.*: 65452800 fminnmv h0, p2, z0\.h
+.*: 65452800 fminnmv h0, p2, z0\.h
+.*: 65453c00 fminnmv h0, p7, z0\.h
+.*: 65453c00 fminnmv h0, p7, z0\.h
+.*: 65452060 fminnmv h0, p0, z3\.h
+.*: 65452060 fminnmv h0, p0, z3\.h
+.*: 654523e0 fminnmv h0, p0, z31\.h
+.*: 654523e0 fminnmv h0, p0, z31\.h
.*: 65852000 fminnmv s0, p0, z0\.s
.*: 65852000 fminnmv s0, p0, z0\.s
.*: 65852001 fminnmv s1, p0, z0\.s
@@ -9580,6 +10574,20 @@ Disassembly of section .*:
.*: 65c52060 fminnmv d0, p0, z3\.d
.*: 65c523e0 fminnmv d0, p0, z31\.d
.*: 65c523e0 fminnmv d0, p0, z31\.d
+.*: 65472000 fminv h0, p0, z0\.h
+.*: 65472000 fminv h0, p0, z0\.h
+.*: 65472001 fminv h1, p0, z0\.h
+.*: 65472001 fminv h1, p0, z0\.h
+.*: 6547201f fminv h31, p0, z0\.h
+.*: 6547201f fminv h31, p0, z0\.h
+.*: 65472800 fminv h0, p2, z0\.h
+.*: 65472800 fminv h0, p2, z0\.h
+.*: 65473c00 fminv h0, p7, z0\.h
+.*: 65473c00 fminv h0, p7, z0\.h
+.*: 65472060 fminv h0, p0, z3\.h
+.*: 65472060 fminv h0, p0, z3\.h
+.*: 654723e0 fminv h0, p0, z31\.h
+.*: 654723e0 fminv h0, p0, z31\.h
.*: 65872000 fminv s0, p0, z0\.s
.*: 65872000 fminv s0, p0, z0\.s
.*: 65872001 fminv s1, p0, z0\.s
@@ -9608,6 +10616,24 @@ Disassembly of section .*:
.*: 65c72060 fminv d0, p0, z3\.d
.*: 65c723e0 fminv d0, p0, z31\.d
.*: 65c723e0 fminv d0, p0, z31\.d
+.*: 65600000 fmla z0\.h, p0/m, z0\.h, z0\.h
+.*: 65600000 fmla z0\.h, p0/m, z0\.h, z0\.h
+.*: 65600001 fmla z1\.h, p0/m, z0\.h, z0\.h
+.*: 65600001 fmla z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560001f fmla z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560001f fmla z31\.h, p0/m, z0\.h, z0\.h
+.*: 65600800 fmla z0\.h, p2/m, z0\.h, z0\.h
+.*: 65600800 fmla z0\.h, p2/m, z0\.h, z0\.h
+.*: 65601c00 fmla z0\.h, p7/m, z0\.h, z0\.h
+.*: 65601c00 fmla z0\.h, p7/m, z0\.h, z0\.h
+.*: 65600060 fmla z0\.h, p0/m, z3\.h, z0\.h
+.*: 65600060 fmla z0\.h, p0/m, z3\.h, z0\.h
+.*: 656003e0 fmla z0\.h, p0/m, z31\.h, z0\.h
+.*: 656003e0 fmla z0\.h, p0/m, z31\.h, z0\.h
+.*: 65640000 fmla z0\.h, p0/m, z0\.h, z4\.h
+.*: 65640000 fmla z0\.h, p0/m, z0\.h, z4\.h
+.*: 657f0000 fmla z0\.h, p0/m, z0\.h, z31\.h
+.*: 657f0000 fmla z0\.h, p0/m, z0\.h, z31\.h
.*: 65a00000 fmla z0\.s, p0/m, z0\.s, z0\.s
.*: 65a00000 fmla z0\.s, p0/m, z0\.s, z0\.s
.*: 65a00001 fmla z1\.s, p0/m, z0\.s, z0\.s
@@ -9644,6 +10670,90 @@ Disassembly of section .*:
.*: 65e40000 fmla z0\.d, p0/m, z0\.d, z4\.d
.*: 65ff0000 fmla z0\.d, p0/m, z0\.d, z31\.d
.*: 65ff0000 fmla z0\.d, p0/m, z0\.d, z31\.d
+.*: 64200000 fmla z0\.h, z0\.h, z0\.h\[0\]
+.*: 64200000 fmla z0\.h, z0\.h, z0\.h\[0\]
+.*: 64200001 fmla z1\.h, z0\.h, z0\.h\[0\]
+.*: 64200001 fmla z1\.h, z0\.h, z0\.h\[0\]
+.*: 6420001f fmla z31\.h, z0\.h, z0\.h\[0\]
+.*: 6420001f fmla z31\.h, z0\.h, z0\.h\[0\]
+.*: 64200040 fmla z0\.h, z2\.h, z0\.h\[0\]
+.*: 64200040 fmla z0\.h, z2\.h, z0\.h\[0\]
+.*: 642003e0 fmla z0\.h, z31\.h, z0\.h\[0\]
+.*: 642003e0 fmla z0\.h, z31\.h, z0\.h\[0\]
+.*: 64230000 fmla z0\.h, z0\.h, z3\.h\[0\]
+.*: 64230000 fmla z0\.h, z0\.h, z3\.h\[0\]
+.*: 64270000 fmla z0\.h, z0\.h, z7\.h\[0\]
+.*: 64270000 fmla z0\.h, z0\.h, z7\.h\[0\]
+.*: 64280000 fmla z0\.h, z0\.h, z0\.h\[1\]
+.*: 64280000 fmla z0\.h, z0\.h, z0\.h\[1\]
+.*: 642c0000 fmla z0\.h, z0\.h, z4\.h\[1\]
+.*: 642c0000 fmla z0\.h, z0\.h, z4\.h\[1\]
+.*: 64630000 fmla z0\.h, z0\.h, z3\.h\[4\]
+.*: 64630000 fmla z0\.h, z0\.h, z3\.h\[4\]
+.*: 64780000 fmla z0\.h, z0\.h, z0\.h\[7\]
+.*: 64780000 fmla z0\.h, z0\.h, z0\.h\[7\]
+.*: 647d0000 fmla z0\.h, z0\.h, z5\.h\[7\]
+.*: 647d0000 fmla z0\.h, z0\.h, z5\.h\[7\]
+.*: 64a00000 fmla z0\.s, z0\.s, z0\.s\[0\]
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+.*: 64a00001 fmla z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a00001 fmla z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a0001f fmla z31\.s, z0\.s, z0\.s\[0\]
+.*: 64a0001f fmla z31\.s, z0\.s, z0\.s\[0\]
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+.*: 64a00040 fmla z0\.s, z2\.s, z0\.s\[0\]
+.*: 64a003e0 fmla z0\.s, z31\.s, z0\.s\[0\]
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+.*: 64b30000 fmla z0\.s, z0\.s, z3\.s\[2\]
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+.*: 64b80000 fmla z0\.s, z0\.s, z0\.s\[3\]
+.*: 64bd0000 fmla z0\.s, z0\.s, z5\.s\[3\]
+.*: 64bd0000 fmla z0\.s, z0\.s, z5\.s\[3\]
+.*: 64e00000 fmla z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e00000 fmla z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e00001 fmla z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e00001 fmla z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e0001f fmla z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e0001f fmla z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e00040 fmla z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e00040 fmla z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e003e0 fmla z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e003e0 fmla z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e30000 fmla z0\.d, z0\.d, z3\.d\[0\]
+.*: 64e30000 fmla z0\.d, z0\.d, z3\.d\[0\]
+.*: 64ef0000 fmla z0\.d, z0\.d, z15\.d\[0\]
+.*: 64ef0000 fmla z0\.d, z0\.d, z15\.d\[0\]
+.*: 64f00000 fmla z0\.d, z0\.d, z0\.d\[1\]
+.*: 64f00000 fmla z0\.d, z0\.d, z0\.d\[1\]
+.*: 64fb0000 fmla z0\.d, z0\.d, z11\.d\[1\]
+.*: 64fb0000 fmla z0\.d, z0\.d, z11\.d\[1\]
+.*: 65602000 fmls z0\.h, p0/m, z0\.h, z0\.h
+.*: 65602000 fmls z0\.h, p0/m, z0\.h, z0\.h
+.*: 65602001 fmls z1\.h, p0/m, z0\.h, z0\.h
+.*: 65602001 fmls z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560201f fmls z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560201f fmls z31\.h, p0/m, z0\.h, z0\.h
+.*: 65602800 fmls z0\.h, p2/m, z0\.h, z0\.h
+.*: 65602800 fmls z0\.h, p2/m, z0\.h, z0\.h
+.*: 65603c00 fmls z0\.h, p7/m, z0\.h, z0\.h
+.*: 65603c00 fmls z0\.h, p7/m, z0\.h, z0\.h
+.*: 65602060 fmls z0\.h, p0/m, z3\.h, z0\.h
+.*: 65602060 fmls z0\.h, p0/m, z3\.h, z0\.h
+.*: 656023e0 fmls z0\.h, p0/m, z31\.h, z0\.h
+.*: 656023e0 fmls z0\.h, p0/m, z31\.h, z0\.h
+.*: 65642000 fmls z0\.h, p0/m, z0\.h, z4\.h
+.*: 65642000 fmls z0\.h, p0/m, z0\.h, z4\.h
+.*: 657f2000 fmls z0\.h, p0/m, z0\.h, z31\.h
+.*: 657f2000 fmls z0\.h, p0/m, z0\.h, z31\.h
.*: 65a02000 fmls z0\.s, p0/m, z0\.s, z0\.s
.*: 65a02000 fmls z0\.s, p0/m, z0\.s, z0\.s
.*: 65a02001 fmls z1\.s, p0/m, z0\.s, z0\.s
@@ -9680,6 +10790,90 @@ Disassembly of section .*:
.*: 65e42000 fmls z0\.d, p0/m, z0\.d, z4\.d
.*: 65ff2000 fmls z0\.d, p0/m, z0\.d, z31\.d
.*: 65ff2000 fmls z0\.d, p0/m, z0\.d, z31\.d
+.*: 64200400 fmls z0\.h, z0\.h, z0\.h\[0\]
+.*: 64200400 fmls z0\.h, z0\.h, z0\.h\[0\]
+.*: 64200401 fmls z1\.h, z0\.h, z0\.h\[0\]
+.*: 64200401 fmls z1\.h, z0\.h, z0\.h\[0\]
+.*: 6420041f fmls z31\.h, z0\.h, z0\.h\[0\]
+.*: 6420041f fmls z31\.h, z0\.h, z0\.h\[0\]
+.*: 64200440 fmls z0\.h, z2\.h, z0\.h\[0\]
+.*: 64200440 fmls z0\.h, z2\.h, z0\.h\[0\]
+.*: 642007e0 fmls z0\.h, z31\.h, z0\.h\[0\]
+.*: 642007e0 fmls z0\.h, z31\.h, z0\.h\[0\]
+.*: 64230400 fmls z0\.h, z0\.h, z3\.h\[0\]
+.*: 64230400 fmls z0\.h, z0\.h, z3\.h\[0\]
+.*: 64270400 fmls z0\.h, z0\.h, z7\.h\[0\]
+.*: 64270400 fmls z0\.h, z0\.h, z7\.h\[0\]
+.*: 64280400 fmls z0\.h, z0\.h, z0\.h\[1\]
+.*: 64280400 fmls z0\.h, z0\.h, z0\.h\[1\]
+.*: 642c0400 fmls z0\.h, z0\.h, z4\.h\[1\]
+.*: 642c0400 fmls z0\.h, z0\.h, z4\.h\[1\]
+.*: 64630400 fmls z0\.h, z0\.h, z3\.h\[4\]
+.*: 64630400 fmls z0\.h, z0\.h, z3\.h\[4\]
+.*: 64780400 fmls z0\.h, z0\.h, z0\.h\[7\]
+.*: 64780400 fmls z0\.h, z0\.h, z0\.h\[7\]
+.*: 647d0400 fmls z0\.h, z0\.h, z5\.h\[7\]
+.*: 647d0400 fmls z0\.h, z0\.h, z5\.h\[7\]
+.*: 64a00400 fmls z0\.s, z0\.s, z0\.s\[0\]
+.*: 64a00400 fmls z0\.s, z0\.s, z0\.s\[0\]
+.*: 64a00401 fmls z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a00401 fmls z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a0041f fmls z31\.s, z0\.s, z0\.s\[0\]
+.*: 64a0041f fmls z31\.s, z0\.s, z0\.s\[0\]
+.*: 64a00440 fmls z0\.s, z2\.s, z0\.s\[0\]
+.*: 64a00440 fmls z0\.s, z2\.s, z0\.s\[0\]
+.*: 64a007e0 fmls z0\.s, z31\.s, z0\.s\[0\]
+.*: 64a007e0 fmls z0\.s, z31\.s, z0\.s\[0\]
+.*: 64a30400 fmls z0\.s, z0\.s, z3\.s\[0\]
+.*: 64a30400 fmls z0\.s, z0\.s, z3\.s\[0\]
+.*: 64a70400 fmls z0\.s, z0\.s, z7\.s\[0\]
+.*: 64a70400 fmls z0\.s, z0\.s, z7\.s\[0\]
+.*: 64a80400 fmls z0\.s, z0\.s, z0\.s\[1\]
+.*: 64a80400 fmls z0\.s, z0\.s, z0\.s\[1\]
+.*: 64ac0400 fmls z0\.s, z0\.s, z4\.s\[1\]
+.*: 64ac0400 fmls z0\.s, z0\.s, z4\.s\[1\]
+.*: 64b30400 fmls z0\.s, z0\.s, z3\.s\[2\]
+.*: 64b30400 fmls z0\.s, z0\.s, z3\.s\[2\]
+.*: 64b80400 fmls z0\.s, z0\.s, z0\.s\[3\]
+.*: 64b80400 fmls z0\.s, z0\.s, z0\.s\[3\]
+.*: 64bd0400 fmls z0\.s, z0\.s, z5\.s\[3\]
+.*: 64bd0400 fmls z0\.s, z0\.s, z5\.s\[3\]
+.*: 64e00400 fmls z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e00400 fmls z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e00401 fmls z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e00401 fmls z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e0041f fmls z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e0041f fmls z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e00440 fmls z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e00440 fmls z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e007e0 fmls z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e007e0 fmls z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e30400 fmls z0\.d, z0\.d, z3\.d\[0\]
+.*: 64e30400 fmls z0\.d, z0\.d, z3\.d\[0\]
+.*: 64ef0400 fmls z0\.d, z0\.d, z15\.d\[0\]
+.*: 64ef0400 fmls z0\.d, z0\.d, z15\.d\[0\]
+.*: 64f00400 fmls z0\.d, z0\.d, z0\.d\[1\]
+.*: 64f00400 fmls z0\.d, z0\.d, z0\.d\[1\]
+.*: 64fb0400 fmls z0\.d, z0\.d, z11\.d\[1\]
+.*: 64fb0400 fmls z0\.d, z0\.d, z11\.d\[1\]
+.*: 6560a000 fmsb z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560a000 fmsb z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560a001 fmsb z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560a001 fmsb z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560a01f fmsb z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560a01f fmsb z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560a800 fmsb z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560a800 fmsb z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560bc00 fmsb z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560bc00 fmsb z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560a060 fmsb z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560a060 fmsb z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560a3e0 fmsb z0\.h, p0/m, z31\.h, z0\.h
+.*: 6560a3e0 fmsb z0\.h, p0/m, z31\.h, z0\.h
+.*: 6564a000 fmsb z0\.h, p0/m, z0\.h, z4\.h
+.*: 6564a000 fmsb z0\.h, p0/m, z0\.h, z4\.h
+.*: 657fa000 fmsb z0\.h, p0/m, z0\.h, z31\.h
+.*: 657fa000 fmsb z0\.h, p0/m, z0\.h, z31\.h
.*: 65a0a000 fmsb z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0a000 fmsb z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0a001 fmsb z1\.s, p0/m, z0\.s, z0\.s
@@ -9716,6 +10910,20 @@ Disassembly of section .*:
.*: 65e4a000 fmsb z0\.d, p0/m, z0\.d, z4\.d
.*: 65ffa000 fmsb z0\.d, p0/m, z0\.d, z31\.d
.*: 65ffa000 fmsb z0\.d, p0/m, z0\.d, z31\.d
+.*: 65400800 fmul z0\.h, z0\.h, z0\.h
+.*: 65400800 fmul z0\.h, z0\.h, z0\.h
+.*: 65400801 fmul z1\.h, z0\.h, z0\.h
+.*: 65400801 fmul z1\.h, z0\.h, z0\.h
+.*: 6540081f fmul z31\.h, z0\.h, z0\.h
+.*: 6540081f fmul z31\.h, z0\.h, z0\.h
+.*: 65400840 fmul z0\.h, z2\.h, z0\.h
+.*: 65400840 fmul z0\.h, z2\.h, z0\.h
+.*: 65400be0 fmul z0\.h, z31\.h, z0\.h
+.*: 65400be0 fmul z0\.h, z31\.h, z0\.h
+.*: 65430800 fmul z0\.h, z0\.h, z3\.h
+.*: 65430800 fmul z0\.h, z0\.h, z3\.h
+.*: 655f0800 fmul z0\.h, z0\.h, z31\.h
+.*: 655f0800 fmul z0\.h, z0\.h, z31\.h
.*: 65800800 fmul z0\.s, z0\.s, z0\.s
.*: 65800800 fmul z0\.s, z0\.s, z0\.s
.*: 65800801 fmul z1\.s, z0\.s, z0\.s
@@ -9744,6 +10952,22 @@ Disassembly of section .*:
.*: 65c30800 fmul z0\.d, z0\.d, z3\.d
.*: 65df0800 fmul z0\.d, z0\.d, z31\.d
.*: 65df0800 fmul z0\.d, z0\.d, z31\.d
+.*: 65428000 fmul z0\.h, p0/m, z0\.h, z0\.h
+.*: 65428000 fmul z0\.h, p0/m, z0\.h, z0\.h
+.*: 65428001 fmul z1\.h, p0/m, z1\.h, z0\.h
+.*: 65428001 fmul z1\.h, p0/m, z1\.h, z0\.h
+.*: 6542801f fmul z31\.h, p0/m, z31\.h, z0\.h
+.*: 6542801f fmul z31\.h, p0/m, z31\.h, z0\.h
+.*: 65428800 fmul z0\.h, p2/m, z0\.h, z0\.h
+.*: 65428800 fmul z0\.h, p2/m, z0\.h, z0\.h
+.*: 65429c00 fmul z0\.h, p7/m, z0\.h, z0\.h
+.*: 65429c00 fmul z0\.h, p7/m, z0\.h, z0\.h
+.*: 65428003 fmul z3\.h, p0/m, z3\.h, z0\.h
+.*: 65428003 fmul z3\.h, p0/m, z3\.h, z0\.h
+.*: 65428080 fmul z0\.h, p0/m, z0\.h, z4\.h
+.*: 65428080 fmul z0\.h, p0/m, z0\.h, z4\.h
+.*: 654283e0 fmul z0\.h, p0/m, z0\.h, z31\.h
+.*: 654283e0 fmul z0\.h, p0/m, z0\.h, z31\.h
.*: 65828000 fmul z0\.s, p0/m, z0\.s, z0\.s
.*: 65828000 fmul z0\.s, p0/m, z0\.s, z0\.s
.*: 65828001 fmul z1\.s, p0/m, z1\.s, z0\.s
@@ -9776,6 +11000,34 @@ Disassembly of section .*:
.*: 65c28080 fmul z0\.d, p0/m, z0\.d, z4\.d
.*: 65c283e0 fmul z0\.d, p0/m, z0\.d, z31\.d
.*: 65c283e0 fmul z0\.d, p0/m, z0\.d, z31\.d
+.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
+.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
+.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
+.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
+.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
+.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
+.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
+.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
+.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
+.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
+.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
+.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
+.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
+.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
+.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
+.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
+.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
+.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
+.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
+.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
+.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
+.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
+.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
+.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
+.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
+.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
+.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
+.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
@@ -9832,6 +11084,88 @@ Disassembly of section .*:
.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
+.*: 64202000 fmul z0\.h, z0\.h, z0\.h\[0\]
+.*: 64202000 fmul z0\.h, z0\.h, z0\.h\[0\]
+.*: 64202001 fmul z1\.h, z0\.h, z0\.h\[0\]
+.*: 64202001 fmul z1\.h, z0\.h, z0\.h\[0\]
+.*: 6420201f fmul z31\.h, z0\.h, z0\.h\[0\]
+.*: 6420201f fmul z31\.h, z0\.h, z0\.h\[0\]
+.*: 64202040 fmul z0\.h, z2\.h, z0\.h\[0\]
+.*: 64202040 fmul z0\.h, z2\.h, z0\.h\[0\]
+.*: 642023e0 fmul z0\.h, z31\.h, z0\.h\[0\]
+.*: 642023e0 fmul z0\.h, z31\.h, z0\.h\[0\]
+.*: 64232000 fmul z0\.h, z0\.h, z3\.h\[0\]
+.*: 64232000 fmul z0\.h, z0\.h, z3\.h\[0\]
+.*: 64272000 fmul z0\.h, z0\.h, z7\.h\[0\]
+.*: 64272000 fmul z0\.h, z0\.h, z7\.h\[0\]
+.*: 64282000 fmul z0\.h, z0\.h, z0\.h\[1\]
+.*: 64282000 fmul z0\.h, z0\.h, z0\.h\[1\]
+.*: 642c2000 fmul z0\.h, z0\.h, z4\.h\[1\]
+.*: 642c2000 fmul z0\.h, z0\.h, z4\.h\[1\]
+.*: 64632000 fmul z0\.h, z0\.h, z3\.h\[4\]
+.*: 64632000 fmul z0\.h, z0\.h, z3\.h\[4\]
+.*: 64782000 fmul z0\.h, z0\.h, z0\.h\[7\]
+.*: 64782000 fmul z0\.h, z0\.h, z0\.h\[7\]
+.*: 647d2000 fmul z0\.h, z0\.h, z5\.h\[7\]
+.*: 647d2000 fmul z0\.h, z0\.h, z5\.h\[7\]
+.*: 64a02000 fmul z0\.s, z0\.s, z0\.s\[0\]
+.*: 64a02000 fmul z0\.s, z0\.s, z0\.s\[0\]
+.*: 64a02001 fmul z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a02001 fmul z1\.s, z0\.s, z0\.s\[0\]
+.*: 64a0201f fmul z31\.s, z0\.s, z0\.s\[0\]
+.*: 64a0201f fmul z31\.s, z0\.s, z0\.s\[0\]
+.*: 64a02040 fmul z0\.s, z2\.s, z0\.s\[0\]
+.*: 64a02040 fmul z0\.s, z2\.s, z0\.s\[0\]
+.*: 64a023e0 fmul z0\.s, z31\.s, z0\.s\[0\]
+.*: 64a023e0 fmul z0\.s, z31\.s, z0\.s\[0\]
+.*: 64a32000 fmul z0\.s, z0\.s, z3\.s\[0\]
+.*: 64a32000 fmul z0\.s, z0\.s, z3\.s\[0\]
+.*: 64a72000 fmul z0\.s, z0\.s, z7\.s\[0\]
+.*: 64a72000 fmul z0\.s, z0\.s, z7\.s\[0\]
+.*: 64a82000 fmul z0\.s, z0\.s, z0\.s\[1\]
+.*: 64a82000 fmul z0\.s, z0\.s, z0\.s\[1\]
+.*: 64ac2000 fmul z0\.s, z0\.s, z4\.s\[1\]
+.*: 64ac2000 fmul z0\.s, z0\.s, z4\.s\[1\]
+.*: 64b32000 fmul z0\.s, z0\.s, z3\.s\[2\]
+.*: 64b32000 fmul z0\.s, z0\.s, z3\.s\[2\]
+.*: 64b82000 fmul z0\.s, z0\.s, z0\.s\[3\]
+.*: 64b82000 fmul z0\.s, z0\.s, z0\.s\[3\]
+.*: 64bd2000 fmul z0\.s, z0\.s, z5\.s\[3\]
+.*: 64bd2000 fmul z0\.s, z0\.s, z5\.s\[3\]
+.*: 64e02000 fmul z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e02000 fmul z0\.d, z0\.d, z0\.d\[0\]
+.*: 64e02001 fmul z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e02001 fmul z1\.d, z0\.d, z0\.d\[0\]
+.*: 64e0201f fmul z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e0201f fmul z31\.d, z0\.d, z0\.d\[0\]
+.*: 64e02040 fmul z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e02040 fmul z0\.d, z2\.d, z0\.d\[0\]
+.*: 64e023e0 fmul z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e023e0 fmul z0\.d, z31\.d, z0\.d\[0\]
+.*: 64e32000 fmul z0\.d, z0\.d, z3\.d\[0\]
+.*: 64e32000 fmul z0\.d, z0\.d, z3\.d\[0\]
+.*: 64ef2000 fmul z0\.d, z0\.d, z15\.d\[0\]
+.*: 64ef2000 fmul z0\.d, z0\.d, z15\.d\[0\]
+.*: 64f02000 fmul z0\.d, z0\.d, z0\.d\[1\]
+.*: 64f02000 fmul z0\.d, z0\.d, z0\.d\[1\]
+.*: 64fb2000 fmul z0\.d, z0\.d, z11\.d\[1\]
+.*: 64fb2000 fmul z0\.d, z0\.d, z11\.d\[1\]
+.*: 654a8000 fmulx z0\.h, p0/m, z0\.h, z0\.h
+.*: 654a8000 fmulx z0\.h, p0/m, z0\.h, z0\.h
+.*: 654a8001 fmulx z1\.h, p0/m, z1\.h, z0\.h
+.*: 654a8001 fmulx z1\.h, p0/m, z1\.h, z0\.h
+.*: 654a801f fmulx z31\.h, p0/m, z31\.h, z0\.h
+.*: 654a801f fmulx z31\.h, p0/m, z31\.h, z0\.h
+.*: 654a8800 fmulx z0\.h, p2/m, z0\.h, z0\.h
+.*: 654a8800 fmulx z0\.h, p2/m, z0\.h, z0\.h
+.*: 654a9c00 fmulx z0\.h, p7/m, z0\.h, z0\.h
+.*: 654a9c00 fmulx z0\.h, p7/m, z0\.h, z0\.h
+.*: 654a8003 fmulx z3\.h, p0/m, z3\.h, z0\.h
+.*: 654a8003 fmulx z3\.h, p0/m, z3\.h, z0\.h
+.*: 654a8080 fmulx z0\.h, p0/m, z0\.h, z4\.h
+.*: 654a8080 fmulx z0\.h, p0/m, z0\.h, z4\.h
+.*: 654a83e0 fmulx z0\.h, p0/m, z0\.h, z31\.h
+.*: 654a83e0 fmulx z0\.h, p0/m, z0\.h, z31\.h
.*: 658a8000 fmulx z0\.s, p0/m, z0\.s, z0\.s
.*: 658a8000 fmulx z0\.s, p0/m, z0\.s, z0\.s
.*: 658a8001 fmulx z1\.s, p0/m, z1\.s, z0\.s
@@ -9864,6 +11198,20 @@ Disassembly of section .*:
.*: 65ca8080 fmulx z0\.d, p0/m, z0\.d, z4\.d
.*: 65ca83e0 fmulx z0\.d, p0/m, z0\.d, z31\.d
.*: 65ca83e0 fmulx z0\.d, p0/m, z0\.d, z31\.d
+.*: 045da000 fneg z0\.h, p0/m, z0\.h
+.*: 045da000 fneg z0\.h, p0/m, z0\.h
+.*: 045da001 fneg z1\.h, p0/m, z0\.h
+.*: 045da001 fneg z1\.h, p0/m, z0\.h
+.*: 045da01f fneg z31\.h, p0/m, z0\.h
+.*: 045da01f fneg z31\.h, p0/m, z0\.h
+.*: 045da800 fneg z0\.h, p2/m, z0\.h
+.*: 045da800 fneg z0\.h, p2/m, z0\.h
+.*: 045dbc00 fneg z0\.h, p7/m, z0\.h
+.*: 045dbc00 fneg z0\.h, p7/m, z0\.h
+.*: 045da060 fneg z0\.h, p0/m, z3\.h
+.*: 045da060 fneg z0\.h, p0/m, z3\.h
+.*: 045da3e0 fneg z0\.h, p0/m, z31\.h
+.*: 045da3e0 fneg z0\.h, p0/m, z31\.h
.*: 049da000 fneg z0\.s, p0/m, z0\.s
.*: 049da000 fneg z0\.s, p0/m, z0\.s
.*: 049da001 fneg z1\.s, p0/m, z0\.s
@@ -9892,6 +11240,24 @@ Disassembly of section .*:
.*: 04dda060 fneg z0\.d, p0/m, z3\.d
.*: 04dda3e0 fneg z0\.d, p0/m, z31\.d
.*: 04dda3e0 fneg z0\.d, p0/m, z31\.d
+.*: 6560c000 fnmad z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560c000 fnmad z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560c001 fnmad z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560c001 fnmad z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560c01f fnmad z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560c01f fnmad z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560c800 fnmad z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560c800 fnmad z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560dc00 fnmad z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560dc00 fnmad z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560c060 fnmad z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560c060 fnmad z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560c3e0 fnmad z0\.h, p0/m, z31\.h, z0\.h
+.*: 6560c3e0 fnmad z0\.h, p0/m, z31\.h, z0\.h
+.*: 6564c000 fnmad z0\.h, p0/m, z0\.h, z4\.h
+.*: 6564c000 fnmad z0\.h, p0/m, z0\.h, z4\.h
+.*: 657fc000 fnmad z0\.h, p0/m, z0\.h, z31\.h
+.*: 657fc000 fnmad z0\.h, p0/m, z0\.h, z31\.h
.*: 65a0c000 fnmad z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0c000 fnmad z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0c001 fnmad z1\.s, p0/m, z0\.s, z0\.s
@@ -9928,6 +11294,24 @@ Disassembly of section .*:
.*: 65e4c000 fnmad z0\.d, p0/m, z0\.d, z4\.d
.*: 65ffc000 fnmad z0\.d, p0/m, z0\.d, z31\.d
.*: 65ffc000 fnmad z0\.d, p0/m, z0\.d, z31\.d
+.*: 65604000 fnmla z0\.h, p0/m, z0\.h, z0\.h
+.*: 65604000 fnmla z0\.h, p0/m, z0\.h, z0\.h
+.*: 65604001 fnmla z1\.h, p0/m, z0\.h, z0\.h
+.*: 65604001 fnmla z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560401f fnmla z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560401f fnmla z31\.h, p0/m, z0\.h, z0\.h
+.*: 65604800 fnmla z0\.h, p2/m, z0\.h, z0\.h
+.*: 65604800 fnmla z0\.h, p2/m, z0\.h, z0\.h
+.*: 65605c00 fnmla z0\.h, p7/m, z0\.h, z0\.h
+.*: 65605c00 fnmla z0\.h, p7/m, z0\.h, z0\.h
+.*: 65604060 fnmla z0\.h, p0/m, z3\.h, z0\.h
+.*: 65604060 fnmla z0\.h, p0/m, z3\.h, z0\.h
+.*: 656043e0 fnmla z0\.h, p0/m, z31\.h, z0\.h
+.*: 656043e0 fnmla z0\.h, p0/m, z31\.h, z0\.h
+.*: 65644000 fnmla z0\.h, p0/m, z0\.h, z4\.h
+.*: 65644000 fnmla z0\.h, p0/m, z0\.h, z4\.h
+.*: 657f4000 fnmla z0\.h, p0/m, z0\.h, z31\.h
+.*: 657f4000 fnmla z0\.h, p0/m, z0\.h, z31\.h
.*: 65a04000 fnmla z0\.s, p0/m, z0\.s, z0\.s
.*: 65a04000 fnmla z0\.s, p0/m, z0\.s, z0\.s
.*: 65a04001 fnmla z1\.s, p0/m, z0\.s, z0\.s
@@ -9964,6 +11348,24 @@ Disassembly of section .*:
.*: 65e44000 fnmla z0\.d, p0/m, z0\.d, z4\.d
.*: 65ff4000 fnmla z0\.d, p0/m, z0\.d, z31\.d
.*: 65ff4000 fnmla z0\.d, p0/m, z0\.d, z31\.d
+.*: 65606000 fnmls z0\.h, p0/m, z0\.h, z0\.h
+.*: 65606000 fnmls z0\.h, p0/m, z0\.h, z0\.h
+.*: 65606001 fnmls z1\.h, p0/m, z0\.h, z0\.h
+.*: 65606001 fnmls z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560601f fnmls z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560601f fnmls z31\.h, p0/m, z0\.h, z0\.h
+.*: 65606800 fnmls z0\.h, p2/m, z0\.h, z0\.h
+.*: 65606800 fnmls z0\.h, p2/m, z0\.h, z0\.h
+.*: 65607c00 fnmls z0\.h, p7/m, z0\.h, z0\.h
+.*: 65607c00 fnmls z0\.h, p7/m, z0\.h, z0\.h
+.*: 65606060 fnmls z0\.h, p0/m, z3\.h, z0\.h
+.*: 65606060 fnmls z0\.h, p0/m, z3\.h, z0\.h
+.*: 656063e0 fnmls z0\.h, p0/m, z31\.h, z0\.h
+.*: 656063e0 fnmls z0\.h, p0/m, z31\.h, z0\.h
+.*: 65646000 fnmls z0\.h, p0/m, z0\.h, z4\.h
+.*: 65646000 fnmls z0\.h, p0/m, z0\.h, z4\.h
+.*: 657f6000 fnmls z0\.h, p0/m, z0\.h, z31\.h
+.*: 657f6000 fnmls z0\.h, p0/m, z0\.h, z31\.h
.*: 65a06000 fnmls z0\.s, p0/m, z0\.s, z0\.s
.*: 65a06000 fnmls z0\.s, p0/m, z0\.s, z0\.s
.*: 65a06001 fnmls z1\.s, p0/m, z0\.s, z0\.s
@@ -10000,6 +11402,24 @@ Disassembly of section .*:
.*: 65e46000 fnmls z0\.d, p0/m, z0\.d, z4\.d
.*: 65ff6000 fnmls z0\.d, p0/m, z0\.d, z31\.d
.*: 65ff6000 fnmls z0\.d, p0/m, z0\.d, z31\.d
+.*: 6560e000 fnmsb z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560e000 fnmsb z0\.h, p0/m, z0\.h, z0\.h
+.*: 6560e001 fnmsb z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560e001 fnmsb z1\.h, p0/m, z0\.h, z0\.h
+.*: 6560e01f fnmsb z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560e01f fnmsb z31\.h, p0/m, z0\.h, z0\.h
+.*: 6560e800 fnmsb z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560e800 fnmsb z0\.h, p2/m, z0\.h, z0\.h
+.*: 6560fc00 fnmsb z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560fc00 fnmsb z0\.h, p7/m, z0\.h, z0\.h
+.*: 6560e060 fnmsb z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560e060 fnmsb z0\.h, p0/m, z3\.h, z0\.h
+.*: 6560e3e0 fnmsb z0\.h, p0/m, z31\.h, z0\.h
+.*: 6560e3e0 fnmsb z0\.h, p0/m, z31\.h, z0\.h
+.*: 6564e000 fnmsb z0\.h, p0/m, z0\.h, z4\.h
+.*: 6564e000 fnmsb z0\.h, p0/m, z0\.h, z4\.h
+.*: 657fe000 fnmsb z0\.h, p0/m, z0\.h, z31\.h
+.*: 657fe000 fnmsb z0\.h, p0/m, z0\.h, z31\.h
.*: 65a0e000 fnmsb z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0e000 fnmsb z0\.s, p0/m, z0\.s, z0\.s
.*: 65a0e001 fnmsb z1\.s, p0/m, z0\.s, z0\.s
@@ -10036,6 +11456,16 @@ Disassembly of section .*:
.*: 65e4e000 fnmsb z0\.d, p0/m, z0\.d, z4\.d
.*: 65ffe000 fnmsb z0\.d, p0/m, z0\.d, z31\.d
.*: 65ffe000 fnmsb z0\.d, p0/m, z0\.d, z31\.d
+.*: 654e3000 frecpe z0\.h, z0\.h
+.*: 654e3000 frecpe z0\.h, z0\.h
+.*: 654e3001 frecpe z1\.h, z0\.h
+.*: 654e3001 frecpe z1\.h, z0\.h
+.*: 654e301f frecpe z31\.h, z0\.h
+.*: 654e301f frecpe z31\.h, z0\.h
+.*: 654e3040 frecpe z0\.h, z2\.h
+.*: 654e3040 frecpe z0\.h, z2\.h
+.*: 654e33e0 frecpe z0\.h, z31\.h
+.*: 654e33e0 frecpe z0\.h, z31\.h
.*: 658e3000 frecpe z0\.s, z0\.s
.*: 658e3000 frecpe z0\.s, z0\.s
.*: 658e3001 frecpe z1\.s, z0\.s
@@ -10056,6 +11486,20 @@ Disassembly of section .*:
.*: 65ce3040 frecpe z0\.d, z2\.d
.*: 65ce33e0 frecpe z0\.d, z31\.d
.*: 65ce33e0 frecpe z0\.d, z31\.d
+.*: 65401800 frecps z0\.h, z0\.h, z0\.h
+.*: 65401800 frecps z0\.h, z0\.h, z0\.h
+.*: 65401801 frecps z1\.h, z0\.h, z0\.h
+.*: 65401801 frecps z1\.h, z0\.h, z0\.h
+.*: 6540181f frecps z31\.h, z0\.h, z0\.h
+.*: 6540181f frecps z31\.h, z0\.h, z0\.h
+.*: 65401840 frecps z0\.h, z2\.h, z0\.h
+.*: 65401840 frecps z0\.h, z2\.h, z0\.h
+.*: 65401be0 frecps z0\.h, z31\.h, z0\.h
+.*: 65401be0 frecps z0\.h, z31\.h, z0\.h
+.*: 65431800 frecps z0\.h, z0\.h, z3\.h
+.*: 65431800 frecps z0\.h, z0\.h, z3\.h
+.*: 655f1800 frecps z0\.h, z0\.h, z31\.h
+.*: 655f1800 frecps z0\.h, z0\.h, z31\.h
.*: 65801800 frecps z0\.s, z0\.s, z0\.s
.*: 65801800 frecps z0\.s, z0\.s, z0\.s
.*: 65801801 frecps z1\.s, z0\.s, z0\.s
@@ -10084,6 +11528,20 @@ Disassembly of section .*:
.*: 65c31800 frecps z0\.d, z0\.d, z3\.d
.*: 65df1800 frecps z0\.d, z0\.d, z31\.d
.*: 65df1800 frecps z0\.d, z0\.d, z31\.d
+.*: 654ca000 frecpx z0\.h, p0/m, z0\.h
+.*: 654ca000 frecpx z0\.h, p0/m, z0\.h
+.*: 654ca001 frecpx z1\.h, p0/m, z0\.h
+.*: 654ca001 frecpx z1\.h, p0/m, z0\.h
+.*: 654ca01f frecpx z31\.h, p0/m, z0\.h
+.*: 654ca01f frecpx z31\.h, p0/m, z0\.h
+.*: 654ca800 frecpx z0\.h, p2/m, z0\.h
+.*: 654ca800 frecpx z0\.h, p2/m, z0\.h
+.*: 654cbc00 frecpx z0\.h, p7/m, z0\.h
+.*: 654cbc00 frecpx z0\.h, p7/m, z0\.h
+.*: 654ca060 frecpx z0\.h, p0/m, z3\.h
+.*: 654ca060 frecpx z0\.h, p0/m, z3\.h
+.*: 654ca3e0 frecpx z0\.h, p0/m, z31\.h
+.*: 654ca3e0 frecpx z0\.h, p0/m, z31\.h
.*: 658ca000 frecpx z0\.s, p0/m, z0\.s
.*: 658ca000 frecpx z0\.s, p0/m, z0\.s
.*: 658ca001 frecpx z1\.s, p0/m, z0\.s
@@ -10112,6 +11570,20 @@ Disassembly of section .*:
.*: 65cca060 frecpx z0\.d, p0/m, z3\.d
.*: 65cca3e0 frecpx z0\.d, p0/m, z31\.d
.*: 65cca3e0 frecpx z0\.d, p0/m, z31\.d
+.*: 6544a000 frinta z0\.h, p0/m, z0\.h
+.*: 6544a000 frinta z0\.h, p0/m, z0\.h
+.*: 6544a001 frinta z1\.h, p0/m, z0\.h
+.*: 6544a001 frinta z1\.h, p0/m, z0\.h
+.*: 6544a01f frinta z31\.h, p0/m, z0\.h
+.*: 6544a01f frinta z31\.h, p0/m, z0\.h
+.*: 6544a800 frinta z0\.h, p2/m, z0\.h
+.*: 6544a800 frinta z0\.h, p2/m, z0\.h
+.*: 6544bc00 frinta z0\.h, p7/m, z0\.h
+.*: 6544bc00 frinta z0\.h, p7/m, z0\.h
+.*: 6544a060 frinta z0\.h, p0/m, z3\.h
+.*: 6544a060 frinta z0\.h, p0/m, z3\.h
+.*: 6544a3e0 frinta z0\.h, p0/m, z31\.h
+.*: 6544a3e0 frinta z0\.h, p0/m, z31\.h
.*: 6584a000 frinta z0\.s, p0/m, z0\.s
.*: 6584a000 frinta z0\.s, p0/m, z0\.s
.*: 6584a001 frinta z1\.s, p0/m, z0\.s
@@ -10140,6 +11612,20 @@ Disassembly of section .*:
.*: 65c4a060 frinta z0\.d, p0/m, z3\.d
.*: 65c4a3e0 frinta z0\.d, p0/m, z31\.d
.*: 65c4a3e0 frinta z0\.d, p0/m, z31\.d
+.*: 6547a000 frinti z0\.h, p0/m, z0\.h
+.*: 6547a000 frinti z0\.h, p0/m, z0\.h
+.*: 6547a001 frinti z1\.h, p0/m, z0\.h
+.*: 6547a001 frinti z1\.h, p0/m, z0\.h
+.*: 6547a01f frinti z31\.h, p0/m, z0\.h
+.*: 6547a01f frinti z31\.h, p0/m, z0\.h
+.*: 6547a800 frinti z0\.h, p2/m, z0\.h
+.*: 6547a800 frinti z0\.h, p2/m, z0\.h
+.*: 6547bc00 frinti z0\.h, p7/m, z0\.h
+.*: 6547bc00 frinti z0\.h, p7/m, z0\.h
+.*: 6547a060 frinti z0\.h, p0/m, z3\.h
+.*: 6547a060 frinti z0\.h, p0/m, z3\.h
+.*: 6547a3e0 frinti z0\.h, p0/m, z31\.h
+.*: 6547a3e0 frinti z0\.h, p0/m, z31\.h
.*: 6587a000 frinti z0\.s, p0/m, z0\.s
.*: 6587a000 frinti z0\.s, p0/m, z0\.s
.*: 6587a001 frinti z1\.s, p0/m, z0\.s
@@ -10168,6 +11654,20 @@ Disassembly of section .*:
.*: 65c7a060 frinti z0\.d, p0/m, z3\.d
.*: 65c7a3e0 frinti z0\.d, p0/m, z31\.d
.*: 65c7a3e0 frinti z0\.d, p0/m, z31\.d
+.*: 6542a000 frintm z0\.h, p0/m, z0\.h
+.*: 6542a000 frintm z0\.h, p0/m, z0\.h
+.*: 6542a001 frintm z1\.h, p0/m, z0\.h
+.*: 6542a001 frintm z1\.h, p0/m, z0\.h
+.*: 6542a01f frintm z31\.h, p0/m, z0\.h
+.*: 6542a01f frintm z31\.h, p0/m, z0\.h
+.*: 6542a800 frintm z0\.h, p2/m, z0\.h
+.*: 6542a800 frintm z0\.h, p2/m, z0\.h
+.*: 6542bc00 frintm z0\.h, p7/m, z0\.h
+.*: 6542bc00 frintm z0\.h, p7/m, z0\.h
+.*: 6542a060 frintm z0\.h, p0/m, z3\.h
+.*: 6542a060 frintm z0\.h, p0/m, z3\.h
+.*: 6542a3e0 frintm z0\.h, p0/m, z31\.h
+.*: 6542a3e0 frintm z0\.h, p0/m, z31\.h
.*: 6582a000 frintm z0\.s, p0/m, z0\.s
.*: 6582a000 frintm z0\.s, p0/m, z0\.s
.*: 6582a001 frintm z1\.s, p0/m, z0\.s
@@ -10196,6 +11696,20 @@ Disassembly of section .*:
.*: 65c2a060 frintm z0\.d, p0/m, z3\.d
.*: 65c2a3e0 frintm z0\.d, p0/m, z31\.d
.*: 65c2a3e0 frintm z0\.d, p0/m, z31\.d
+.*: 6540a000 frintn z0\.h, p0/m, z0\.h
+.*: 6540a000 frintn z0\.h, p0/m, z0\.h
+.*: 6540a001 frintn z1\.h, p0/m, z0\.h
+.*: 6540a001 frintn z1\.h, p0/m, z0\.h
+.*: 6540a01f frintn z31\.h, p0/m, z0\.h
+.*: 6540a01f frintn z31\.h, p0/m, z0\.h
+.*: 6540a800 frintn z0\.h, p2/m, z0\.h
+.*: 6540a800 frintn z0\.h, p2/m, z0\.h
+.*: 6540bc00 frintn z0\.h, p7/m, z0\.h
+.*: 6540bc00 frintn z0\.h, p7/m, z0\.h
+.*: 6540a060 frintn z0\.h, p0/m, z3\.h
+.*: 6540a060 frintn z0\.h, p0/m, z3\.h
+.*: 6540a3e0 frintn z0\.h, p0/m, z31\.h
+.*: 6540a3e0 frintn z0\.h, p0/m, z31\.h
.*: 6580a000 frintn z0\.s, p0/m, z0\.s
.*: 6580a000 frintn z0\.s, p0/m, z0\.s
.*: 6580a001 frintn z1\.s, p0/m, z0\.s
@@ -10224,6 +11738,20 @@ Disassembly of section .*:
.*: 65c0a060 frintn z0\.d, p0/m, z3\.d
.*: 65c0a3e0 frintn z0\.d, p0/m, z31\.d
.*: 65c0a3e0 frintn z0\.d, p0/m, z31\.d
+.*: 6541a000 frintp z0\.h, p0/m, z0\.h
+.*: 6541a000 frintp z0\.h, p0/m, z0\.h
+.*: 6541a001 frintp z1\.h, p0/m, z0\.h
+.*: 6541a001 frintp z1\.h, p0/m, z0\.h
+.*: 6541a01f frintp z31\.h, p0/m, z0\.h
+.*: 6541a01f frintp z31\.h, p0/m, z0\.h
+.*: 6541a800 frintp z0\.h, p2/m, z0\.h
+.*: 6541a800 frintp z0\.h, p2/m, z0\.h
+.*: 6541bc00 frintp z0\.h, p7/m, z0\.h
+.*: 6541bc00 frintp z0\.h, p7/m, z0\.h
+.*: 6541a060 frintp z0\.h, p0/m, z3\.h
+.*: 6541a060 frintp z0\.h, p0/m, z3\.h
+.*: 6541a3e0 frintp z0\.h, p0/m, z31\.h
+.*: 6541a3e0 frintp z0\.h, p0/m, z31\.h
.*: 6581a000 frintp z0\.s, p0/m, z0\.s
.*: 6581a000 frintp z0\.s, p0/m, z0\.s
.*: 6581a001 frintp z1\.s, p0/m, z0\.s
@@ -10252,6 +11780,20 @@ Disassembly of section .*:
.*: 65c1a060 frintp z0\.d, p0/m, z3\.d
.*: 65c1a3e0 frintp z0\.d, p0/m, z31\.d
.*: 65c1a3e0 frintp z0\.d, p0/m, z31\.d
+.*: 6546a000 frintx z0\.h, p0/m, z0\.h
+.*: 6546a000 frintx z0\.h, p0/m, z0\.h
+.*: 6546a001 frintx z1\.h, p0/m, z0\.h
+.*: 6546a001 frintx z1\.h, p0/m, z0\.h
+.*: 6546a01f frintx z31\.h, p0/m, z0\.h
+.*: 6546a01f frintx z31\.h, p0/m, z0\.h
+.*: 6546a800 frintx z0\.h, p2/m, z0\.h
+.*: 6546a800 frintx z0\.h, p2/m, z0\.h
+.*: 6546bc00 frintx z0\.h, p7/m, z0\.h
+.*: 6546bc00 frintx z0\.h, p7/m, z0\.h
+.*: 6546a060 frintx z0\.h, p0/m, z3\.h
+.*: 6546a060 frintx z0\.h, p0/m, z3\.h
+.*: 6546a3e0 frintx z0\.h, p0/m, z31\.h
+.*: 6546a3e0 frintx z0\.h, p0/m, z31\.h
.*: 6586a000 frintx z0\.s, p0/m, z0\.s
.*: 6586a000 frintx z0\.s, p0/m, z0\.s
.*: 6586a001 frintx z1\.s, p0/m, z0\.s
@@ -10280,6 +11822,20 @@ Disassembly of section .*:
.*: 65c6a060 frintx z0\.d, p0/m, z3\.d
.*: 65c6a3e0 frintx z0\.d, p0/m, z31\.d
.*: 65c6a3e0 frintx z0\.d, p0/m, z31\.d
+.*: 6543a000 frintz z0\.h, p0/m, z0\.h
+.*: 6543a000 frintz z0\.h, p0/m, z0\.h
+.*: 6543a001 frintz z1\.h, p0/m, z0\.h
+.*: 6543a001 frintz z1\.h, p0/m, z0\.h
+.*: 6543a01f frintz z31\.h, p0/m, z0\.h
+.*: 6543a01f frintz z31\.h, p0/m, z0\.h
+.*: 6543a800 frintz z0\.h, p2/m, z0\.h
+.*: 6543a800 frintz z0\.h, p2/m, z0\.h
+.*: 6543bc00 frintz z0\.h, p7/m, z0\.h
+.*: 6543bc00 frintz z0\.h, p7/m, z0\.h
+.*: 6543a060 frintz z0\.h, p0/m, z3\.h
+.*: 6543a060 frintz z0\.h, p0/m, z3\.h
+.*: 6543a3e0 frintz z0\.h, p0/m, z31\.h
+.*: 6543a3e0 frintz z0\.h, p0/m, z31\.h
.*: 6583a000 frintz z0\.s, p0/m, z0\.s
.*: 6583a000 frintz z0\.s, p0/m, z0\.s
.*: 6583a001 frintz z1\.s, p0/m, z0\.s
@@ -10308,6 +11864,16 @@ Disassembly of section .*:
.*: 65c3a060 frintz z0\.d, p0/m, z3\.d
.*: 65c3a3e0 frintz z0\.d, p0/m, z31\.d
.*: 65c3a3e0 frintz z0\.d, p0/m, z31\.d
+.*: 654f3000 frsqrte z0\.h, z0\.h
+.*: 654f3000 frsqrte z0\.h, z0\.h
+.*: 654f3001 frsqrte z1\.h, z0\.h
+.*: 654f3001 frsqrte z1\.h, z0\.h
+.*: 654f301f frsqrte z31\.h, z0\.h
+.*: 654f301f frsqrte z31\.h, z0\.h
+.*: 654f3040 frsqrte z0\.h, z2\.h
+.*: 654f3040 frsqrte z0\.h, z2\.h
+.*: 654f33e0 frsqrte z0\.h, z31\.h
+.*: 654f33e0 frsqrte z0\.h, z31\.h
.*: 658f3000 frsqrte z0\.s, z0\.s
.*: 658f3000 frsqrte z0\.s, z0\.s
.*: 658f3001 frsqrte z1\.s, z0\.s
@@ -10328,6 +11894,20 @@ Disassembly of section .*:
.*: 65cf3040 frsqrte z0\.d, z2\.d
.*: 65cf33e0 frsqrte z0\.d, z31\.d
.*: 65cf33e0 frsqrte z0\.d, z31\.d
+.*: 65401c00 frsqrts z0\.h, z0\.h, z0\.h
+.*: 65401c00 frsqrts z0\.h, z0\.h, z0\.h
+.*: 65401c01 frsqrts z1\.h, z0\.h, z0\.h
+.*: 65401c01 frsqrts z1\.h, z0\.h, z0\.h
+.*: 65401c1f frsqrts z31\.h, z0\.h, z0\.h
+.*: 65401c1f frsqrts z31\.h, z0\.h, z0\.h
+.*: 65401c40 frsqrts z0\.h, z2\.h, z0\.h
+.*: 65401c40 frsqrts z0\.h, z2\.h, z0\.h
+.*: 65401fe0 frsqrts z0\.h, z31\.h, z0\.h
+.*: 65401fe0 frsqrts z0\.h, z31\.h, z0\.h
+.*: 65431c00 frsqrts z0\.h, z0\.h, z3\.h
+.*: 65431c00 frsqrts z0\.h, z0\.h, z3\.h
+.*: 655f1c00 frsqrts z0\.h, z0\.h, z31\.h
+.*: 655f1c00 frsqrts z0\.h, z0\.h, z31\.h
.*: 65801c00 frsqrts z0\.s, z0\.s, z0\.s
.*: 65801c00 frsqrts z0\.s, z0\.s, z0\.s
.*: 65801c01 frsqrts z1\.s, z0\.s, z0\.s
@@ -10356,6 +11936,22 @@ Disassembly of section .*:
.*: 65c31c00 frsqrts z0\.d, z0\.d, z3\.d
.*: 65df1c00 frsqrts z0\.d, z0\.d, z31\.d
.*: 65df1c00 frsqrts z0\.d, z0\.d, z31\.d
+.*: 65498000 fscale z0\.h, p0/m, z0\.h, z0\.h
+.*: 65498000 fscale z0\.h, p0/m, z0\.h, z0\.h
+.*: 65498001 fscale z1\.h, p0/m, z1\.h, z0\.h
+.*: 65498001 fscale z1\.h, p0/m, z1\.h, z0\.h
+.*: 6549801f fscale z31\.h, p0/m, z31\.h, z0\.h
+.*: 6549801f fscale z31\.h, p0/m, z31\.h, z0\.h
+.*: 65498800 fscale z0\.h, p2/m, z0\.h, z0\.h
+.*: 65498800 fscale z0\.h, p2/m, z0\.h, z0\.h
+.*: 65499c00 fscale z0\.h, p7/m, z0\.h, z0\.h
+.*: 65499c00 fscale z0\.h, p7/m, z0\.h, z0\.h
+.*: 65498003 fscale z3\.h, p0/m, z3\.h, z0\.h
+.*: 65498003 fscale z3\.h, p0/m, z3\.h, z0\.h
+.*: 65498080 fscale z0\.h, p0/m, z0\.h, z4\.h
+.*: 65498080 fscale z0\.h, p0/m, z0\.h, z4\.h
+.*: 654983e0 fscale z0\.h, p0/m, z0\.h, z31\.h
+.*: 654983e0 fscale z0\.h, p0/m, z0\.h, z31\.h
.*: 65898000 fscale z0\.s, p0/m, z0\.s, z0\.s
.*: 65898000 fscale z0\.s, p0/m, z0\.s, z0\.s
.*: 65898001 fscale z1\.s, p0/m, z1\.s, z0\.s
@@ -10388,6 +11984,20 @@ Disassembly of section .*:
.*: 65c98080 fscale z0\.d, p0/m, z0\.d, z4\.d
.*: 65c983e0 fscale z0\.d, p0/m, z0\.d, z31\.d
.*: 65c983e0 fscale z0\.d, p0/m, z0\.d, z31\.d
+.*: 654da000 fsqrt z0\.h, p0/m, z0\.h
+.*: 654da000 fsqrt z0\.h, p0/m, z0\.h
+.*: 654da001 fsqrt z1\.h, p0/m, z0\.h
+.*: 654da001 fsqrt z1\.h, p0/m, z0\.h
+.*: 654da01f fsqrt z31\.h, p0/m, z0\.h
+.*: 654da01f fsqrt z31\.h, p0/m, z0\.h
+.*: 654da800 fsqrt z0\.h, p2/m, z0\.h
+.*: 654da800 fsqrt z0\.h, p2/m, z0\.h
+.*: 654dbc00 fsqrt z0\.h, p7/m, z0\.h
+.*: 654dbc00 fsqrt z0\.h, p7/m, z0\.h
+.*: 654da060 fsqrt z0\.h, p0/m, z3\.h
+.*: 654da060 fsqrt z0\.h, p0/m, z3\.h
+.*: 654da3e0 fsqrt z0\.h, p0/m, z31\.h
+.*: 654da3e0 fsqrt z0\.h, p0/m, z31\.h
.*: 658da000 fsqrt z0\.s, p0/m, z0\.s
.*: 658da000 fsqrt z0\.s, p0/m, z0\.s
.*: 658da001 fsqrt z1\.s, p0/m, z0\.s
@@ -10416,6 +12026,20 @@ Disassembly of section .*:
.*: 65cda060 fsqrt z0\.d, p0/m, z3\.d
.*: 65cda3e0 fsqrt z0\.d, p0/m, z31\.d
.*: 65cda3e0 fsqrt z0\.d, p0/m, z31\.d
+.*: 65400400 fsub z0\.h, z0\.h, z0\.h
+.*: 65400400 fsub z0\.h, z0\.h, z0\.h
+.*: 65400401 fsub z1\.h, z0\.h, z0\.h
+.*: 65400401 fsub z1\.h, z0\.h, z0\.h
+.*: 6540041f fsub z31\.h, z0\.h, z0\.h
+.*: 6540041f fsub z31\.h, z0\.h, z0\.h
+.*: 65400440 fsub z0\.h, z2\.h, z0\.h
+.*: 65400440 fsub z0\.h, z2\.h, z0\.h
+.*: 654007e0 fsub z0\.h, z31\.h, z0\.h
+.*: 654007e0 fsub z0\.h, z31\.h, z0\.h
+.*: 65430400 fsub z0\.h, z0\.h, z3\.h
+.*: 65430400 fsub z0\.h, z0\.h, z3\.h
+.*: 655f0400 fsub z0\.h, z0\.h, z31\.h
+.*: 655f0400 fsub z0\.h, z0\.h, z31\.h
.*: 65800400 fsub z0\.s, z0\.s, z0\.s
.*: 65800400 fsub z0\.s, z0\.s, z0\.s
.*: 65800401 fsub z1\.s, z0\.s, z0\.s
@@ -10444,6 +12068,22 @@ Disassembly of section .*:
.*: 65c30400 fsub z0\.d, z0\.d, z3\.d
.*: 65df0400 fsub z0\.d, z0\.d, z31\.d
.*: 65df0400 fsub z0\.d, z0\.d, z31\.d
+.*: 65418000 fsub z0\.h, p0/m, z0\.h, z0\.h
+.*: 65418000 fsub z0\.h, p0/m, z0\.h, z0\.h
+.*: 65418001 fsub z1\.h, p0/m, z1\.h, z0\.h
+.*: 65418001 fsub z1\.h, p0/m, z1\.h, z0\.h
+.*: 6541801f fsub z31\.h, p0/m, z31\.h, z0\.h
+.*: 6541801f fsub z31\.h, p0/m, z31\.h, z0\.h
+.*: 65418800 fsub z0\.h, p2/m, z0\.h, z0\.h
+.*: 65418800 fsub z0\.h, p2/m, z0\.h, z0\.h
+.*: 65419c00 fsub z0\.h, p7/m, z0\.h, z0\.h
+.*: 65419c00 fsub z0\.h, p7/m, z0\.h, z0\.h
+.*: 65418003 fsub z3\.h, p0/m, z3\.h, z0\.h
+.*: 65418003 fsub z3\.h, p0/m, z3\.h, z0\.h
+.*: 65418080 fsub z0\.h, p0/m, z0\.h, z4\.h
+.*: 65418080 fsub z0\.h, p0/m, z0\.h, z4\.h
+.*: 654183e0 fsub z0\.h, p0/m, z0\.h, z31\.h
+.*: 654183e0 fsub z0\.h, p0/m, z0\.h, z31\.h
.*: 65818000 fsub z0\.s, p0/m, z0\.s, z0\.s
.*: 65818000 fsub z0\.s, p0/m, z0\.s, z0\.s
.*: 65818001 fsub z1\.s, p0/m, z1\.s, z0\.s
@@ -10476,6 +12116,34 @@ Disassembly of section .*:
.*: 65c18080 fsub z0\.d, p0/m, z0\.d, z4\.d
.*: 65c183e0 fsub z0\.d, p0/m, z0\.d, z31\.d
.*: 65c183e0 fsub z0\.d, p0/m, z0\.d, z31\.d
+.*: 65598000 fsub z0\.h, p0/m, z0\.h, #0\.5
+.*: 65598000 fsub z0\.h, p0/m, z0\.h, #0\.5
+.*: 65598000 fsub z0\.h, p0/m, z0\.h, #0\.5
+.*: 65598000 fsub z0\.h, p0/m, z0\.h, #0\.5
+.*: 65598001 fsub z1\.h, p0/m, z1\.h, #0\.5
+.*: 65598001 fsub z1\.h, p0/m, z1\.h, #0\.5
+.*: 65598001 fsub z1\.h, p0/m, z1\.h, #0\.5
+.*: 65598001 fsub z1\.h, p0/m, z1\.h, #0\.5
+.*: 6559801f fsub z31\.h, p0/m, z31\.h, #0\.5
+.*: 6559801f fsub z31\.h, p0/m, z31\.h, #0\.5
+.*: 6559801f fsub z31\.h, p0/m, z31\.h, #0\.5
+.*: 6559801f fsub z31\.h, p0/m, z31\.h, #0\.5
+.*: 65598800 fsub z0\.h, p2/m, z0\.h, #0\.5
+.*: 65598800 fsub z0\.h, p2/m, z0\.h, #0\.5
+.*: 65598800 fsub z0\.h, p2/m, z0\.h, #0\.5
+.*: 65598800 fsub z0\.h, p2/m, z0\.h, #0\.5
+.*: 65599c00 fsub z0\.h, p7/m, z0\.h, #0\.5
+.*: 65599c00 fsub z0\.h, p7/m, z0\.h, #0\.5
+.*: 65599c00 fsub z0\.h, p7/m, z0\.h, #0\.5
+.*: 65599c00 fsub z0\.h, p7/m, z0\.h, #0\.5
+.*: 65598003 fsub z3\.h, p0/m, z3\.h, #0\.5
+.*: 65598003 fsub z3\.h, p0/m, z3\.h, #0\.5
+.*: 65598003 fsub z3\.h, p0/m, z3\.h, #0\.5
+.*: 65598003 fsub z3\.h, p0/m, z3\.h, #0\.5
+.*: 65598020 fsub z0\.h, p0/m, z0\.h, #1\.0
+.*: 65598020 fsub z0\.h, p0/m, z0\.h, #1\.0
+.*: 65598020 fsub z0\.h, p0/m, z0\.h, #1\.0
+.*: 65598020 fsub z0\.h, p0/m, z0\.h, #1\.0
.*: 65998000 fsub z0\.s, p0/m, z0\.s, #0\.5
.*: 65998000 fsub z0\.s, p0/m, z0\.s, #0\.5
.*: 65998000 fsub z0\.s, p0/m, z0\.s, #0\.5
@@ -10532,6 +12200,22 @@ Disassembly of section .*:
.*: 65d98020 fsub z0\.d, p0/m, z0\.d, #1\.0
.*: 65d98020 fsub z0\.d, p0/m, z0\.d, #1\.0
.*: 65d98020 fsub z0\.d, p0/m, z0\.d, #1\.0
+.*: 65438000 fsubr z0\.h, p0/m, z0\.h, z0\.h
+.*: 65438000 fsubr z0\.h, p0/m, z0\.h, z0\.h
+.*: 65438001 fsubr z1\.h, p0/m, z1\.h, z0\.h
+.*: 65438001 fsubr z1\.h, p0/m, z1\.h, z0\.h
+.*: 6543801f fsubr z31\.h, p0/m, z31\.h, z0\.h
+.*: 6543801f fsubr z31\.h, p0/m, z31\.h, z0\.h
+.*: 65438800 fsubr z0\.h, p2/m, z0\.h, z0\.h
+.*: 65438800 fsubr z0\.h, p2/m, z0\.h, z0\.h
+.*: 65439c00 fsubr z0\.h, p7/m, z0\.h, z0\.h
+.*: 65439c00 fsubr z0\.h, p7/m, z0\.h, z0\.h
+.*: 65438003 fsubr z3\.h, p0/m, z3\.h, z0\.h
+.*: 65438003 fsubr z3\.h, p0/m, z3\.h, z0\.h
+.*: 65438080 fsubr z0\.h, p0/m, z0\.h, z4\.h
+.*: 65438080 fsubr z0\.h, p0/m, z0\.h, z4\.h
+.*: 654383e0 fsubr z0\.h, p0/m, z0\.h, z31\.h
+.*: 654383e0 fsubr z0\.h, p0/m, z0\.h, z31\.h
.*: 65838000 fsubr z0\.s, p0/m, z0\.s, z0\.s
.*: 65838000 fsubr z0\.s, p0/m, z0\.s, z0\.s
.*: 65838001 fsubr z1\.s, p0/m, z1\.s, z0\.s
@@ -10564,6 +12248,34 @@ Disassembly of section .*:
.*: 65c38080 fsubr z0\.d, p0/m, z0\.d, z4\.d
.*: 65c383e0 fsubr z0\.d, p0/m, z0\.d, z31\.d
.*: 65c383e0 fsubr z0\.d, p0/m, z0\.d, z31\.d
+.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
+.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
+.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
+.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
+.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
+.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
+.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
+.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
+.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
+.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
+.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
+.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
+.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
+.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
+.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
+.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
+.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
+.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
+.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
+.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
+.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
+.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
+.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
+.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
+.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
+.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
+.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
+.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
@@ -10620,6 +12332,26 @@ Disassembly of section .*:
.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
+.*: 65508000 ftmad z0\.h, z0\.h, z0\.h, #0
+.*: 65508000 ftmad z0\.h, z0\.h, z0\.h, #0
+.*: 65508001 ftmad z1\.h, z1\.h, z0\.h, #0
+.*: 65508001 ftmad z1\.h, z1\.h, z0\.h, #0
+.*: 6550801f ftmad z31\.h, z31\.h, z0\.h, #0
+.*: 6550801f ftmad z31\.h, z31\.h, z0\.h, #0
+.*: 65508002 ftmad z2\.h, z2\.h, z0\.h, #0
+.*: 65508002 ftmad z2\.h, z2\.h, z0\.h, #0
+.*: 65508060 ftmad z0\.h, z0\.h, z3\.h, #0
+.*: 65508060 ftmad z0\.h, z0\.h, z3\.h, #0
+.*: 655083e0 ftmad z0\.h, z0\.h, z31\.h, #0
+.*: 655083e0 ftmad z0\.h, z0\.h, z31\.h, #0
+.*: 65538000 ftmad z0\.h, z0\.h, z0\.h, #3
+.*: 65538000 ftmad z0\.h, z0\.h, z0\.h, #3
+.*: 65548000 ftmad z0\.h, z0\.h, z0\.h, #4
+.*: 65548000 ftmad z0\.h, z0\.h, z0\.h, #4
+.*: 65558000 ftmad z0\.h, z0\.h, z0\.h, #5
+.*: 65558000 ftmad z0\.h, z0\.h, z0\.h, #5
+.*: 65578000 ftmad z0\.h, z0\.h, z0\.h, #7
+.*: 65578000 ftmad z0\.h, z0\.h, z0\.h, #7
.*: 65908000 ftmad z0\.s, z0\.s, z0\.s, #0
.*: 65908000 ftmad z0\.s, z0\.s, z0\.s, #0
.*: 65908001 ftmad z1\.s, z1\.s, z0\.s, #0
@@ -10660,6 +12392,20 @@ Disassembly of section .*:
.*: 65d58000 ftmad z0\.d, z0\.d, z0\.d, #5
.*: 65d78000 ftmad z0\.d, z0\.d, z0\.d, #7
.*: 65d78000 ftmad z0\.d, z0\.d, z0\.d, #7
+.*: 65400c00 ftsmul z0\.h, z0\.h, z0\.h
+.*: 65400c00 ftsmul z0\.h, z0\.h, z0\.h
+.*: 65400c01 ftsmul z1\.h, z0\.h, z0\.h
+.*: 65400c01 ftsmul z1\.h, z0\.h, z0\.h
+.*: 65400c1f ftsmul z31\.h, z0\.h, z0\.h
+.*: 65400c1f ftsmul z31\.h, z0\.h, z0\.h
+.*: 65400c40 ftsmul z0\.h, z2\.h, z0\.h
+.*: 65400c40 ftsmul z0\.h, z2\.h, z0\.h
+.*: 65400fe0 ftsmul z0\.h, z31\.h, z0\.h
+.*: 65400fe0 ftsmul z0\.h, z31\.h, z0\.h
+.*: 65430c00 ftsmul z0\.h, z0\.h, z3\.h
+.*: 65430c00 ftsmul z0\.h, z0\.h, z3\.h
+.*: 655f0c00 ftsmul z0\.h, z0\.h, z31\.h
+.*: 655f0c00 ftsmul z0\.h, z0\.h, z31\.h
.*: 65800c00 ftsmul z0\.s, z0\.s, z0\.s
.*: 65800c00 ftsmul z0\.s, z0\.s, z0\.s
.*: 65800c01 ftsmul z1\.s, z0\.s, z0\.s
@@ -10688,6 +12434,20 @@ Disassembly of section .*:
.*: 65c30c00 ftsmul z0\.d, z0\.d, z3\.d
.*: 65df0c00 ftsmul z0\.d, z0\.d, z31\.d
.*: 65df0c00 ftsmul z0\.d, z0\.d, z31\.d
+.*: 0460b000 ftssel z0\.h, z0\.h, z0\.h
+.*: 0460b000 ftssel z0\.h, z0\.h, z0\.h
+.*: 0460b001 ftssel z1\.h, z0\.h, z0\.h
+.*: 0460b001 ftssel z1\.h, z0\.h, z0\.h
+.*: 0460b01f ftssel z31\.h, z0\.h, z0\.h
+.*: 0460b01f ftssel z31\.h, z0\.h, z0\.h
+.*: 0460b040 ftssel z0\.h, z2\.h, z0\.h
+.*: 0460b040 ftssel z0\.h, z2\.h, z0\.h
+.*: 0460b3e0 ftssel z0\.h, z31\.h, z0\.h
+.*: 0460b3e0 ftssel z0\.h, z31\.h, z0\.h
+.*: 0463b000 ftssel z0\.h, z0\.h, z3\.h
+.*: 0463b000 ftssel z0\.h, z0\.h, z3\.h
+.*: 047fb000 ftssel z0\.h, z0\.h, z31\.h
+.*: 047fb000 ftssel z0\.h, z0\.h, z31\.h
.*: 04a0b000 ftssel z0\.s, z0\.s, z0\.s
.*: 04a0b000 ftssel z0\.s, z0\.s, z0\.s
.*: 04a0b001 ftssel z1\.s, z0\.s, z0\.s
@@ -13837,6 +15597,227 @@ Disassembly of section .*:
.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0, #132\]
.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\]
.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\]
+.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
+.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
+.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
+.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
+.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
+.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
+.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
+.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
+.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
+.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
+.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
+.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
+.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
+.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
+.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
+.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
+.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
+.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
+.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
+.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
+.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
+.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
+.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
+.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
+.*: a4082000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-128\]
+.*: a4082000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-128\]
+.*: a40f2000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-16\]
+.*: a40f2000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-16\]
+.*: a4012000 ld1rqb \{z0\.b\}, p0/z, \[x0, #16\]
+.*: a4012000 ld1rqb \{z0\.b\}, p0/z, \[x0, #16\]
+.*: a4072000 ld1rqb \{z0\.b\}, p0/z, \[x0, #112\]
+.*: a4072000 ld1rqb \{z0\.b\}, p0/z, \[x0, #112\]
+.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
+.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
+.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
+.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
+.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
+.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
+.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
+.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
+.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
+.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
+.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
+.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
+.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
+.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
+.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
+.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
+.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
+.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
+.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
+.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
+.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
+.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
+.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
+.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
+.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
+.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
+.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
+.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
+.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
+.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
+.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
+.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
+.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
+.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
+.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
+.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
+.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
+.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
+.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
+.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
+.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
+.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
+.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
+.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
+.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
+.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
+.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
+.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
+.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
+.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
+.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
+.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
+.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
+.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
+.*: a5882000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-128\]
+.*: a5882000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-128\]
+.*: a58f2000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-16\]
+.*: a58f2000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-16\]
+.*: a5812000 ld1rqd \{z0\.d\}, p0/z, \[x0, #16\]
+.*: a5812000 ld1rqd \{z0\.d\}, p0/z, \[x0, #16\]
+.*: a5872000 ld1rqd \{z0\.d\}, p0/z, \[x0, #112\]
+.*: a5872000 ld1rqd \{z0\.d\}, p0/z, \[x0, #112\]
+.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*: a5800800 ld1rqd \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*: a5800800 ld1rqd \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*: a5801c00 ld1rqd \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*: a5801c00 ld1rqd \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*: a5800060 ld1rqd \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*: a5800060 ld1rqd \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*: a58003e0 ld1rqd \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*: a58003e0 ld1rqd \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*: a5840000 ld1rqd \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*: a5840000 ld1rqd \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*: a59e0000 ld1rqd \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*: a59e0000 ld1rqd \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
+.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
+.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
+.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
+.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
+.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
+.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
+.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
+.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
+.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
+.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
+.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
+.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
+.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
+.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
+.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
+.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
+.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
+.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
+.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
+.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
+.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
+.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
+.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
+.*: a4882000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-128\]
+.*: a4882000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-128\]
+.*: a48f2000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-16\]
+.*: a48f2000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-16\]
+.*: a4812000 ld1rqh \{z0\.h\}, p0/z, \[x0, #16\]
+.*: a4812000 ld1rqh \{z0\.h\}, p0/z, \[x0, #16\]
+.*: a4872000 ld1rqh \{z0\.h\}, p0/z, \[x0, #112\]
+.*: a4872000 ld1rqh \{z0\.h\}, p0/z, \[x0, #112\]
+.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*: a4800800 ld1rqh \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*: a4800800 ld1rqh \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*: a4801c00 ld1rqh \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*: a4801c00 ld1rqh \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*: a4800060 ld1rqh \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*: a4800060 ld1rqh \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*: a48003e0 ld1rqh \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*: a48003e0 ld1rqh \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*: a4840000 ld1rqh \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*: a4840000 ld1rqh \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*: a49e0000 ld1rqh \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*: a49e0000 ld1rqh \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
+.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
+.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
+.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
+.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
+.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
+.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
+.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
+.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
+.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
+.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
+.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
+.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
+.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
+.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
+.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
+.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
+.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
+.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
+.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
+.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
+.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
+.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
+.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
+.*: a5082000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-128\]
+.*: a5082000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-128\]
+.*: a50f2000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-16\]
+.*: a50f2000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-16\]
+.*: a5012000 ld1rqw \{z0\.s\}, p0/z, \[x0, #16\]
+.*: a5012000 ld1rqw \{z0\.s\}, p0/z, \[x0, #16\]
+.*: a5072000 ld1rqw \{z0\.s\}, p0/z, \[x0, #112\]
+.*: a5072000 ld1rqw \{z0\.s\}, p0/z, \[x0, #112\]
+.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*: a5000800 ld1rqw \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*: a5000800 ld1rqw \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*: a5001c00 ld1rqw \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*: a5001c00 ld1rqw \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*: a5000060 ld1rqw \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*: a5000060 ld1rqw \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*: a50003e0 ld1rqw \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*: a50003e0 ld1rqw \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*: a5040000 ld1rqw \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*: a5040000 ld1rqw \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*: a51e0000 ld1rqw \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*: a51e0000 ld1rqw \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
@@ -25018,6 +26999,34 @@ Disassembly of section .*:
.*: 04802060 saddv d0, p0, z3\.s
.*: 048023e0 saddv d0, p0, z31\.s
.*: 048023e0 saddv d0, p0, z31\.s
+.*: 6552a000 scvtf z0\.h, p0/m, z0\.h
+.*: 6552a000 scvtf z0\.h, p0/m, z0\.h
+.*: 6552a001 scvtf z1\.h, p0/m, z0\.h
+.*: 6552a001 scvtf z1\.h, p0/m, z0\.h
+.*: 6552a01f scvtf z31\.h, p0/m, z0\.h
+.*: 6552a01f scvtf z31\.h, p0/m, z0\.h
+.*: 6552a800 scvtf z0\.h, p2/m, z0\.h
+.*: 6552a800 scvtf z0\.h, p2/m, z0\.h
+.*: 6552bc00 scvtf z0\.h, p7/m, z0\.h
+.*: 6552bc00 scvtf z0\.h, p7/m, z0\.h
+.*: 6552a060 scvtf z0\.h, p0/m, z3\.h
+.*: 6552a060 scvtf z0\.h, p0/m, z3\.h
+.*: 6552a3e0 scvtf z0\.h, p0/m, z31\.h
+.*: 6552a3e0 scvtf z0\.h, p0/m, z31\.h
+.*: 6554a000 scvtf z0\.h, p0/m, z0\.s
+.*: 6554a000 scvtf z0\.h, p0/m, z0\.s
+.*: 6554a001 scvtf z1\.h, p0/m, z0\.s
+.*: 6554a001 scvtf z1\.h, p0/m, z0\.s
+.*: 6554a01f scvtf z31\.h, p0/m, z0\.s
+.*: 6554a01f scvtf z31\.h, p0/m, z0\.s
+.*: 6554a800 scvtf z0\.h, p2/m, z0\.s
+.*: 6554a800 scvtf z0\.h, p2/m, z0\.s
+.*: 6554bc00 scvtf z0\.h, p7/m, z0\.s
+.*: 6554bc00 scvtf z0\.h, p7/m, z0\.s
+.*: 6554a060 scvtf z0\.h, p0/m, z3\.s
+.*: 6554a060 scvtf z0\.h, p0/m, z3\.s
+.*: 6554a3e0 scvtf z0\.h, p0/m, z31\.s
+.*: 6554a3e0 scvtf z0\.h, p0/m, z31\.s
.*: 6594a000 scvtf z0\.s, p0/m, z0\.s
.*: 6594a000 scvtf z0\.s, p0/m, z0\.s
.*: 6594a001 scvtf z1\.s, p0/m, z0\.s
@@ -25046,6 +27055,20 @@ Disassembly of section .*:
.*: 65d0a060 scvtf z0\.d, p0/m, z3\.s
.*: 65d0a3e0 scvtf z0\.d, p0/m, z31\.s
.*: 65d0a3e0 scvtf z0\.d, p0/m, z31\.s
+.*: 6556a000 scvtf z0\.h, p0/m, z0\.d
+.*: 6556a000 scvtf z0\.h, p0/m, z0\.d
+.*: 6556a001 scvtf z1\.h, p0/m, z0\.d
+.*: 6556a001 scvtf z1\.h, p0/m, z0\.d
+.*: 6556a01f scvtf z31\.h, p0/m, z0\.d
+.*: 6556a01f scvtf z31\.h, p0/m, z0\.d
+.*: 6556a800 scvtf z0\.h, p2/m, z0\.d
+.*: 6556a800 scvtf z0\.h, p2/m, z0\.d
+.*: 6556bc00 scvtf z0\.h, p7/m, z0\.d
+.*: 6556bc00 scvtf z0\.h, p7/m, z0\.d
+.*: 6556a060 scvtf z0\.h, p0/m, z3\.d
+.*: 6556a060 scvtf z0\.h, p0/m, z3\.d
+.*: 6556a3e0 scvtf z0\.h, p0/m, z31\.d
+.*: 6556a3e0 scvtf z0\.h, p0/m, z31\.d
.*: 65d4a000 scvtf z0\.s, p0/m, z0\.d
.*: 65d4a000 scvtf z0\.s, p0/m, z0\.d
.*: 65d4a001 scvtf z1\.s, p0/m, z0\.d
@@ -25138,6 +27161,76 @@ Disassembly of section .*:
.*: 04d60080 sdivr z0\.d, p0/m, z0\.d, z4\.d
.*: 04d603e0 sdivr z0\.d, p0/m, z0\.d, z31\.d
.*: 04d603e0 sdivr z0\.d, p0/m, z0\.d, z31\.d
+.*: 44800000 sdot z0\.s, z0\.b, z0\.b
+.*: 44800000 sdot z0\.s, z0\.b, z0\.b
+.*: 44800001 sdot z1\.s, z0\.b, z0\.b
+.*: 44800001 sdot z1\.s, z0\.b, z0\.b
+.*: 4480001f sdot z31\.s, z0\.b, z0\.b
+.*: 4480001f sdot z31\.s, z0\.b, z0\.b
+.*: 44800040 sdot z0\.s, z2\.b, z0\.b
+.*: 44800040 sdot z0\.s, z2\.b, z0\.b
+.*: 448003e0 sdot z0\.s, z31\.b, z0\.b
+.*: 448003e0 sdot z0\.s, z31\.b, z0\.b
+.*: 44830000 sdot z0\.s, z0\.b, z3\.b
+.*: 44830000 sdot z0\.s, z0\.b, z3\.b
+.*: 449f0000 sdot z0\.s, z0\.b, z31\.b
+.*: 449f0000 sdot z0\.s, z0\.b, z31\.b
+.*: 44c00000 sdot z0\.d, z0\.h, z0\.h
+.*: 44c00000 sdot z0\.d, z0\.h, z0\.h
+.*: 44c00001 sdot z1\.d, z0\.h, z0\.h
+.*: 44c00001 sdot z1\.d, z0\.h, z0\.h
+.*: 44c0001f sdot z31\.d, z0\.h, z0\.h
+.*: 44c0001f sdot z31\.d, z0\.h, z0\.h
+.*: 44c00040 sdot z0\.d, z2\.h, z0\.h
+.*: 44c00040 sdot z0\.d, z2\.h, z0\.h
+.*: 44c003e0 sdot z0\.d, z31\.h, z0\.h
+.*: 44c003e0 sdot z0\.d, z31\.h, z0\.h
+.*: 44c30000 sdot z0\.d, z0\.h, z3\.h
+.*: 44c30000 sdot z0\.d, z0\.h, z3\.h
+.*: 44df0000 sdot z0\.d, z0\.h, z31\.h
+.*: 44df0000 sdot z0\.d, z0\.h, z31\.h
+.*: 44a00000 sdot z0\.s, z0\.b, z0\.b\[0\]
+.*: 44a00000 sdot z0\.s, z0\.b, z0\.b\[0\]
+.*: 44a00001 sdot z1\.s, z0\.b, z0\.b\[0\]
+.*: 44a00001 sdot z1\.s, z0\.b, z0\.b\[0\]
+.*: 44a0001f sdot z31\.s, z0\.b, z0\.b\[0\]
+.*: 44a0001f sdot z31\.s, z0\.b, z0\.b\[0\]
+.*: 44a00040 sdot z0\.s, z2\.b, z0\.b\[0\]
+.*: 44a00040 sdot z0\.s, z2\.b, z0\.b\[0\]
+.*: 44a003e0 sdot z0\.s, z31\.b, z0\.b\[0\]
+.*: 44a003e0 sdot z0\.s, z31\.b, z0\.b\[0\]
+.*: 44a30000 sdot z0\.s, z0\.b, z3\.b\[0\]
+.*: 44a30000 sdot z0\.s, z0\.b, z3\.b\[0\]
+.*: 44a70000 sdot z0\.s, z0\.b, z7\.b\[0\]
+.*: 44a70000 sdot z0\.s, z0\.b, z7\.b\[0\]
+.*: 44a80000 sdot z0\.s, z0\.b, z0\.b\[1\]
+.*: 44a80000 sdot z0\.s, z0\.b, z0\.b\[1\]
+.*: 44ac0000 sdot z0\.s, z0\.b, z4\.b\[1\]
+.*: 44ac0000 sdot z0\.s, z0\.b, z4\.b\[1\]
+.*: 44b30000 sdot z0\.s, z0\.b, z3\.b\[2\]
+.*: 44b30000 sdot z0\.s, z0\.b, z3\.b\[2\]
+.*: 44b80000 sdot z0\.s, z0\.b, z0\.b\[3\]
+.*: 44b80000 sdot z0\.s, z0\.b, z0\.b\[3\]
+.*: 44bd0000 sdot z0\.s, z0\.b, z5\.b\[3\]
+.*: 44bd0000 sdot z0\.s, z0\.b, z5\.b\[3\]
+.*: 44e00000 sdot z0\.d, z0\.h, z0\.h\[0\]
+.*: 44e00000 sdot z0\.d, z0\.h, z0\.h\[0\]
+.*: 44e00001 sdot z1\.d, z0\.h, z0\.h\[0\]
+.*: 44e00001 sdot z1\.d, z0\.h, z0\.h\[0\]
+.*: 44e0001f sdot z31\.d, z0\.h, z0\.h\[0\]
+.*: 44e0001f sdot z31\.d, z0\.h, z0\.h\[0\]
+.*: 44e00040 sdot z0\.d, z2\.h, z0\.h\[0\]
+.*: 44e00040 sdot z0\.d, z2\.h, z0\.h\[0\]
+.*: 44e003e0 sdot z0\.d, z31\.h, z0\.h\[0\]
+.*: 44e003e0 sdot z0\.d, z31\.h, z0\.h\[0\]
+.*: 44e30000 sdot z0\.d, z0\.h, z3\.h\[0\]
+.*: 44e30000 sdot z0\.d, z0\.h, z3\.h\[0\]
+.*: 44ef0000 sdot z0\.d, z0\.h, z15\.h\[0\]
+.*: 44ef0000 sdot z0\.d, z0\.h, z15\.h\[0\]
+.*: 44f00000 sdot z0\.d, z0\.h, z0\.h\[1\]
+.*: 44f00000 sdot z0\.d, z0\.h, z0\.h\[1\]
+.*: 44fb0000 sdot z0\.d, z0\.h, z11\.h\[1\]
+.*: 44fb0000 sdot z0\.d, z0\.h, z11\.h\[1\]
.*: 0520c000 mov z0\.b, p0/m, z0\.b
.*: 0520c000 mov z0\.b, p0/m, z0\.b
.*: 0520c001 sel z1\.b, p0, z0\.b, z0\.b
@@ -32917,6 +35010,34 @@ Disassembly of section .*:
.*: 04c12060 uaddv d0, p0, z3\.d
.*: 04c123e0 uaddv d0, p0, z31\.d
.*: 04c123e0 uaddv d0, p0, z31\.d
+.*: 6553a000 ucvtf z0\.h, p0/m, z0\.h
+.*: 6553a000 ucvtf z0\.h, p0/m, z0\.h
+.*: 6553a001 ucvtf z1\.h, p0/m, z0\.h
+.*: 6553a001 ucvtf z1\.h, p0/m, z0\.h
+.*: 6553a01f ucvtf z31\.h, p0/m, z0\.h
+.*: 6553a01f ucvtf z31\.h, p0/m, z0\.h
+.*: 6553a800 ucvtf z0\.h, p2/m, z0\.h
+.*: 6553a800 ucvtf z0\.h, p2/m, z0\.h
+.*: 6553bc00 ucvtf z0\.h, p7/m, z0\.h
+.*: 6553bc00 ucvtf z0\.h, p7/m, z0\.h
+.*: 6553a060 ucvtf z0\.h, p0/m, z3\.h
+.*: 6553a060 ucvtf z0\.h, p0/m, z3\.h
+.*: 6553a3e0 ucvtf z0\.h, p0/m, z31\.h
+.*: 6553a3e0 ucvtf z0\.h, p0/m, z31\.h
+.*: 6555a000 ucvtf z0\.h, p0/m, z0\.s
+.*: 6555a000 ucvtf z0\.h, p0/m, z0\.s
+.*: 6555a001 ucvtf z1\.h, p0/m, z0\.s
+.*: 6555a001 ucvtf z1\.h, p0/m, z0\.s
+.*: 6555a01f ucvtf z31\.h, p0/m, z0\.s
+.*: 6555a01f ucvtf z31\.h, p0/m, z0\.s
+.*: 6555a800 ucvtf z0\.h, p2/m, z0\.s
+.*: 6555a800 ucvtf z0\.h, p2/m, z0\.s
+.*: 6555bc00 ucvtf z0\.h, p7/m, z0\.s
+.*: 6555bc00 ucvtf z0\.h, p7/m, z0\.s
+.*: 6555a060 ucvtf z0\.h, p0/m, z3\.s
+.*: 6555a060 ucvtf z0\.h, p0/m, z3\.s
+.*: 6555a3e0 ucvtf z0\.h, p0/m, z31\.s
+.*: 6555a3e0 ucvtf z0\.h, p0/m, z31\.s
.*: 6595a000 ucvtf z0\.s, p0/m, z0\.s
.*: 6595a000 ucvtf z0\.s, p0/m, z0\.s
.*: 6595a001 ucvtf z1\.s, p0/m, z0\.s
@@ -32945,6 +35066,20 @@ Disassembly of section .*:
.*: 65d1a060 ucvtf z0\.d, p0/m, z3\.s
.*: 65d1a3e0 ucvtf z0\.d, p0/m, z31\.s
.*: 65d1a3e0 ucvtf z0\.d, p0/m, z31\.s
+.*: 6557a000 ucvtf z0\.h, p0/m, z0\.d
+.*: 6557a000 ucvtf z0\.h, p0/m, z0\.d
+.*: 6557a001 ucvtf z1\.h, p0/m, z0\.d
+.*: 6557a001 ucvtf z1\.h, p0/m, z0\.d
+.*: 6557a01f ucvtf z31\.h, p0/m, z0\.d
+.*: 6557a01f ucvtf z31\.h, p0/m, z0\.d
+.*: 6557a800 ucvtf z0\.h, p2/m, z0\.d
+.*: 6557a800 ucvtf z0\.h, p2/m, z0\.d
+.*: 6557bc00 ucvtf z0\.h, p7/m, z0\.d
+.*: 6557bc00 ucvtf z0\.h, p7/m, z0\.d
+.*: 6557a060 ucvtf z0\.h, p0/m, z3\.d
+.*: 6557a060 ucvtf z0\.h, p0/m, z3\.d
+.*: 6557a3e0 ucvtf z0\.h, p0/m, z31\.d
+.*: 6557a3e0 ucvtf z0\.h, p0/m, z31\.d
.*: 65d5a000 ucvtf z0\.s, p0/m, z0\.d
.*: 65d5a000 ucvtf z0\.s, p0/m, z0\.d
.*: 65d5a001 ucvtf z1\.s, p0/m, z0\.d
@@ -33037,6 +35172,76 @@ Disassembly of section .*:
.*: 04d70080 udivr z0\.d, p0/m, z0\.d, z4\.d
.*: 04d703e0 udivr z0\.d, p0/m, z0\.d, z31\.d
.*: 04d703e0 udivr z0\.d, p0/m, z0\.d, z31\.d
+.*: 44800400 udot z0\.s, z0\.b, z0\.b
+.*: 44800400 udot z0\.s, z0\.b, z0\.b
+.*: 44800401 udot z1\.s, z0\.b, z0\.b
+.*: 44800401 udot z1\.s, z0\.b, z0\.b
+.*: 4480041f udot z31\.s, z0\.b, z0\.b
+.*: 4480041f udot z31\.s, z0\.b, z0\.b
+.*: 44800440 udot z0\.s, z2\.b, z0\.b
+.*: 44800440 udot z0\.s, z2\.b, z0\.b
+.*: 448007e0 udot z0\.s, z31\.b, z0\.b
+.*: 448007e0 udot z0\.s, z31\.b, z0\.b
+.*: 44830400 udot z0\.s, z0\.b, z3\.b
+.*: 44830400 udot z0\.s, z0\.b, z3\.b
+.*: 449f0400 udot z0\.s, z0\.b, z31\.b
+.*: 449f0400 udot z0\.s, z0\.b, z31\.b
+.*: 44c00400 udot z0\.d, z0\.h, z0\.h
+.*: 44c00400 udot z0\.d, z0\.h, z0\.h
+.*: 44c00401 udot z1\.d, z0\.h, z0\.h
+.*: 44c00401 udot z1\.d, z0\.h, z0\.h
+.*: 44c0041f udot z31\.d, z0\.h, z0\.h
+.*: 44c0041f udot z31\.d, z0\.h, z0\.h
+.*: 44c00440 udot z0\.d, z2\.h, z0\.h
+.*: 44c00440 udot z0\.d, z2\.h, z0\.h
+.*: 44c007e0 udot z0\.d, z31\.h, z0\.h
+.*: 44c007e0 udot z0\.d, z31\.h, z0\.h
+.*: 44c30400 udot z0\.d, z0\.h, z3\.h
+.*: 44c30400 udot z0\.d, z0\.h, z3\.h
+.*: 44df0400 udot z0\.d, z0\.h, z31\.h
+.*: 44df0400 udot z0\.d, z0\.h, z31\.h
+.*: 44a00400 udot z0\.s, z0\.b, z0\.b\[0\]
+.*: 44a00400 udot z0\.s, z0\.b, z0\.b\[0\]
+.*: 44a00401 udot z1\.s, z0\.b, z0\.b\[0\]
+.*: 44a00401 udot z1\.s, z0\.b, z0\.b\[0\]
+.*: 44a0041f udot z31\.s, z0\.b, z0\.b\[0\]
+.*: 44a0041f udot z31\.s, z0\.b, z0\.b\[0\]
+.*: 44a00440 udot z0\.s, z2\.b, z0\.b\[0\]
+.*: 44a00440 udot z0\.s, z2\.b, z0\.b\[0\]
+.*: 44a007e0 udot z0\.s, z31\.b, z0\.b\[0\]
+.*: 44a007e0 udot z0\.s, z31\.b, z0\.b\[0\]
+.*: 44a30400 udot z0\.s, z0\.b, z3\.b\[0\]
+.*: 44a30400 udot z0\.s, z0\.b, z3\.b\[0\]
+.*: 44a70400 udot z0\.s, z0\.b, z7\.b\[0\]
+.*: 44a70400 udot z0\.s, z0\.b, z7\.b\[0\]
+.*: 44a80400 udot z0\.s, z0\.b, z0\.b\[1\]
+.*: 44a80400 udot z0\.s, z0\.b, z0\.b\[1\]
+.*: 44ac0400 udot z0\.s, z0\.b, z4\.b\[1\]
+.*: 44ac0400 udot z0\.s, z0\.b, z4\.b\[1\]
+.*: 44b30400 udot z0\.s, z0\.b, z3\.b\[2\]
+.*: 44b30400 udot z0\.s, z0\.b, z3\.b\[2\]
+.*: 44b80400 udot z0\.s, z0\.b, z0\.b\[3\]
+.*: 44b80400 udot z0\.s, z0\.b, z0\.b\[3\]
+.*: 44bd0400 udot z0\.s, z0\.b, z5\.b\[3\]
+.*: 44bd0400 udot z0\.s, z0\.b, z5\.b\[3\]
+.*: 44e00400 udot z0\.d, z0\.h, z0\.h\[0\]
+.*: 44e00400 udot z0\.d, z0\.h, z0\.h\[0\]
+.*: 44e00401 udot z1\.d, z0\.h, z0\.h\[0\]
+.*: 44e00401 udot z1\.d, z0\.h, z0\.h\[0\]
+.*: 44e0041f udot z31\.d, z0\.h, z0\.h\[0\]
+.*: 44e0041f udot z31\.d, z0\.h, z0\.h\[0\]
+.*: 44e00440 udot z0\.d, z2\.h, z0\.h\[0\]
+.*: 44e00440 udot z0\.d, z2\.h, z0\.h\[0\]
+.*: 44e007e0 udot z0\.d, z31\.h, z0\.h\[0\]
+.*: 44e007e0 udot z0\.d, z31\.h, z0\.h\[0\]
+.*: 44e30400 udot z0\.d, z0\.h, z3\.h\[0\]
+.*: 44e30400 udot z0\.d, z0\.h, z3\.h\[0\]
+.*: 44ef0400 udot z0\.d, z0\.h, z15\.h\[0\]
+.*: 44ef0400 udot z0\.d, z0\.h, z15\.h\[0\]
+.*: 44f00400 udot z0\.d, z0\.h, z0\.h\[1\]
+.*: 44f00400 udot z0\.d, z0\.h, z0\.h\[1\]
+.*: 44fb0400 udot z0\.d, z0\.h, z11\.h\[1\]
+.*: 44fb0400 udot z0\.d, z0\.h, z11\.h\[1\]
.*: 2529c000 umax z0\.b, z0\.b, #0
.*: 2529c000 umax z0\.b, z0\.b, #0
.*: 2529c001 umax z1\.b, z1\.b, #0
@@ -37999,6 +40204,24 @@ Disassembly of section .*:
.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
+.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
+.*: 6543c010 facge p0\.h, p0/z, z0\.h, z3\.h
+.*: 6543c010 facge p0\.h, p0/z, z0\.h, z3\.h
+.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
+.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
+.*: 6540c090 facge p0\.h, p0/z, z4\.h, z0\.h
+.*: 6540c090 facge p0\.h, p0/z, z4\.h, z0\.h
+.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
+.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
@@ -38035,6 +40258,24 @@ Disassembly of section .*:
.*: 65c0c090 facge p0\.d, p0/z, z4\.d, z0\.d
.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
+.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 6543e010 facgt p0\.h, p0/z, z0\.h, z3\.h
+.*: 6543e010 facgt p0\.h, p0/z, z0\.h, z3\.h
+.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 6540e090 facgt p0\.h, p0/z, z4\.h, z0\.h
+.*: 6540e090 facgt p0\.h, p0/z, z4\.h, z0\.h
+.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
.*: 6580e011 facgt p1\.s, p0/z, z0\.s, z0\.s
@@ -38071,6 +40312,24 @@ Disassembly of section .*:
.*: 65c0e090 facgt p0\.d, p0/z, z4\.d, z0\.d
.*: 65c0e3f0 facgt p0\.d, p0/z, z31\.d, z0\.d
.*: 65c0e3f0 facgt p0\.d, p0/z, z31\.d, z0\.d
+.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
+.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
+.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
+.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
+.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
+.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
+.*: 65434000 fcmge p0\.h, p0/z, z0\.h, z3\.h
+.*: 65434000 fcmge p0\.h, p0/z, z0\.h, z3\.h
+.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
+.*: 65404080 fcmge p0\.h, p0/z, z4\.h, z0\.h
+.*: 65404080 fcmge p0\.h, p0/z, z4\.h, z0\.h
+.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
+.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
@@ -38107,6 +40366,24 @@ Disassembly of section .*:
.*: 65c04080 fcmge p0\.d, p0/z, z4\.d, z0\.d
.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
+.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
+.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
+.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
+.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
+.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
+.*: 65434010 fcmgt p0\.h, p0/z, z0\.h, z3\.h
+.*: 65434010 fcmgt p0\.h, p0/z, z0\.h, z3\.h
+.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
+.*: 65404090 fcmgt p0\.h, p0/z, z4\.h, z0\.h
+.*: 65404090 fcmgt p0\.h, p0/z, z4\.h, z0\.h
+.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
+.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
@@ -38143,6 +40420,12 @@ Disassembly of section .*:
.*: 65c04090 fcmgt p0\.d, p0/z, z4\.d, z0\.d
.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
+.*: 2578c000 mov z0\.h, #0
+.*: 2578c000 mov z0\.h, #0
+.*: 2578c001 mov z1\.h, #0
+.*: 2578c001 mov z1\.h, #0
+.*: 2578c01f mov z31\.h, #0
+.*: 2578c01f mov z31\.h, #0
.*: 25b8c000 mov z0\.s, #0
.*: 25b8c000 mov z0\.s, #0
.*: 25b8c001 mov z1\.s, #0
@@ -38155,6 +40438,16 @@ Disassembly of section .*:
.*: 25f8c001 mov z1\.d, #0
.*: 25f8c01f mov z31\.d, #0
.*: 25f8c01f mov z31\.d, #0
+.*: 05504000 mov z0\.h, p0/m, #0
+.*: 05504000 mov z0\.h, p0/m, #0
+.*: 05504001 mov z1\.h, p0/m, #0
+.*: 05504001 mov z1\.h, p0/m, #0
+.*: 0550401f mov z31\.h, p0/m, #0
+.*: 0550401f mov z31\.h, p0/m, #0
+.*: 05524000 mov z0\.h, p2/m, #0
+.*: 05524000 mov z0\.h, p2/m, #0
+.*: 055f4000 mov z0\.h, p15/m, #0
+.*: 055f4000 mov z0\.h, p15/m, #0
.*: 05904000 mov z0\.s, p0/m, #0
.*: 05904000 mov z0\.s, p0/m, #0
.*: 05904001 mov z1\.s, p0/m, #0
@@ -38236,3 +40529,36 @@ Disassembly of section .*:
.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
+
+.*: 6ec3c441 fcmla v1\.2d, v2\.2d, v3\.2d, #0
+.*: 6ec3cc41 fcmla v1\.2d, v2\.2d, v3\.2d, #90
+.*: 6ec3d441 fcmla v1\.2d, v2\.2d, v3\.2d, #180
+.*: 6ec3dc41 fcmla v1\.2d, v2\.2d, v3\.2d, #270
+.*: 2e83cc41 fcmla v1\.2s, v2\.2s, v3\.2s, #90
+.*: 6e83cc41 fcmla v1\.4s, v2\.4s, v3\.4s, #90
+.*: 2e43cc41 fcmla v1\.4h, v2\.4h, v3\.4h, #90
+.*: 6e43cc41 fcmla v1\.8h, v2\.8h, v3\.8h, #90
+.*: 6f831041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #0
+.*: 6f833041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #90
+.*: 6f835041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #180
+.*: 6f837041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #270
+.*: 6f833841 fcmla v1\.4s, v2\.4s, v3\.s\[1\], #90
+.*: 2f433041 fcmla v1\.4h, v2\.4h, v3\.h\[0\], #90
+.*: 2f633041 fcmla v1\.4h, v2\.4h, v3\.h\[1\], #90
+.*: 6f433041 fcmla v1\.8h, v2\.8h, v3\.h\[0\], #90
+.*: 6f633041 fcmla v1\.8h, v2\.8h, v3\.h\[1\], #90
+.*: 6f433841 fcmla v1\.8h, v2\.8h, v3\.h\[2\], #90
+.*: 6f633841 fcmla v1\.8h, v2\.8h, v3\.h\[3\], #90
+.*: 6ec3e441 fcadd v1\.2d, v2\.2d, v3\.2d, #90
+.*: 6ec3f441 fcadd v1\.2d, v2\.2d, v3\.2d, #270
+.*: 2e83e441 fcadd v1\.2s, v2\.2s, v3\.2s, #90
+.*: 6e83e441 fcadd v1\.4s, v2\.4s, v3\.4s, #90
+.*: 2e43e441 fcadd v1\.4h, v2\.4h, v3\.4h, #90
+.*: 6e43e441 fcadd v1\.8h, v2\.8h, v3\.8h, #90
+.*: 4e63d441 fadd v1\.2d, v2\.2d, v3\.2d
+.*: 0e23d441 fadd v1\.2s, v2\.2s, v3\.2s
+.*: 4e23d441 fadd v1\.4s, v2\.4s, v3\.4s
+.*: 0e401400 fadd v0\.4h, v0\.4h, v0\.4h
+.*: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
+.*: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
+.*: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
diff --git a/gas/testsuite/gas/aarch64/sve.s b/gas/testsuite/gas/aarch64/sve.s
index e2c3fd0..2130b0d 100644
--- a/gas/testsuite/gas/aarch64/sve.s
+++ b/gas/testsuite/gas/aarch64/sve.s
@@ -15,6 +15,24 @@
.equ w0, 1
.equ x0, 1
+ fmov z0.h, #2.0000000000
+ FMOV Z0.H, #2.0000000000
+ fmov z1.h, #2.0000000000
+ FMOV Z1.H, #2.0000000000
+ fmov z31.h, #2.0000000000
+ FMOV Z31.H, #2.0000000000
+ fmov z0.h, #16.0000000000
+ FMOV Z0.H, #16.0000000000
+ fmov z0.h, #0.1875000000
+ FMOV Z0.H, #0.1875000000
+ fmov z0.h, #1.9375000000
+ FMOV Z0.H, #1.9375000000
+ fmov z0.h, #-3.0000000000
+ FMOV Z0.H, #-3.0000000000
+ fmov z0.h, #-0.1250000000
+ FMOV Z0.H, #-0.1250000000
+ fmov z0.h, #-1.9375000000
+ FMOV Z0.H, #-1.9375000000
fmov z0.s, #2.0000000000
FMOV Z0.S, #2.0000000000
fmov z1.s, #2.0000000000
@@ -51,6 +69,28 @@
FMOV Z0.D, #-0.1250000000
fmov z0.d, #-1.9375000000
FMOV Z0.D, #-1.9375000000
+ fmov z0.h, p0/m, #2.0000000000
+ FMOV Z0.H, P0/M, #2.0000000000
+ fmov z1.h, p0/m, #2.0000000000
+ FMOV Z1.H, P0/M, #2.0000000000
+ fmov z31.h, p0/m, #2.0000000000
+ FMOV Z31.H, P0/M, #2.0000000000
+ fmov z0.h, p2/m, #2.0000000000
+ FMOV Z0.H, P2/M, #2.0000000000
+ fmov z0.h, p15/m, #2.0000000000
+ FMOV Z0.H, P15/M, #2.0000000000
+ fmov z0.h, p0/m, #16.0000000000
+ FMOV Z0.H, P0/M, #16.0000000000
+ fmov z0.h, p0/m, #0.1875000000
+ FMOV Z0.H, P0/M, #0.1875000000
+ fmov z0.h, p0/m, #1.9375000000
+ FMOV Z0.H, P0/M, #1.9375000000
+ fmov z0.h, p0/m, #-3.0000000000
+ FMOV Z0.H, P0/M, #-3.0000000000
+ fmov z0.h, p0/m, #-0.1250000000
+ FMOV Z0.H, P0/M, #-0.1250000000
+ fmov z0.h, p0/m, #-1.9375000000
+ FMOV Z0.H, P0/M, #-1.9375000000
fmov z0.s, p0/m, #2.0000000000
FMOV Z0.S, P0/M, #2.0000000000
fmov z1.s, p0/m, #2.0000000000
@@ -145,6 +185,16 @@
MOV Z0.D, D2
mov z0.d, d31
MOV Z0.D, D31
+ mov z0.q, q0
+ mov z0.Q, Q0
+ mov z1.q, q0
+ mov z1.Q, Q0
+ mov z31.q, q0
+ mov z31.Q, Q0
+ mov z0.q, q2
+ mov z0.Q, Q2
+ mov z0.q, q31
+ mov z0.Q, Q31
mov z0.b, w0
MOV Z0.B, W0
mov z1.b, w0
@@ -323,6 +373,22 @@
MOV Z0.B, Z31.B[7]
mov z0.b, z0.b[8]
MOV Z0.B, Z0.B[8]
+ mov z0.q, z0.q[1]
+ MOV Z0.Q, Z0.Q[1]
+ mov z1.q, z0.q[1]
+ MOV Z1.Q, Z0.Q[1]
+ mov z31.q, z0.q[1]
+ MOV Z31.Q, Z0.Q[1]
+ mov z0.q, z2.q[1]
+ MOV Z0.Q, Z2.Q[1]
+ mov z0.q, z31.q[1]
+ MOV Z0.Q, Z31.Q[1]
+ mov z0.q, z0.q[0]
+ MOV Z0.Q, Z0.Q[0]
+ mov z0.q, z0.q[2]
+ MOV Z0.Q, Z0.Q[2]
+ mov z0.q, z0.q[3]
+ MOV Z0.Q, Z0.Q[3]
mov z0.s, #0xff
MOV Z0.S, #0XFF
mov z0.d, #0xff000000ff
@@ -7654,6 +7720,22 @@
DUP Z0.B, Z31.B[7]
dup z0.b, z0.b[8]
DUP Z0.B, Z0.B[8]
+ dup z0.q, z0.q[1]
+ DUP Z0.Q, Z0.Q[1]
+ dup z1.q, z0.q[1]
+ DUP Z1.Q, Z0.Q[1]
+ dup z31.q, z0.q[1]
+ DUP Z31.Q, Z0.Q[1]
+ dup z0.q, z2.q[1]
+ DUP Z0.Q, Z2.Q[1]
+ dup z0.q, z31.q[1]
+ DUP Z0.Q, Z31.Q[1]
+ dup z0.q, z0.q[0]
+ DUP Z0.Q, Z0.Q[0]
+ dup z0.q, z0.q[2]
+ DUP Z0.Q, Z0.Q[2]
+ dup z0.q, z0.q[3]
+ DUP Z0.Q, Z0.Q[3]
dup z0.b, #0
DUP Z0.B, #0
dup z0.b, #0, lsl #0
@@ -8101,6 +8183,22 @@
EXT Z0.B, Z0.B, Z0.B, #129
ext z0.b, z0.b, z0.b, #255
EXT Z0.B, Z0.B, Z0.B, #255
+ fabd z0.h, p0/m, z0.h, z0.h
+ FABD Z0.H, P0/M, Z0.H, Z0.H
+ fabd z1.h, p0/m, z1.h, z0.h
+ FABD Z1.H, P0/M, Z1.H, Z0.H
+ fabd z31.h, p0/m, z31.h, z0.h
+ FABD Z31.H, P0/M, Z31.H, Z0.H
+ fabd z0.h, p2/m, z0.h, z0.h
+ FABD Z0.H, P2/M, Z0.H, Z0.H
+ fabd z0.h, p7/m, z0.h, z0.h
+ FABD Z0.H, P7/M, Z0.H, Z0.H
+ fabd z3.h, p0/m, z3.h, z0.h
+ FABD Z3.H, P0/M, Z3.H, Z0.H
+ fabd z0.h, p0/m, z0.h, z4.h
+ FABD Z0.H, P0/M, Z0.H, Z4.H
+ fabd z0.h, p0/m, z0.h, z31.h
+ FABD Z0.H, P0/M, Z0.H, Z31.H
fabd z0.s, p0/m, z0.s, z0.s
FABD Z0.S, P0/M, Z0.S, Z0.S
fabd z1.s, p0/m, z1.s, z0.s
@@ -8133,6 +8231,20 @@
FABD Z0.D, P0/M, Z0.D, Z4.D
fabd z0.d, p0/m, z0.d, z31.d
FABD Z0.D, P0/M, Z0.D, Z31.D
+ fabs z0.h, p0/m, z0.h
+ FABS Z0.H, P0/M, Z0.H
+ fabs z1.h, p0/m, z0.h
+ FABS Z1.H, P0/M, Z0.H
+ fabs z31.h, p0/m, z0.h
+ FABS Z31.H, P0/M, Z0.H
+ fabs z0.h, p2/m, z0.h
+ FABS Z0.H, P2/M, Z0.H
+ fabs z0.h, p7/m, z0.h
+ FABS Z0.H, P7/M, Z0.H
+ fabs z0.h, p0/m, z3.h
+ FABS Z0.H, P0/M, Z3.H
+ fabs z0.h, p0/m, z31.h
+ FABS Z0.H, P0/M, Z31.H
fabs z0.s, p0/m, z0.s
FABS Z0.S, P0/M, Z0.S
fabs z1.s, p0/m, z0.s
@@ -8161,6 +8273,24 @@
FABS Z0.D, P0/M, Z3.D
fabs z0.d, p0/m, z31.d
FABS Z0.D, P0/M, Z31.D
+ facge p0.h, p0/z, z0.h, z0.h
+ FACGE P0.H, P0/Z, Z0.H, Z0.H
+ facge p1.h, p0/z, z0.h, z0.h
+ FACGE P1.H, P0/Z, Z0.H, Z0.H
+ facge p15.h, p0/z, z0.h, z0.h
+ FACGE P15.H, P0/Z, Z0.H, Z0.H
+ facge p0.h, p2/z, z0.h, z0.h
+ FACGE P0.H, P2/Z, Z0.H, Z0.H
+ facge p0.h, p7/z, z0.h, z0.h
+ FACGE P0.H, P7/Z, Z0.H, Z0.H
+ facge p0.h, p0/z, z3.h, z0.h
+ FACGE P0.H, P0/Z, Z3.H, Z0.H
+ facge p0.h, p0/z, z31.h, z0.h
+ FACGE P0.H, P0/Z, Z31.H, Z0.H
+ facge p0.h, p0/z, z0.h, z4.h
+ FACGE P0.H, P0/Z, Z0.H, Z4.H
+ facge p0.h, p0/z, z0.h, z31.h
+ FACGE P0.H, P0/Z, Z0.H, Z31.H
facge p0.s, p0/z, z0.s, z0.s
FACGE P0.S, P0/Z, Z0.S, Z0.S
facge p1.s, p0/z, z0.s, z0.s
@@ -8197,6 +8327,24 @@
FACGE P0.D, P0/Z, Z0.D, Z4.D
facge p0.d, p0/z, z0.d, z31.d
FACGE P0.D, P0/Z, Z0.D, Z31.D
+ facgt p0.h, p0/z, z0.h, z0.h
+ FACGT P0.H, P0/Z, Z0.H, Z0.H
+ facgt p1.h, p0/z, z0.h, z0.h
+ FACGT P1.H, P0/Z, Z0.H, Z0.H
+ facgt p15.h, p0/z, z0.h, z0.h
+ FACGT P15.H, P0/Z, Z0.H, Z0.H
+ facgt p0.h, p2/z, z0.h, z0.h
+ FACGT P0.H, P2/Z, Z0.H, Z0.H
+ facgt p0.h, p7/z, z0.h, z0.h
+ FACGT P0.H, P7/Z, Z0.H, Z0.H
+ facgt p0.h, p0/z, z3.h, z0.h
+ FACGT P0.H, P0/Z, Z3.H, Z0.H
+ facgt p0.h, p0/z, z31.h, z0.h
+ FACGT P0.H, P0/Z, Z31.H, Z0.H
+ facgt p0.h, p0/z, z0.h, z4.h
+ FACGT P0.H, P0/Z, Z0.H, Z4.H
+ facgt p0.h, p0/z, z0.h, z31.h
+ FACGT P0.H, P0/Z, Z0.H, Z31.H
facgt p0.s, p0/z, z0.s, z0.s
FACGT P0.S, P0/Z, Z0.S, Z0.S
facgt p1.s, p0/z, z0.s, z0.s
@@ -8233,6 +8381,20 @@
FACGT P0.D, P0/Z, Z0.D, Z4.D
facgt p0.d, p0/z, z0.d, z31.d
FACGT P0.D, P0/Z, Z0.D, Z31.D
+ fadd z0.h, z0.h, z0.h
+ FADD Z0.H, Z0.H, Z0.H
+ fadd z1.h, z0.h, z0.h
+ FADD Z1.H, Z0.H, Z0.H
+ fadd z31.h, z0.h, z0.h
+ FADD Z31.H, Z0.H, Z0.H
+ fadd z0.h, z2.h, z0.h
+ FADD Z0.H, Z2.H, Z0.H
+ fadd z0.h, z31.h, z0.h
+ FADD Z0.H, Z31.H, Z0.H
+ fadd z0.h, z0.h, z3.h
+ FADD Z0.H, Z0.H, Z3.H
+ fadd z0.h, z0.h, z31.h
+ FADD Z0.H, Z0.H, Z31.H
fadd z0.s, z0.s, z0.s
FADD Z0.S, Z0.S, Z0.S
fadd z1.s, z0.s, z0.s
@@ -8261,6 +8423,22 @@
FADD Z0.D, Z0.D, Z3.D
fadd z0.d, z0.d, z31.d
FADD Z0.D, Z0.D, Z31.D
+ fadd z0.h, p0/m, z0.h, z0.h
+ FADD Z0.H, P0/M, Z0.H, Z0.H
+ fadd z1.h, p0/m, z1.h, z0.h
+ FADD Z1.H, P0/M, Z1.H, Z0.H
+ fadd z31.h, p0/m, z31.h, z0.h
+ FADD Z31.H, P0/M, Z31.H, Z0.H
+ fadd z0.h, p2/m, z0.h, z0.h
+ FADD Z0.H, P2/M, Z0.H, Z0.H
+ fadd z0.h, p7/m, z0.h, z0.h
+ FADD Z0.H, P7/M, Z0.H, Z0.H
+ fadd z3.h, p0/m, z3.h, z0.h
+ FADD Z3.H, P0/M, Z3.H, Z0.H
+ fadd z0.h, p0/m, z0.h, z4.h
+ FADD Z0.H, P0/M, Z0.H, Z4.H
+ fadd z0.h, p0/m, z0.h, z31.h
+ FADD Z0.H, P0/M, Z0.H, Z31.H
fadd z0.s, p0/m, z0.s, z0.s
FADD Z0.S, P0/M, Z0.S, Z0.S
fadd z1.s, p0/m, z1.s, z0.s
@@ -8293,6 +8471,34 @@
FADD Z0.D, P0/M, Z0.D, Z4.D
fadd z0.d, p0/m, z0.d, z31.d
FADD Z0.D, P0/M, Z0.D, Z31.D
+ fadd z0.h, p0/m, z0.h, #0.5
+ FADD Z0.H, P0/M, Z0.H, #0.5
+ fadd z0.h, p0/m, z0.h, #0.50000
+ fadd z0.h, p0/m, z0.h, #5.0000000000e-01
+ fadd z1.h, p0/m, z1.h, #0.5
+ FADD Z1.H, P0/M, Z1.H, #0.5
+ fadd z1.h, p0/m, z1.h, #0.50000
+ fadd z1.h, p0/m, z1.h, #5.0000000000e-01
+ fadd z31.h, p0/m, z31.h, #0.5
+ FADD Z31.H, P0/M, Z31.H, #0.5
+ fadd z31.h, p0/m, z31.h, #0.50000
+ fadd z31.h, p0/m, z31.h, #5.0000000000e-01
+ fadd z0.h, p2/m, z0.h, #0.5
+ FADD Z0.H, P2/M, Z0.H, #0.5
+ fadd z0.h, p2/m, z0.h, #0.50000
+ fadd z0.h, p2/m, z0.h, #5.0000000000e-01
+ fadd z0.h, p7/m, z0.h, #0.5
+ FADD Z0.H, P7/M, Z0.H, #0.5
+ fadd z0.h, p7/m, z0.h, #0.50000
+ fadd z0.h, p7/m, z0.h, #5.0000000000e-01
+ fadd z3.h, p0/m, z3.h, #0.5
+ FADD Z3.H, P0/M, Z3.H, #0.5
+ fadd z3.h, p0/m, z3.h, #0.50000
+ fadd z3.h, p0/m, z3.h, #5.0000000000e-01
+ fadd z0.h, p0/m, z0.h, #1.0
+ FADD Z0.H, P0/M, Z0.H, #1.0
+ fadd z0.h, p0/m, z0.h, #1.00000
+ fadd z0.h, p0/m, z0.h, #1.0000000000e+00
fadd z0.s, p0/m, z0.s, #0.5
FADD Z0.S, P0/M, Z0.S, #0.5
fadd z0.s, p0/m, z0.s, #0.50000
@@ -8349,6 +8555,22 @@
FADD Z0.D, P0/M, Z0.D, #1.0
fadd z0.d, p0/m, z0.d, #1.00000
fadd z0.d, p0/m, z0.d, #1.0000000000e+00
+ fadda h0, p0, h0, z0.h
+ FADDA H0, P0, H0, Z0.H
+ fadda h1, p0, h1, z0.h
+ FADDA H1, P0, H1, Z0.H
+ fadda h31, p0, h31, z0.h
+ FADDA H31, P0, H31, Z0.H
+ fadda h0, p2, h0, z0.h
+ FADDA H0, P2, H0, Z0.H
+ fadda h0, p7, h0, z0.h
+ FADDA H0, P7, H0, Z0.H
+ fadda h3, p0, h3, z0.h
+ FADDA H3, P0, H3, Z0.H
+ fadda h0, p0, h0, z4.h
+ FADDA H0, P0, H0, Z4.H
+ fadda h0, p0, h0, z31.h
+ FADDA H0, P0, H0, Z31.H
fadda s0, p0, s0, z0.s
FADDA S0, P0, S0, Z0.S
fadda s1, p0, s1, z0.s
@@ -8381,6 +8603,20 @@
FADDA D0, P0, D0, Z4.D
fadda d0, p0, d0, z31.d
FADDA D0, P0, D0, Z31.D
+ faddv h0, p0, z0.h
+ FADDV H0, P0, Z0.H
+ faddv h1, p0, z0.h
+ FADDV H1, P0, Z0.H
+ faddv h31, p0, z0.h
+ FADDV H31, P0, Z0.H
+ faddv h0, p2, z0.h
+ FADDV H0, P2, Z0.H
+ faddv h0, p7, z0.h
+ FADDV H0, P7, Z0.H
+ faddv h0, p0, z3.h
+ FADDV H0, P0, Z3.H
+ faddv h0, p0, z31.h
+ FADDV H0, P0, Z31.H
faddv s0, p0, z0.s
FADDV S0, P0, Z0.S
faddv s1, p0, z0.s
@@ -8409,6 +8645,202 @@
FADDV D0, P0, Z3.D
faddv d0, p0, z31.d
FADDV D0, P0, Z31.D
+ fcadd z0.h, p0/m, z0.h, z0.h, #90
+ FCADD Z0.H, P0/M, Z0.H, Z0.H, #90
+ fcadd z1.h, p0/m, z1.h, z0.h, #90
+ FCADD Z1.H, P0/M, Z1.H, Z0.H, #90
+ fcadd z31.h, p0/m, z31.h, z0.h, #90
+ FCADD Z31.H, P0/M, Z31.H, Z0.H, #90
+ fcadd z0.h, p2/m, z0.h, z0.h, #90
+ FCADD Z0.H, P2/M, Z0.H, Z0.H, #90
+ fcadd z0.h, p7/m, z0.h, z0.h, #90
+ FCADD Z0.H, P7/M, Z0.H, Z0.H, #90
+ fcadd z3.h, p0/m, z3.h, z0.h, #90
+ FCADD Z3.H, P0/M, Z3.H, Z0.H, #90
+ fcadd z0.h, p0/m, z0.h, z4.h, #90
+ FCADD Z0.H, P0/M, Z0.H, Z4.H, #90
+ fcadd z0.h, p0/m, z0.h, z31.h, #90
+ FCADD Z0.H, P0/M, Z0.H, Z31.H, #90
+ fcadd z0.h, p0/m, z0.h, z0.h, #270
+ FCADD Z0.H, P0/M, Z0.H, Z0.H, #270
+ fcadd z0.s, p0/m, z0.s, z0.s, #90
+ FCADD Z0.S, P0/M, Z0.S, Z0.S, #90
+ fcadd z1.s, p0/m, z1.s, z0.s, #90
+ FCADD Z1.S, P0/M, Z1.S, Z0.S, #90
+ fcadd z31.s, p0/m, z31.s, z0.s, #90
+ FCADD Z31.S, P0/M, Z31.S, Z0.S, #90
+ fcadd z0.s, p2/m, z0.s, z0.s, #90
+ FCADD Z0.S, P2/M, Z0.S, Z0.S, #90
+ fcadd z0.s, p7/m, z0.s, z0.s, #90
+ FCADD Z0.S, P7/M, Z0.S, Z0.S, #90
+ fcadd z3.s, p0/m, z3.s, z0.s, #90
+ FCADD Z3.S, P0/M, Z3.S, Z0.S, #90
+ fcadd z0.s, p0/m, z0.s, z4.s, #90
+ FCADD Z0.S, P0/M, Z0.S, Z4.S, #90
+ fcadd z0.s, p0/m, z0.s, z31.s, #90
+ FCADD Z0.S, P0/M, Z0.S, Z31.S, #90
+ fcadd z0.s, p0/m, z0.s, z0.s, #270
+ FCADD Z0.S, P0/M, Z0.S, Z0.S, #270
+ fcadd z0.d, p0/m, z0.d, z0.d, #90
+ FCADD Z0.D, P0/M, Z0.D, Z0.D, #90
+ fcadd z1.d, p0/m, z1.d, z0.d, #90
+ FCADD Z1.D, P0/M, Z1.D, Z0.D, #90
+ fcadd z31.d, p0/m, z31.d, z0.d, #90
+ FCADD Z31.D, P0/M, Z31.D, Z0.D, #90
+ fcadd z0.d, p2/m, z0.d, z0.d, #90
+ FCADD Z0.D, P2/M, Z0.D, Z0.D, #90
+ fcadd z0.d, p7/m, z0.d, z0.d, #90
+ FCADD Z0.D, P7/M, Z0.D, Z0.D, #90
+ fcadd z3.d, p0/m, z3.d, z0.d, #90
+ FCADD Z3.D, P0/M, Z3.D, Z0.D, #90
+ fcadd z0.d, p0/m, z0.d, z4.d, #90
+ FCADD Z0.D, P0/M, Z0.D, Z4.D, #90
+ fcadd z0.d, p0/m, z0.d, z31.d, #90
+ FCADD Z0.D, P0/M, Z0.D, Z31.D, #90
+ fcadd z0.d, p0/m, z0.d, z0.d, #270
+ FCADD Z0.D, P0/M, Z0.D, Z0.D, #270
+ fcmla z0.h, p0/m, z0.h, z0.h, #0
+ FCMLA Z0.H, P0/M, Z0.H, Z0.H, #0
+ fcmla z1.h, p0/m, z0.h, z0.h, #0
+ FCMLA Z1.H, P0/M, Z0.H, Z0.H, #0
+ fcmla z31.h, p0/m, z0.h, z0.h, #0
+ FCMLA Z31.H, P0/M, Z0.H, Z0.H, #0
+ fcmla z0.h, p2/m, z0.h, z0.h, #0
+ FCMLA Z0.H, P2/M, Z0.H, Z0.H, #0
+ fcmla z0.h, p7/m, z0.h, z0.h, #0
+ FCMLA Z0.H, P7/M, Z0.H, Z0.H, #0
+ fcmla z0.h, p0/m, z3.h, z0.h, #0
+ FCMLA Z0.H, P0/M, Z3.H, Z0.H, #0
+ fcmla z0.h, p0/m, z31.h, z0.h, #0
+ FCMLA Z0.H, P0/M, Z31.H, Z0.H, #0
+ fcmla z0.h, p0/m, z0.h, z4.h, #0
+ FCMLA Z0.H, P0/M, Z0.H, Z4.H, #0
+ fcmla z0.h, p0/m, z0.h, z31.h, #0
+ FCMLA Z0.H, P0/M, Z0.H, Z31.H, #0
+ fcmla z0.h, p0/m, z0.h, z0.h, #90
+ FCMLA Z0.H, P0/M, Z0.H, Z0.H, #90
+ fcmla z0.h, p0/m, z0.h, z0.h, #180
+ FCMLA Z0.H, P0/M, Z0.H, Z0.H, #180
+ fcmla z0.h, p0/m, z0.h, z0.h, #270
+ FCMLA Z0.H, P0/M, Z0.H, Z0.H, #270
+ fcmla z0.s, p0/m, z0.s, z0.s, #0
+ FCMLA Z0.S, P0/M, Z0.S, Z0.S, #0
+ fcmla z1.s, p0/m, z0.s, z0.s, #0
+ FCMLA Z1.S, P0/M, Z0.S, Z0.S, #0
+ fcmla z31.s, p0/m, z0.s, z0.s, #0
+ FCMLA Z31.S, P0/M, Z0.S, Z0.S, #0
+ fcmla z0.s, p2/m, z0.s, z0.s, #0
+ FCMLA Z0.S, P2/M, Z0.S, Z0.S, #0
+ fcmla z0.s, p7/m, z0.s, z0.s, #0
+ FCMLA Z0.S, P7/M, Z0.S, Z0.S, #0
+ fcmla z0.s, p0/m, z3.s, z0.s, #0
+ FCMLA Z0.S, P0/M, Z3.S, Z0.S, #0
+ fcmla z0.s, p0/m, z31.s, z0.s, #0
+ FCMLA Z0.S, P0/M, Z31.S, Z0.S, #0
+ fcmla z0.s, p0/m, z0.s, z4.s, #0
+ FCMLA Z0.S, P0/M, Z0.S, Z4.S, #0
+ fcmla z0.s, p0/m, z0.s, z31.s, #0
+ FCMLA Z0.S, P0/M, Z0.S, Z31.S, #0
+ fcmla z0.s, p0/m, z0.s, z0.s, #90
+ FCMLA Z0.S, P0/M, Z0.S, Z0.S, #90
+ fcmla z0.s, p0/m, z0.s, z0.s, #180
+ FCMLA Z0.S, P0/M, Z0.S, Z0.S, #180
+ fcmla z0.s, p0/m, z0.s, z0.s, #270
+ FCMLA Z0.S, P0/M, Z0.S, Z0.S, #270
+ fcmla z0.d, p0/m, z0.d, z0.d, #0
+ FCMLA Z0.D, P0/M, Z0.D, Z0.D, #0
+ fcmla z1.d, p0/m, z0.d, z0.d, #0
+ FCMLA Z1.D, P0/M, Z0.D, Z0.D, #0
+ fcmla z31.d, p0/m, z0.d, z0.d, #0
+ FCMLA Z31.D, P0/M, Z0.D, Z0.D, #0
+ fcmla z0.d, p2/m, z0.d, z0.d, #0
+ FCMLA Z0.D, P2/M, Z0.D, Z0.D, #0
+ fcmla z0.d, p7/m, z0.d, z0.d, #0
+ FCMLA Z0.D, P7/M, Z0.D, Z0.D, #0
+ fcmla z0.d, p0/m, z3.d, z0.d, #0
+ FCMLA Z0.D, P0/M, Z3.D, Z0.D, #0
+ fcmla z0.d, p0/m, z31.d, z0.d, #0
+ FCMLA Z0.D, P0/M, Z31.D, Z0.D, #0
+ fcmla z0.d, p0/m, z0.d, z4.d, #0
+ FCMLA Z0.D, P0/M, Z0.D, Z4.D, #0
+ fcmla z0.d, p0/m, z0.d, z31.d, #0
+ FCMLA Z0.D, P0/M, Z0.D, Z31.D, #0
+ fcmla z0.d, p0/m, z0.d, z0.d, #90
+ FCMLA Z0.D, P0/M, Z0.D, Z0.D, #90
+ fcmla z0.d, p0/m, z0.d, z0.d, #180
+ FCMLA Z0.D, P0/M, Z0.D, Z0.D, #180
+ fcmla z0.d, p0/m, z0.d, z0.d, #270
+ FCMLA Z0.D, P0/M, Z0.D, Z0.D, #270
+ fcmla z0.h, z0.h, z0.h[0], #0
+ FCMLA Z0.H, Z0.H, Z0.H[0], #0
+ fcmla z1.h, z0.h, z0.h[0], #0
+ FCMLA Z1.H, Z0.H, Z0.H[0], #0
+ fcmla z31.h, z0.h, z0.h[0], #0
+ FCMLA Z31.H, Z0.H, Z0.H[0], #0
+ fcmla z0.h, z2.h, z0.h[0], #0
+ FCMLA Z0.H, Z2.H, Z0.H[0], #0
+ fcmla z0.h, z31.h, z0.h[0], #0
+ FCMLA Z0.H, Z31.H, Z0.H[0], #0
+ fcmla z0.h, z0.h, z3.h[0], #0
+ FCMLA Z0.H, Z0.H, Z3.H[0], #0
+ fcmla z0.h, z0.h, z7.h[0], #0
+ FCMLA Z0.H, Z0.H, Z7.H[0], #0
+ fcmla z0.h, z0.h, z0.h[1], #0
+ FCMLA Z0.H, Z0.H, Z0.H[1], #0
+ fcmla z0.h, z0.h, z5.h[1], #0
+ FCMLA Z0.H, Z0.H, Z5.H[1], #0
+ fcmla z0.h, z0.h, z0.h[2], #0
+ FCMLA Z0.H, Z0.H, Z0.H[2], #0
+ fcmla z0.h, z0.h, z3.h[2], #0
+ FCMLA Z0.H, Z0.H, Z3.H[2], #0
+ fcmla z0.h, z0.h, z0.h[3], #0
+ FCMLA Z0.H, Z0.H, Z0.H[3], #0
+ fcmla z0.h, z0.h, z6.h[3], #0
+ FCMLA Z0.H, Z0.H, Z6.H[3], #0
+ fcmla z0.h, z0.h, z0.h[0], #90
+ FCMLA Z0.H, Z0.H, Z0.H[0], #90
+ fcmla z0.h, z0.h, z0.h[0], #180
+ FCMLA Z0.H, Z0.H, Z0.H[0], #180
+ fcmla z0.h, z0.h, z0.h[0], #270
+ FCMLA Z0.H, Z0.H, Z0.H[0], #270
+ fcmla z0.s, z0.s, z0.s[0], #0
+ FCMLA Z0.S, Z0.S, Z0.S[0], #0
+ fcmla z1.s, z0.s, z0.s[0], #0
+ FCMLA Z1.S, Z0.S, Z0.S[0], #0
+ fcmla z31.s, z0.s, z0.s[0], #0
+ FCMLA Z31.S, Z0.S, Z0.S[0], #0
+ fcmla z0.s, z2.s, z0.s[0], #0
+ FCMLA Z0.S, Z2.S, Z0.S[0], #0
+ fcmla z0.s, z31.s, z0.s[0], #0
+ FCMLA Z0.S, Z31.S, Z0.S[0], #0
+ fcmla z0.s, z0.s, z3.s[0], #0
+ FCMLA Z0.S, Z0.S, Z3.S[0], #0
+ fcmla z0.s, z0.s, z15.s[0], #0
+ FCMLA Z0.S, Z0.S, Z15.S[0], #0
+ fcmla z0.s, z0.s, z0.s[1], #0
+ FCMLA Z0.S, Z0.S, Z0.S[1], #0
+ fcmla z0.s, z0.s, z11.s[1], #0
+ FCMLA Z0.S, Z0.S, Z11.S[1], #0
+ fcmla z0.s, z0.s, z0.s[0], #90
+ FCMLA Z0.S, Z0.S, Z0.S[0], #90
+ fcmla z0.s, z0.s, z0.s[0], #180
+ FCMLA Z0.S, Z0.S, Z0.S[0], #180
+ fcmla z0.s, z0.s, z0.s[0], #270
+ FCMLA Z0.S, Z0.S, Z0.S[0], #270
+ fcmeq p0.h, p0/z, z0.h, #0.0
+ FCMEQ P0.H, P0/Z, Z0.H, #0.0
+ fcmeq p1.h, p0/z, z0.h, #0.0
+ FCMEQ P1.H, P0/Z, Z0.H, #0.0
+ fcmeq p15.h, p0/z, z0.h, #0.0
+ FCMEQ P15.H, P0/Z, Z0.H, #0.0
+ fcmeq p0.h, p2/z, z0.h, #0.0
+ FCMEQ P0.H, P2/Z, Z0.H, #0.0
+ fcmeq p0.h, p7/z, z0.h, #0.0
+ FCMEQ P0.H, P7/Z, Z0.H, #0.0
+ fcmeq p0.h, p0/z, z3.h, #0.0
+ FCMEQ P0.H, P0/Z, Z3.H, #0.0
+ fcmeq p0.h, p0/z, z31.h, #0.0
+ FCMEQ P0.H, P0/Z, Z31.H, #0.0
fcmeq p0.s, p0/z, z0.s, #0.0
FCMEQ P0.S, P0/Z, Z0.S, #0.0
fcmeq p1.s, p0/z, z0.s, #0.0
@@ -8437,6 +8869,24 @@
FCMEQ P0.D, P0/Z, Z3.D, #0.0
fcmeq p0.d, p0/z, z31.d, #0.0
FCMEQ P0.D, P0/Z, Z31.D, #0.0
+ fcmeq p0.h, p0/z, z0.h, z0.h
+ FCMEQ P0.H, P0/Z, Z0.H, Z0.H
+ fcmeq p1.h, p0/z, z0.h, z0.h
+ FCMEQ P1.H, P0/Z, Z0.H, Z0.H
+ fcmeq p15.h, p0/z, z0.h, z0.h
+ FCMEQ P15.H, P0/Z, Z0.H, Z0.H
+ fcmeq p0.h, p2/z, z0.h, z0.h
+ FCMEQ P0.H, P2/Z, Z0.H, Z0.H
+ fcmeq p0.h, p7/z, z0.h, z0.h
+ FCMEQ P0.H, P7/Z, Z0.H, Z0.H
+ fcmeq p0.h, p0/z, z3.h, z0.h
+ FCMEQ P0.H, P0/Z, Z3.H, Z0.H
+ fcmeq p0.h, p0/z, z31.h, z0.h
+ FCMEQ P0.H, P0/Z, Z31.H, Z0.H
+ fcmeq p0.h, p0/z, z0.h, z4.h
+ FCMEQ P0.H, P0/Z, Z0.H, Z4.H
+ fcmeq p0.h, p0/z, z0.h, z31.h
+ FCMEQ P0.H, P0/Z, Z0.H, Z31.H
fcmeq p0.s, p0/z, z0.s, z0.s
FCMEQ P0.S, P0/Z, Z0.S, Z0.S
fcmeq p1.s, p0/z, z0.s, z0.s
@@ -8473,6 +8923,20 @@
FCMEQ P0.D, P0/Z, Z0.D, Z4.D
fcmeq p0.d, p0/z, z0.d, z31.d
FCMEQ P0.D, P0/Z, Z0.D, Z31.D
+ fcmge p0.h, p0/z, z0.h, #0.0
+ FCMGE P0.H, P0/Z, Z0.H, #0.0
+ fcmge p1.h, p0/z, z0.h, #0.0
+ FCMGE P1.H, P0/Z, Z0.H, #0.0
+ fcmge p15.h, p0/z, z0.h, #0.0
+ FCMGE P15.H, P0/Z, Z0.H, #0.0
+ fcmge p0.h, p2/z, z0.h, #0.0
+ FCMGE P0.H, P2/Z, Z0.H, #0.0
+ fcmge p0.h, p7/z, z0.h, #0.0
+ FCMGE P0.H, P7/Z, Z0.H, #0.0
+ fcmge p0.h, p0/z, z3.h, #0.0
+ FCMGE P0.H, P0/Z, Z3.H, #0.0
+ fcmge p0.h, p0/z, z31.h, #0.0
+ FCMGE P0.H, P0/Z, Z31.H, #0.0
fcmge p0.s, p0/z, z0.s, #0.0
FCMGE P0.S, P0/Z, Z0.S, #0.0
fcmge p1.s, p0/z, z0.s, #0.0
@@ -8501,6 +8965,24 @@
FCMGE P0.D, P0/Z, Z3.D, #0.0
fcmge p0.d, p0/z, z31.d, #0.0
FCMGE P0.D, P0/Z, Z31.D, #0.0
+ fcmge p0.h, p0/z, z0.h, z0.h
+ FCMGE P0.H, P0/Z, Z0.H, Z0.H
+ fcmge p1.h, p0/z, z0.h, z0.h
+ FCMGE P1.H, P0/Z, Z0.H, Z0.H
+ fcmge p15.h, p0/z, z0.h, z0.h
+ FCMGE P15.H, P0/Z, Z0.H, Z0.H
+ fcmge p0.h, p2/z, z0.h, z0.h
+ FCMGE P0.H, P2/Z, Z0.H, Z0.H
+ fcmge p0.h, p7/z, z0.h, z0.h
+ FCMGE P0.H, P7/Z, Z0.H, Z0.H
+ fcmge p0.h, p0/z, z3.h, z0.h
+ FCMGE P0.H, P0/Z, Z3.H, Z0.H
+ fcmge p0.h, p0/z, z31.h, z0.h
+ FCMGE P0.H, P0/Z, Z31.H, Z0.H
+ fcmge p0.h, p0/z, z0.h, z4.h
+ FCMGE P0.H, P0/Z, Z0.H, Z4.H
+ fcmge p0.h, p0/z, z0.h, z31.h
+ FCMGE P0.H, P0/Z, Z0.H, Z31.H
fcmge p0.s, p0/z, z0.s, z0.s
FCMGE P0.S, P0/Z, Z0.S, Z0.S
fcmge p1.s, p0/z, z0.s, z0.s
@@ -8537,6 +9019,20 @@
FCMGE P0.D, P0/Z, Z0.D, Z4.D
fcmge p0.d, p0/z, z0.d, z31.d
FCMGE P0.D, P0/Z, Z0.D, Z31.D
+ fcmgt p0.h, p0/z, z0.h, #0.0
+ FCMGT P0.H, P0/Z, Z0.H, #0.0
+ fcmgt p1.h, p0/z, z0.h, #0.0
+ FCMGT P1.H, P0/Z, Z0.H, #0.0
+ fcmgt p15.h, p0/z, z0.h, #0.0
+ FCMGT P15.H, P0/Z, Z0.H, #0.0
+ fcmgt p0.h, p2/z, z0.h, #0.0
+ FCMGT P0.H, P2/Z, Z0.H, #0.0
+ fcmgt p0.h, p7/z, z0.h, #0.0
+ FCMGT P0.H, P7/Z, Z0.H, #0.0
+ fcmgt p0.h, p0/z, z3.h, #0.0
+ FCMGT P0.H, P0/Z, Z3.H, #0.0
+ fcmgt p0.h, p0/z, z31.h, #0.0
+ FCMGT P0.H, P0/Z, Z31.H, #0.0
fcmgt p0.s, p0/z, z0.s, #0.0
FCMGT P0.S, P0/Z, Z0.S, #0.0
fcmgt p1.s, p0/z, z0.s, #0.0
@@ -8565,6 +9061,24 @@
FCMGT P0.D, P0/Z, Z3.D, #0.0
fcmgt p0.d, p0/z, z31.d, #0.0
FCMGT P0.D, P0/Z, Z31.D, #0.0
+ fcmgt p0.h, p0/z, z0.h, z0.h
+ FCMGT P0.H, P0/Z, Z0.H, Z0.H
+ fcmgt p1.h, p0/z, z0.h, z0.h
+ FCMGT P1.H, P0/Z, Z0.H, Z0.H
+ fcmgt p15.h, p0/z, z0.h, z0.h
+ FCMGT P15.H, P0/Z, Z0.H, Z0.H
+ fcmgt p0.h, p2/z, z0.h, z0.h
+ FCMGT P0.H, P2/Z, Z0.H, Z0.H
+ fcmgt p0.h, p7/z, z0.h, z0.h
+ FCMGT P0.H, P7/Z, Z0.H, Z0.H
+ fcmgt p0.h, p0/z, z3.h, z0.h
+ FCMGT P0.H, P0/Z, Z3.H, Z0.H
+ fcmgt p0.h, p0/z, z31.h, z0.h
+ FCMGT P0.H, P0/Z, Z31.H, Z0.H
+ fcmgt p0.h, p0/z, z0.h, z4.h
+ FCMGT P0.H, P0/Z, Z0.H, Z4.H
+ fcmgt p0.h, p0/z, z0.h, z31.h
+ FCMGT P0.H, P0/Z, Z0.H, Z31.H
fcmgt p0.s, p0/z, z0.s, z0.s
FCMGT P0.S, P0/Z, Z0.S, Z0.S
fcmgt p1.s, p0/z, z0.s, z0.s
@@ -8601,6 +9115,20 @@
FCMGT P0.D, P0/Z, Z0.D, Z4.D
fcmgt p0.d, p0/z, z0.d, z31.d
FCMGT P0.D, P0/Z, Z0.D, Z31.D
+ fcmle p0.h, p0/z, z0.h, #0.0
+ FCMLE P0.H, P0/Z, Z0.H, #0.0
+ fcmle p1.h, p0/z, z0.h, #0.0
+ FCMLE P1.H, P0/Z, Z0.H, #0.0
+ fcmle p15.h, p0/z, z0.h, #0.0
+ FCMLE P15.H, P0/Z, Z0.H, #0.0
+ fcmle p0.h, p2/z, z0.h, #0.0
+ FCMLE P0.H, P2/Z, Z0.H, #0.0
+ fcmle p0.h, p7/z, z0.h, #0.0
+ FCMLE P0.H, P7/Z, Z0.H, #0.0
+ fcmle p0.h, p0/z, z3.h, #0.0
+ FCMLE P0.H, P0/Z, Z3.H, #0.0
+ fcmle p0.h, p0/z, z31.h, #0.0
+ FCMLE P0.H, P0/Z, Z31.H, #0.0
fcmle p0.s, p0/z, z0.s, #0.0
FCMLE P0.S, P0/Z, Z0.S, #0.0
fcmle p1.s, p0/z, z0.s, #0.0
@@ -8629,6 +9157,20 @@
FCMLE P0.D, P0/Z, Z3.D, #0.0
fcmle p0.d, p0/z, z31.d, #0.0
FCMLE P0.D, P0/Z, Z31.D, #0.0
+ fcmlt p0.h, p0/z, z0.h, #0.0
+ FCMLT P0.H, P0/Z, Z0.H, #0.0
+ fcmlt p1.h, p0/z, z0.h, #0.0
+ FCMLT P1.H, P0/Z, Z0.H, #0.0
+ fcmlt p15.h, p0/z, z0.h, #0.0
+ FCMLT P15.H, P0/Z, Z0.H, #0.0
+ fcmlt p0.h, p2/z, z0.h, #0.0
+ FCMLT P0.H, P2/Z, Z0.H, #0.0
+ fcmlt p0.h, p7/z, z0.h, #0.0
+ FCMLT P0.H, P7/Z, Z0.H, #0.0
+ fcmlt p0.h, p0/z, z3.h, #0.0
+ FCMLT P0.H, P0/Z, Z3.H, #0.0
+ fcmlt p0.h, p0/z, z31.h, #0.0
+ FCMLT P0.H, P0/Z, Z31.H, #0.0
fcmlt p0.s, p0/z, z0.s, #0.0
FCMLT P0.S, P0/Z, Z0.S, #0.0
fcmlt p1.s, p0/z, z0.s, #0.0
@@ -8657,6 +9199,20 @@
FCMLT P0.D, P0/Z, Z3.D, #0.0
fcmlt p0.d, p0/z, z31.d, #0.0
FCMLT P0.D, P0/Z, Z31.D, #0.0
+ fcmne p0.h, p0/z, z0.h, #0.0
+ FCMNE P0.H, P0/Z, Z0.H, #0.0
+ fcmne p1.h, p0/z, z0.h, #0.0
+ FCMNE P1.H, P0/Z, Z0.H, #0.0
+ fcmne p15.h, p0/z, z0.h, #0.0
+ FCMNE P15.H, P0/Z, Z0.H, #0.0
+ fcmne p0.h, p2/z, z0.h, #0.0
+ FCMNE P0.H, P2/Z, Z0.H, #0.0
+ fcmne p0.h, p7/z, z0.h, #0.0
+ FCMNE P0.H, P7/Z, Z0.H, #0.0
+ fcmne p0.h, p0/z, z3.h, #0.0
+ FCMNE P0.H, P0/Z, Z3.H, #0.0
+ fcmne p0.h, p0/z, z31.h, #0.0
+ FCMNE P0.H, P0/Z, Z31.H, #0.0
fcmne p0.s, p0/z, z0.s, #0.0
FCMNE P0.S, P0/Z, Z0.S, #0.0
fcmne p1.s, p0/z, z0.s, #0.0
@@ -8685,6 +9241,24 @@
FCMNE P0.D, P0/Z, Z3.D, #0.0
fcmne p0.d, p0/z, z31.d, #0.0
FCMNE P0.D, P0/Z, Z31.D, #0.0
+ fcmne p0.h, p0/z, z0.h, z0.h
+ FCMNE P0.H, P0/Z, Z0.H, Z0.H
+ fcmne p1.h, p0/z, z0.h, z0.h
+ FCMNE P1.H, P0/Z, Z0.H, Z0.H
+ fcmne p15.h, p0/z, z0.h, z0.h
+ FCMNE P15.H, P0/Z, Z0.H, Z0.H
+ fcmne p0.h, p2/z, z0.h, z0.h
+ FCMNE P0.H, P2/Z, Z0.H, Z0.H
+ fcmne p0.h, p7/z, z0.h, z0.h
+ FCMNE P0.H, P7/Z, Z0.H, Z0.H
+ fcmne p0.h, p0/z, z3.h, z0.h
+ FCMNE P0.H, P0/Z, Z3.H, Z0.H
+ fcmne p0.h, p0/z, z31.h, z0.h
+ FCMNE P0.H, P0/Z, Z31.H, Z0.H
+ fcmne p0.h, p0/z, z0.h, z4.h
+ FCMNE P0.H, P0/Z, Z0.H, Z4.H
+ fcmne p0.h, p0/z, z0.h, z31.h
+ FCMNE P0.H, P0/Z, Z0.H, Z31.H
fcmne p0.s, p0/z, z0.s, z0.s
FCMNE P0.S, P0/Z, Z0.S, Z0.S
fcmne p1.s, p0/z, z0.s, z0.s
@@ -8721,6 +9295,24 @@
FCMNE P0.D, P0/Z, Z0.D, Z4.D
fcmne p0.d, p0/z, z0.d, z31.d
FCMNE P0.D, P0/Z, Z0.D, Z31.D
+ fcmuo p0.h, p0/z, z0.h, z0.h
+ FCMUO P0.H, P0/Z, Z0.H, Z0.H
+ fcmuo p1.h, p0/z, z0.h, z0.h
+ FCMUO P1.H, P0/Z, Z0.H, Z0.H
+ fcmuo p15.h, p0/z, z0.h, z0.h
+ FCMUO P15.H, P0/Z, Z0.H, Z0.H
+ fcmuo p0.h, p2/z, z0.h, z0.h
+ FCMUO P0.H, P2/Z, Z0.H, Z0.H
+ fcmuo p0.h, p7/z, z0.h, z0.h
+ FCMUO P0.H, P7/Z, Z0.H, Z0.H
+ fcmuo p0.h, p0/z, z3.h, z0.h
+ FCMUO P0.H, P0/Z, Z3.H, Z0.H
+ fcmuo p0.h, p0/z, z31.h, z0.h
+ FCMUO P0.H, P0/Z, Z31.H, Z0.H
+ fcmuo p0.h, p0/z, z0.h, z4.h
+ FCMUO P0.H, P0/Z, Z0.H, Z4.H
+ fcmuo p0.h, p0/z, z0.h, z31.h
+ FCMUO P0.H, P0/Z, Z0.H, Z31.H
fcmuo p0.s, p0/z, z0.s, z0.s
FCMUO P0.S, P0/Z, Z0.S, Z0.S
fcmuo p1.s, p0/z, z0.s, z0.s
@@ -8757,6 +9349,28 @@
FCMUO P0.D, P0/Z, Z0.D, Z4.D
fcmuo p0.d, p0/z, z0.d, z31.d
FCMUO P0.D, P0/Z, Z0.D, Z31.D
+ fcpy z0.h, p0/m, #2.0000000000
+ FCPY Z0.H, P0/M, #2.0000000000
+ fcpy z1.h, p0/m, #2.0000000000
+ FCPY Z1.H, P0/M, #2.0000000000
+ fcpy z31.h, p0/m, #2.0000000000
+ FCPY Z31.H, P0/M, #2.0000000000
+ fcpy z0.h, p2/m, #2.0000000000
+ FCPY Z0.H, P2/M, #2.0000000000
+ fcpy z0.h, p15/m, #2.0000000000
+ FCPY Z0.H, P15/M, #2.0000000000
+ fcpy z0.h, p0/m, #16.0000000000
+ FCPY Z0.H, P0/M, #16.0000000000
+ fcpy z0.h, p0/m, #0.1875000000
+ FCPY Z0.H, P0/M, #0.1875000000
+ fcpy z0.h, p0/m, #1.9375000000
+ FCPY Z0.H, P0/M, #1.9375000000
+ fcpy z0.h, p0/m, #-3.0000000000
+ FCPY Z0.H, P0/M, #-3.0000000000
+ fcpy z0.h, p0/m, #-0.1250000000
+ FCPY Z0.H, P0/M, #-0.1250000000
+ fcpy z0.h, p0/m, #-1.9375000000
+ FCPY Z0.H, P0/M, #-1.9375000000
fcpy z0.s, p0/m, #2.0000000000
FCPY Z0.S, P0/M, #2.0000000000
fcpy z1.s, p0/m, #2.0000000000
@@ -8885,6 +9499,48 @@
FCVT Z0.D, P0/M, Z3.S
fcvt z0.d, p0/m, z31.s
FCVT Z0.D, P0/M, Z31.S
+ fcvtzs z0.h, p0/m, z0.h
+ FCVTZS Z0.H, P0/M, Z0.H
+ fcvtzs z1.h, p0/m, z0.h
+ FCVTZS Z1.H, P0/M, Z0.H
+ fcvtzs z31.h, p0/m, z0.h
+ FCVTZS Z31.H, P0/M, Z0.H
+ fcvtzs z0.h, p2/m, z0.h
+ FCVTZS Z0.H, P2/M, Z0.H
+ fcvtzs z0.h, p7/m, z0.h
+ FCVTZS Z0.H, P7/M, Z0.H
+ fcvtzs z0.h, p0/m, z3.h
+ FCVTZS Z0.H, P0/M, Z3.H
+ fcvtzs z0.h, p0/m, z31.h
+ FCVTZS Z0.H, P0/M, Z31.H
+ fcvtzs z0.s, p0/m, z0.h
+ FCVTZS Z0.S, P0/M, Z0.H
+ fcvtzs z1.s, p0/m, z0.h
+ FCVTZS Z1.S, P0/M, Z0.H
+ fcvtzs z31.s, p0/m, z0.h
+ FCVTZS Z31.S, P0/M, Z0.H
+ fcvtzs z0.s, p2/m, z0.h
+ FCVTZS Z0.S, P2/M, Z0.H
+ fcvtzs z0.s, p7/m, z0.h
+ FCVTZS Z0.S, P7/M, Z0.H
+ fcvtzs z0.s, p0/m, z3.h
+ FCVTZS Z0.S, P0/M, Z3.H
+ fcvtzs z0.s, p0/m, z31.h
+ FCVTZS Z0.S, P0/M, Z31.H
+ fcvtzs z0.d, p0/m, z0.h
+ FCVTZS Z0.D, P0/M, Z0.H
+ fcvtzs z1.d, p0/m, z0.h
+ FCVTZS Z1.D, P0/M, Z0.H
+ fcvtzs z31.d, p0/m, z0.h
+ FCVTZS Z31.D, P0/M, Z0.H
+ fcvtzs z0.d, p2/m, z0.h
+ FCVTZS Z0.D, P2/M, Z0.H
+ fcvtzs z0.d, p7/m, z0.h
+ FCVTZS Z0.D, P7/M, Z0.H
+ fcvtzs z0.d, p0/m, z3.h
+ FCVTZS Z0.D, P0/M, Z3.H
+ fcvtzs z0.d, p0/m, z31.h
+ FCVTZS Z0.D, P0/M, Z31.H
fcvtzs z0.s, p0/m, z0.s
FCVTZS Z0.S, P0/M, Z0.S
fcvtzs z1.s, p0/m, z0.s
@@ -8941,6 +9597,48 @@
FCVTZS Z0.D, P0/M, Z3.D
fcvtzs z0.d, p0/m, z31.d
FCVTZS Z0.D, P0/M, Z31.D
+ fcvtzu z0.h, p0/m, z0.h
+ FCVTZU Z0.H, P0/M, Z0.H
+ fcvtzu z1.h, p0/m, z0.h
+ FCVTZU Z1.H, P0/M, Z0.H
+ fcvtzu z31.h, p0/m, z0.h
+ FCVTZU Z31.H, P0/M, Z0.H
+ fcvtzu z0.h, p2/m, z0.h
+ FCVTZU Z0.H, P2/M, Z0.H
+ fcvtzu z0.h, p7/m, z0.h
+ FCVTZU Z0.H, P7/M, Z0.H
+ fcvtzu z0.h, p0/m, z3.h
+ FCVTZU Z0.H, P0/M, Z3.H
+ fcvtzu z0.h, p0/m, z31.h
+ FCVTZU Z0.H, P0/M, Z31.H
+ fcvtzu z0.s, p0/m, z0.h
+ FCVTZU Z0.S, P0/M, Z0.H
+ fcvtzu z1.s, p0/m, z0.h
+ FCVTZU Z1.S, P0/M, Z0.H
+ fcvtzu z31.s, p0/m, z0.h
+ FCVTZU Z31.S, P0/M, Z0.H
+ fcvtzu z0.s, p2/m, z0.h
+ FCVTZU Z0.S, P2/M, Z0.H
+ fcvtzu z0.s, p7/m, z0.h
+ FCVTZU Z0.S, P7/M, Z0.H
+ fcvtzu z0.s, p0/m, z3.h
+ FCVTZU Z0.S, P0/M, Z3.H
+ fcvtzu z0.s, p0/m, z31.h
+ FCVTZU Z0.S, P0/M, Z31.H
+ fcvtzu z0.d, p0/m, z0.h
+ FCVTZU Z0.D, P0/M, Z0.H
+ fcvtzu z1.d, p0/m, z0.h
+ FCVTZU Z1.D, P0/M, Z0.H
+ fcvtzu z31.d, p0/m, z0.h
+ FCVTZU Z31.D, P0/M, Z0.H
+ fcvtzu z0.d, p2/m, z0.h
+ FCVTZU Z0.D, P2/M, Z0.H
+ fcvtzu z0.d, p7/m, z0.h
+ FCVTZU Z0.D, P7/M, Z0.H
+ fcvtzu z0.d, p0/m, z3.h
+ FCVTZU Z0.D, P0/M, Z3.H
+ fcvtzu z0.d, p0/m, z31.h
+ FCVTZU Z0.D, P0/M, Z31.H
fcvtzu z0.s, p0/m, z0.s
FCVTZU Z0.S, P0/M, Z0.S
fcvtzu z1.s, p0/m, z0.s
@@ -8997,6 +9695,22 @@
FCVTZU Z0.D, P0/M, Z3.D
fcvtzu z0.d, p0/m, z31.d
FCVTZU Z0.D, P0/M, Z31.D
+ fdiv z0.h, p0/m, z0.h, z0.h
+ FDIV Z0.H, P0/M, Z0.H, Z0.H
+ fdiv z1.h, p0/m, z1.h, z0.h
+ FDIV Z1.H, P0/M, Z1.H, Z0.H
+ fdiv z31.h, p0/m, z31.h, z0.h
+ FDIV Z31.H, P0/M, Z31.H, Z0.H
+ fdiv z0.h, p2/m, z0.h, z0.h
+ FDIV Z0.H, P2/M, Z0.H, Z0.H
+ fdiv z0.h, p7/m, z0.h, z0.h
+ FDIV Z0.H, P7/M, Z0.H, Z0.H
+ fdiv z3.h, p0/m, z3.h, z0.h
+ FDIV Z3.H, P0/M, Z3.H, Z0.H
+ fdiv z0.h, p0/m, z0.h, z4.h
+ FDIV Z0.H, P0/M, Z0.H, Z4.H
+ fdiv z0.h, p0/m, z0.h, z31.h
+ FDIV Z0.H, P0/M, Z0.H, Z31.H
fdiv z0.s, p0/m, z0.s, z0.s
FDIV Z0.S, P0/M, Z0.S, Z0.S
fdiv z1.s, p0/m, z1.s, z0.s
@@ -9029,6 +9743,22 @@
FDIV Z0.D, P0/M, Z0.D, Z4.D
fdiv z0.d, p0/m, z0.d, z31.d
FDIV Z0.D, P0/M, Z0.D, Z31.D
+ fdivr z0.h, p0/m, z0.h, z0.h
+ FDIVR Z0.H, P0/M, Z0.H, Z0.H
+ fdivr z1.h, p0/m, z1.h, z0.h
+ FDIVR Z1.H, P0/M, Z1.H, Z0.H
+ fdivr z31.h, p0/m, z31.h, z0.h
+ FDIVR Z31.H, P0/M, Z31.H, Z0.H
+ fdivr z0.h, p2/m, z0.h, z0.h
+ FDIVR Z0.H, P2/M, Z0.H, Z0.H
+ fdivr z0.h, p7/m, z0.h, z0.h
+ FDIVR Z0.H, P7/M, Z0.H, Z0.H
+ fdivr z3.h, p0/m, z3.h, z0.h
+ FDIVR Z3.H, P0/M, Z3.H, Z0.H
+ fdivr z0.h, p0/m, z0.h, z4.h
+ FDIVR Z0.H, P0/M, Z0.H, Z4.H
+ fdivr z0.h, p0/m, z0.h, z31.h
+ FDIVR Z0.H, P0/M, Z0.H, Z31.H
fdivr z0.s, p0/m, z0.s, z0.s
FDIVR Z0.S, P0/M, Z0.S, Z0.S
fdivr z1.s, p0/m, z1.s, z0.s
@@ -9061,6 +9791,24 @@
FDIVR Z0.D, P0/M, Z0.D, Z4.D
fdivr z0.d, p0/m, z0.d, z31.d
FDIVR Z0.D, P0/M, Z0.D, Z31.D
+ fdup z0.h, #2.0000000000
+ FDUP Z0.H, #2.0000000000
+ fdup z1.h, #2.0000000000
+ FDUP Z1.H, #2.0000000000
+ fdup z31.h, #2.0000000000
+ FDUP Z31.H, #2.0000000000
+ fdup z0.h, #16.0000000000
+ FDUP Z0.H, #16.0000000000
+ fdup z0.h, #0.1875000000
+ FDUP Z0.H, #0.1875000000
+ fdup z0.h, #1.9375000000
+ FDUP Z0.H, #1.9375000000
+ fdup z0.h, #-3.0000000000
+ FDUP Z0.H, #-3.0000000000
+ fdup z0.h, #-0.1250000000
+ FDUP Z0.H, #-0.1250000000
+ fdup z0.h, #-1.9375000000
+ FDUP Z0.H, #-1.9375000000
fdup z0.s, #2.0000000000
FDUP Z0.S, #2.0000000000
fdup z1.s, #2.0000000000
@@ -9097,6 +9845,16 @@
FDUP Z0.D, #-0.1250000000
fdup z0.d, #-1.9375000000
FDUP Z0.D, #-1.9375000000
+ fexpa z0.h, z0.h
+ FEXPA Z0.H, Z0.H
+ fexpa z1.h, z0.h
+ FEXPA Z1.H, Z0.H
+ fexpa z31.h, z0.h
+ FEXPA Z31.H, Z0.H
+ fexpa z0.h, z2.h
+ FEXPA Z0.H, Z2.H
+ fexpa z0.h, z31.h
+ FEXPA Z0.H, Z31.H
fexpa z0.s, z0.s
FEXPA Z0.S, Z0.S
fexpa z1.s, z0.s
@@ -9117,6 +9875,24 @@
FEXPA Z0.D, Z2.D
fexpa z0.d, z31.d
FEXPA Z0.D, Z31.D
+ fmad z0.h, p0/m, z0.h, z0.h
+ FMAD Z0.H, P0/M, Z0.H, Z0.H
+ fmad z1.h, p0/m, z0.h, z0.h
+ FMAD Z1.H, P0/M, Z0.H, Z0.H
+ fmad z31.h, p0/m, z0.h, z0.h
+ FMAD Z31.H, P0/M, Z0.H, Z0.H
+ fmad z0.h, p2/m, z0.h, z0.h
+ FMAD Z0.H, P2/M, Z0.H, Z0.H
+ fmad z0.h, p7/m, z0.h, z0.h
+ FMAD Z0.H, P7/M, Z0.H, Z0.H
+ fmad z0.h, p0/m, z3.h, z0.h
+ FMAD Z0.H, P0/M, Z3.H, Z0.H
+ fmad z0.h, p0/m, z31.h, z0.h
+ FMAD Z0.H, P0/M, Z31.H, Z0.H
+ fmad z0.h, p0/m, z0.h, z4.h
+ FMAD Z0.H, P0/M, Z0.H, Z4.H
+ fmad z0.h, p0/m, z0.h, z31.h
+ FMAD Z0.H, P0/M, Z0.H, Z31.H
fmad z0.s, p0/m, z0.s, z0.s
FMAD Z0.S, P0/M, Z0.S, Z0.S
fmad z1.s, p0/m, z0.s, z0.s
@@ -9153,6 +9929,22 @@
FMAD Z0.D, P0/M, Z0.D, Z4.D
fmad z0.d, p0/m, z0.d, z31.d
FMAD Z0.D, P0/M, Z0.D, Z31.D
+ fmax z0.h, p0/m, z0.h, z0.h
+ FMAX Z0.H, P0/M, Z0.H, Z0.H
+ fmax z1.h, p0/m, z1.h, z0.h
+ FMAX Z1.H, P0/M, Z1.H, Z0.H
+ fmax z31.h, p0/m, z31.h, z0.h
+ FMAX Z31.H, P0/M, Z31.H, Z0.H
+ fmax z0.h, p2/m, z0.h, z0.h
+ FMAX Z0.H, P2/M, Z0.H, Z0.H
+ fmax z0.h, p7/m, z0.h, z0.h
+ FMAX Z0.H, P7/M, Z0.H, Z0.H
+ fmax z3.h, p0/m, z3.h, z0.h
+ FMAX Z3.H, P0/M, Z3.H, Z0.H
+ fmax z0.h, p0/m, z0.h, z4.h
+ FMAX Z0.H, P0/M, Z0.H, Z4.H
+ fmax z0.h, p0/m, z0.h, z31.h
+ FMAX Z0.H, P0/M, Z0.H, Z31.H
fmax z0.s, p0/m, z0.s, z0.s
FMAX Z0.S, P0/M, Z0.S, Z0.S
fmax z1.s, p0/m, z1.s, z0.s
@@ -9185,6 +9977,34 @@
FMAX Z0.D, P0/M, Z0.D, Z4.D
fmax z0.d, p0/m, z0.d, z31.d
FMAX Z0.D, P0/M, Z0.D, Z31.D
+ fmax z0.h, p0/m, z0.h, #0.0
+ FMAX Z0.H, P0/M, Z0.H, #0.0
+ fmax z0.h, p0/m, z0.h, #0.00000
+ fmax z0.h, p0/m, z0.h, #0.0000000000e+00
+ fmax z1.h, p0/m, z1.h, #0.0
+ FMAX Z1.H, P0/M, Z1.H, #0.0
+ fmax z1.h, p0/m, z1.h, #0.00000
+ fmax z1.h, p0/m, z1.h, #0.0000000000e+00
+ fmax z31.h, p0/m, z31.h, #0.0
+ FMAX Z31.H, P0/M, Z31.H, #0.0
+ fmax z31.h, p0/m, z31.h, #0.00000
+ fmax z31.h, p0/m, z31.h, #0.0000000000e+00
+ fmax z0.h, p2/m, z0.h, #0.0
+ FMAX Z0.H, P2/M, Z0.H, #0.0
+ fmax z0.h, p2/m, z0.h, #0.00000
+ fmax z0.h, p2/m, z0.h, #0.0000000000e+00
+ fmax z0.h, p7/m, z0.h, #0.0
+ FMAX Z0.H, P7/M, Z0.H, #0.0
+ fmax z0.h, p7/m, z0.h, #0.00000
+ fmax z0.h, p7/m, z0.h, #0.0000000000e+00
+ fmax z3.h, p0/m, z3.h, #0.0
+ FMAX Z3.H, P0/M, Z3.H, #0.0
+ fmax z3.h, p0/m, z3.h, #0.00000
+ fmax z3.h, p0/m, z3.h, #0.0000000000e+00
+ fmax z0.h, p0/m, z0.h, #1.0
+ FMAX Z0.H, P0/M, Z0.H, #1.0
+ fmax z0.h, p0/m, z0.h, #1.00000
+ fmax z0.h, p0/m, z0.h, #1.0000000000e+00
fmax z0.s, p0/m, z0.s, #0.0
FMAX Z0.S, P0/M, Z0.S, #0.0
fmax z0.s, p0/m, z0.s, #0.00000
@@ -9241,6 +10061,22 @@
FMAX Z0.D, P0/M, Z0.D, #1.0
fmax z0.d, p0/m, z0.d, #1.00000
fmax z0.d, p0/m, z0.d, #1.0000000000e+00
+ fmaxnm z0.h, p0/m, z0.h, z0.h
+ FMAXNM Z0.H, P0/M, Z0.H, Z0.H
+ fmaxnm z1.h, p0/m, z1.h, z0.h
+ FMAXNM Z1.H, P0/M, Z1.H, Z0.H
+ fmaxnm z31.h, p0/m, z31.h, z0.h
+ FMAXNM Z31.H, P0/M, Z31.H, Z0.H
+ fmaxnm z0.h, p2/m, z0.h, z0.h
+ FMAXNM Z0.H, P2/M, Z0.H, Z0.H
+ fmaxnm z0.h, p7/m, z0.h, z0.h
+ FMAXNM Z0.H, P7/M, Z0.H, Z0.H
+ fmaxnm z3.h, p0/m, z3.h, z0.h
+ FMAXNM Z3.H, P0/M, Z3.H, Z0.H
+ fmaxnm z0.h, p0/m, z0.h, z4.h
+ FMAXNM Z0.H, P0/M, Z0.H, Z4.H
+ fmaxnm z0.h, p0/m, z0.h, z31.h
+ FMAXNM Z0.H, P0/M, Z0.H, Z31.H
fmaxnm z0.s, p0/m, z0.s, z0.s
FMAXNM Z0.S, P0/M, Z0.S, Z0.S
fmaxnm z1.s, p0/m, z1.s, z0.s
@@ -9273,6 +10109,34 @@
FMAXNM Z0.D, P0/M, Z0.D, Z4.D
fmaxnm z0.d, p0/m, z0.d, z31.d
FMAXNM Z0.D, P0/M, Z0.D, Z31.D
+ fmaxnm z0.h, p0/m, z0.h, #0.0
+ FMAXNM Z0.H, P0/M, Z0.H, #0.0
+ fmaxnm z0.h, p0/m, z0.h, #0.00000
+ fmaxnm z0.h, p0/m, z0.h, #0.0000000000e+00
+ fmaxnm z1.h, p0/m, z1.h, #0.0
+ FMAXNM Z1.H, P0/M, Z1.H, #0.0
+ fmaxnm z1.h, p0/m, z1.h, #0.00000
+ fmaxnm z1.h, p0/m, z1.h, #0.0000000000e+00
+ fmaxnm z31.h, p0/m, z31.h, #0.0
+ FMAXNM Z31.H, P0/M, Z31.H, #0.0
+ fmaxnm z31.h, p0/m, z31.h, #0.00000
+ fmaxnm z31.h, p0/m, z31.h, #0.0000000000e+00
+ fmaxnm z0.h, p2/m, z0.h, #0.0
+ FMAXNM Z0.H, P2/M, Z0.H, #0.0
+ fmaxnm z0.h, p2/m, z0.h, #0.00000
+ fmaxnm z0.h, p2/m, z0.h, #0.0000000000e+00
+ fmaxnm z0.h, p7/m, z0.h, #0.0
+ FMAXNM Z0.H, P7/M, Z0.H, #0.0
+ fmaxnm z0.h, p7/m, z0.h, #0.00000
+ fmaxnm z0.h, p7/m, z0.h, #0.0000000000e+00
+ fmaxnm z3.h, p0/m, z3.h, #0.0
+ FMAXNM Z3.H, P0/M, Z3.H, #0.0
+ fmaxnm z3.h, p0/m, z3.h, #0.00000
+ fmaxnm z3.h, p0/m, z3.h, #0.0000000000e+00
+ fmaxnm z0.h, p0/m, z0.h, #1.0
+ FMAXNM Z0.H, P0/M, Z0.H, #1.0
+ fmaxnm z0.h, p0/m, z0.h, #1.00000
+ fmaxnm z0.h, p0/m, z0.h, #1.0000000000e+00
fmaxnm z0.s, p0/m, z0.s, #0.0
FMAXNM Z0.S, P0/M, Z0.S, #0.0
fmaxnm z0.s, p0/m, z0.s, #0.00000
@@ -9329,6 +10193,20 @@
FMAXNM Z0.D, P0/M, Z0.D, #1.0
fmaxnm z0.d, p0/m, z0.d, #1.00000
fmaxnm z0.d, p0/m, z0.d, #1.0000000000e+00
+ fmaxnmv h0, p0, z0.h
+ FMAXNMV H0, P0, Z0.H
+ fmaxnmv h1, p0, z0.h
+ FMAXNMV H1, P0, Z0.H
+ fmaxnmv h31, p0, z0.h
+ FMAXNMV H31, P0, Z0.H
+ fmaxnmv h0, p2, z0.h
+ FMAXNMV H0, P2, Z0.H
+ fmaxnmv h0, p7, z0.h
+ FMAXNMV H0, P7, Z0.H
+ fmaxnmv h0, p0, z3.h
+ FMAXNMV H0, P0, Z3.H
+ fmaxnmv h0, p0, z31.h
+ FMAXNMV H0, P0, Z31.H
fmaxnmv s0, p0, z0.s
FMAXNMV S0, P0, Z0.S
fmaxnmv s1, p0, z0.s
@@ -9357,6 +10235,20 @@
FMAXNMV D0, P0, Z3.D
fmaxnmv d0, p0, z31.d
FMAXNMV D0, P0, Z31.D
+ fmaxv h0, p0, z0.h
+ FMAXV H0, P0, Z0.H
+ fmaxv h1, p0, z0.h
+ FMAXV H1, P0, Z0.H
+ fmaxv h31, p0, z0.h
+ FMAXV H31, P0, Z0.H
+ fmaxv h0, p2, z0.h
+ FMAXV H0, P2, Z0.H
+ fmaxv h0, p7, z0.h
+ FMAXV H0, P7, Z0.H
+ fmaxv h0, p0, z3.h
+ FMAXV H0, P0, Z3.H
+ fmaxv h0, p0, z31.h
+ FMAXV H0, P0, Z31.H
fmaxv s0, p0, z0.s
FMAXV S0, P0, Z0.S
fmaxv s1, p0, z0.s
@@ -9385,6 +10277,22 @@
FMAXV D0, P0, Z3.D
fmaxv d0, p0, z31.d
FMAXV D0, P0, Z31.D
+ fmin z0.h, p0/m, z0.h, z0.h
+ FMIN Z0.H, P0/M, Z0.H, Z0.H
+ fmin z1.h, p0/m, z1.h, z0.h
+ FMIN Z1.H, P0/M, Z1.H, Z0.H
+ fmin z31.h, p0/m, z31.h, z0.h
+ FMIN Z31.H, P0/M, Z31.H, Z0.H
+ fmin z0.h, p2/m, z0.h, z0.h
+ FMIN Z0.H, P2/M, Z0.H, Z0.H
+ fmin z0.h, p7/m, z0.h, z0.h
+ FMIN Z0.H, P7/M, Z0.H, Z0.H
+ fmin z3.h, p0/m, z3.h, z0.h
+ FMIN Z3.H, P0/M, Z3.H, Z0.H
+ fmin z0.h, p0/m, z0.h, z4.h
+ FMIN Z0.H, P0/M, Z0.H, Z4.H
+ fmin z0.h, p0/m, z0.h, z31.h
+ FMIN Z0.H, P0/M, Z0.H, Z31.H
fmin z0.s, p0/m, z0.s, z0.s
FMIN Z0.S, P0/M, Z0.S, Z0.S
fmin z1.s, p0/m, z1.s, z0.s
@@ -9417,6 +10325,34 @@
FMIN Z0.D, P0/M, Z0.D, Z4.D
fmin z0.d, p0/m, z0.d, z31.d
FMIN Z0.D, P0/M, Z0.D, Z31.D
+ fmin z0.h, p0/m, z0.h, #0.0
+ FMIN Z0.H, P0/M, Z0.H, #0.0
+ fmin z0.h, p0/m, z0.h, #0.00000
+ fmin z0.h, p0/m, z0.h, #0.0000000000e+00
+ fmin z1.h, p0/m, z1.h, #0.0
+ FMIN Z1.H, P0/M, Z1.H, #0.0
+ fmin z1.h, p0/m, z1.h, #0.00000
+ fmin z1.h, p0/m, z1.h, #0.0000000000e+00
+ fmin z31.h, p0/m, z31.h, #0.0
+ FMIN Z31.H, P0/M, Z31.H, #0.0
+ fmin z31.h, p0/m, z31.h, #0.00000
+ fmin z31.h, p0/m, z31.h, #0.0000000000e+00
+ fmin z0.h, p2/m, z0.h, #0.0
+ FMIN Z0.H, P2/M, Z0.H, #0.0
+ fmin z0.h, p2/m, z0.h, #0.00000
+ fmin z0.h, p2/m, z0.h, #0.0000000000e+00
+ fmin z0.h, p7/m, z0.h, #0.0
+ FMIN Z0.H, P7/M, Z0.H, #0.0
+ fmin z0.h, p7/m, z0.h, #0.00000
+ fmin z0.h, p7/m, z0.h, #0.0000000000e+00
+ fmin z3.h, p0/m, z3.h, #0.0
+ FMIN Z3.H, P0/M, Z3.H, #0.0
+ fmin z3.h, p0/m, z3.h, #0.00000
+ fmin z3.h, p0/m, z3.h, #0.0000000000e+00
+ fmin z0.h, p0/m, z0.h, #1.0
+ FMIN Z0.H, P0/M, Z0.H, #1.0
+ fmin z0.h, p0/m, z0.h, #1.00000
+ fmin z0.h, p0/m, z0.h, #1.0000000000e+00
fmin z0.s, p0/m, z0.s, #0.0
FMIN Z0.S, P0/M, Z0.S, #0.0
fmin z0.s, p0/m, z0.s, #0.00000
@@ -9473,6 +10409,22 @@
FMIN Z0.D, P0/M, Z0.D, #1.0
fmin z0.d, p0/m, z0.d, #1.00000
fmin z0.d, p0/m, z0.d, #1.0000000000e+00
+ fminnm z0.h, p0/m, z0.h, z0.h
+ FMINNM Z0.H, P0/M, Z0.H, Z0.H
+ fminnm z1.h, p0/m, z1.h, z0.h
+ FMINNM Z1.H, P0/M, Z1.H, Z0.H
+ fminnm z31.h, p0/m, z31.h, z0.h
+ FMINNM Z31.H, P0/M, Z31.H, Z0.H
+ fminnm z0.h, p2/m, z0.h, z0.h
+ FMINNM Z0.H, P2/M, Z0.H, Z0.H
+ fminnm z0.h, p7/m, z0.h, z0.h
+ FMINNM Z0.H, P7/M, Z0.H, Z0.H
+ fminnm z3.h, p0/m, z3.h, z0.h
+ FMINNM Z3.H, P0/M, Z3.H, Z0.H
+ fminnm z0.h, p0/m, z0.h, z4.h
+ FMINNM Z0.H, P0/M, Z0.H, Z4.H
+ fminnm z0.h, p0/m, z0.h, z31.h
+ FMINNM Z0.H, P0/M, Z0.H, Z31.H
fminnm z0.s, p0/m, z0.s, z0.s
FMINNM Z0.S, P0/M, Z0.S, Z0.S
fminnm z1.s, p0/m, z1.s, z0.s
@@ -9505,6 +10457,34 @@
FMINNM Z0.D, P0/M, Z0.D, Z4.D
fminnm z0.d, p0/m, z0.d, z31.d
FMINNM Z0.D, P0/M, Z0.D, Z31.D
+ fminnm z0.h, p0/m, z0.h, #0.0
+ FMINNM Z0.H, P0/M, Z0.H, #0.0
+ fminnm z0.h, p0/m, z0.h, #0.00000
+ fminnm z0.h, p0/m, z0.h, #0.0000000000e+00
+ fminnm z1.h, p0/m, z1.h, #0.0
+ FMINNM Z1.H, P0/M, Z1.H, #0.0
+ fminnm z1.h, p0/m, z1.h, #0.00000
+ fminnm z1.h, p0/m, z1.h, #0.0000000000e+00
+ fminnm z31.h, p0/m, z31.h, #0.0
+ FMINNM Z31.H, P0/M, Z31.H, #0.0
+ fminnm z31.h, p0/m, z31.h, #0.00000
+ fminnm z31.h, p0/m, z31.h, #0.0000000000e+00
+ fminnm z0.h, p2/m, z0.h, #0.0
+ FMINNM Z0.H, P2/M, Z0.H, #0.0
+ fminnm z0.h, p2/m, z0.h, #0.00000
+ fminnm z0.h, p2/m, z0.h, #0.0000000000e+00
+ fminnm z0.h, p7/m, z0.h, #0.0
+ FMINNM Z0.H, P7/M, Z0.H, #0.0
+ fminnm z0.h, p7/m, z0.h, #0.00000
+ fminnm z0.h, p7/m, z0.h, #0.0000000000e+00
+ fminnm z3.h, p0/m, z3.h, #0.0
+ FMINNM Z3.H, P0/M, Z3.H, #0.0
+ fminnm z3.h, p0/m, z3.h, #0.00000
+ fminnm z3.h, p0/m, z3.h, #0.0000000000e+00
+ fminnm z0.h, p0/m, z0.h, #1.0
+ FMINNM Z0.H, P0/M, Z0.H, #1.0
+ fminnm z0.h, p0/m, z0.h, #1.00000
+ fminnm z0.h, p0/m, z0.h, #1.0000000000e+00
fminnm z0.s, p0/m, z0.s, #0.0
FMINNM Z0.S, P0/M, Z0.S, #0.0
fminnm z0.s, p0/m, z0.s, #0.00000
@@ -9561,6 +10541,20 @@
FMINNM Z0.D, P0/M, Z0.D, #1.0
fminnm z0.d, p0/m, z0.d, #1.00000
fminnm z0.d, p0/m, z0.d, #1.0000000000e+00
+ fminnmv h0, p0, z0.h
+ FMINNMV h0, P0, Z0.H
+ fminnmv h1, p0, z0.h
+ FMINNMV h1, P0, Z0.H
+ fminnmv h31, p0, z0.h
+ FMINNMV h31, P0, Z0.H
+ fminnmv h0, p2, z0.h
+ FMINNMV h0, P2, Z0.H
+ fminnmv h0, p7, z0.h
+ FMINNMV h0, P7, Z0.H
+ fminnmv h0, p0, z3.h
+ FMINNMV h0, P0, Z3.H
+ fminnmv h0, p0, z31.h
+ FMINNMV h0, P0, Z31.H
fminnmv s0, p0, z0.s
FMINNMV S0, P0, Z0.S
fminnmv s1, p0, z0.s
@@ -9589,6 +10583,20 @@
FMINNMV D0, P0, Z3.D
fminnmv d0, p0, z31.d
FMINNMV D0, P0, Z31.D
+ fminv h0, p0, z0.h
+ FMINV H0, P0, Z0.H
+ fminv h1, p0, z0.h
+ FMINV H1, P0, Z0.H
+ fminv h31, p0, z0.h
+ FMINV H31, P0, Z0.H
+ fminv h0, p2, z0.h
+ FMINV H0, P2, Z0.H
+ fminv h0, p7, z0.h
+ FMINV H0, P7, Z0.H
+ fminv h0, p0, z3.h
+ FMINV H0, P0, Z3.H
+ fminv h0, p0, z31.h
+ FMINV H0, P0, Z31.H
fminv s0, p0, z0.s
FMINV S0, P0, Z0.S
fminv s1, p0, z0.s
@@ -9617,6 +10625,24 @@
FMINV D0, P0, Z3.D
fminv d0, p0, z31.d
FMINV D0, P0, Z31.D
+ fmla z0.h, p0/m, z0.h, z0.h
+ FMLA Z0.H, P0/M, Z0.H, Z0.H
+ fmla z1.h, p0/m, z0.h, z0.h
+ FMLA Z1.H, P0/M, Z0.H, Z0.H
+ fmla z31.h, p0/m, z0.h, z0.h
+ FMLA Z31.H, P0/M, Z0.H, Z0.H
+ fmla z0.h, p2/m, z0.h, z0.h
+ FMLA Z0.H, P2/M, Z0.H, Z0.H
+ fmla z0.h, p7/m, z0.h, z0.h
+ FMLA Z0.H, P7/M, Z0.H, Z0.H
+ fmla z0.h, p0/m, z3.h, z0.h
+ FMLA Z0.H, P0/M, Z3.H, Z0.H
+ fmla z0.h, p0/m, z31.h, z0.h
+ FMLA Z0.H, P0/M, Z31.H, Z0.H
+ fmla z0.h, p0/m, z0.h, z4.h
+ FMLA Z0.H, P0/M, Z0.H, Z4.H
+ fmla z0.h, p0/m, z0.h, z31.h
+ FMLA Z0.H, P0/M, Z0.H, Z31.H
fmla z0.s, p0/m, z0.s, z0.s
FMLA Z0.S, P0/M, Z0.S, Z0.S
fmla z1.s, p0/m, z0.s, z0.s
@@ -9653,6 +10679,90 @@
FMLA Z0.D, P0/M, Z0.D, Z4.D
fmla z0.d, p0/m, z0.d, z31.d
FMLA Z0.D, P0/M, Z0.D, Z31.D
+ fmla z0.h, z0.h, z0.h[0]
+ FMLA Z0.H, Z0.H, Z0.H[0]
+ fmla z1.h, z0.h, z0.h[0]
+ FMLA Z1.H, Z0.H, Z0.H[0]
+ fmla z31.h, z0.h, z0.h[0]
+ FMLA Z31.H, Z0.H, Z0.H[0]
+ fmla z0.h, z2.h, z0.h[0]
+ FMLA Z0.H, Z2.H, Z0.H[0]
+ fmla z0.h, z31.h, z0.h[0]
+ FMLA Z0.H, Z31.H, Z0.H[0]
+ fmla z0.h, z0.h, z3.h[0]
+ FMLA Z0.H, Z0.H, Z3.H[0]
+ fmla z0.h, z0.h, z7.h[0]
+ FMLA Z0.H, Z0.H, Z7.H[0]
+ fmla z0.h, z0.h, z0.h[1]
+ FMLA Z0.H, Z0.H, Z0.H[1]
+ fmla z0.h, z0.h, z4.h[1]
+ FMLA Z0.H, Z0.H, Z4.H[1]
+ fmla z0.h, z0.h, z3.h[4]
+ FMLA Z0.H, Z0.H, Z3.H[4]
+ fmla z0.h, z0.h, z0.h[7]
+ FMLA Z0.H, Z0.H, Z0.H[7]
+ fmla z0.h, z0.h, z5.h[7]
+ FMLA Z0.H, Z0.H, Z5.H[7]
+ fmla z0.s, z0.s, z0.s[0]
+ FMLA Z0.S, Z0.S, Z0.S[0]
+ fmla z1.s, z0.s, z0.s[0]
+ FMLA Z1.S, Z0.S, Z0.S[0]
+ fmla z31.s, z0.s, z0.s[0]
+ FMLA Z31.S, Z0.S, Z0.S[0]
+ fmla z0.s, z2.s, z0.s[0]
+ FMLA Z0.S, Z2.S, Z0.S[0]
+ fmla z0.s, z31.s, z0.s[0]
+ FMLA Z0.S, Z31.S, Z0.S[0]
+ fmla z0.s, z0.s, z3.s[0]
+ FMLA Z0.S, Z0.S, Z3.S[0]
+ fmla z0.s, z0.s, z7.s[0]
+ FMLA Z0.S, Z0.S, Z7.S[0]
+ fmla z0.s, z0.s, z0.s[1]
+ FMLA Z0.S, Z0.S, Z0.S[1]
+ fmla z0.s, z0.s, z4.s[1]
+ FMLA Z0.S, Z0.S, Z4.S[1]
+ fmla z0.s, z0.s, z3.s[2]
+ FMLA Z0.S, Z0.S, Z3.S[2]
+ fmla z0.s, z0.s, z0.s[3]
+ FMLA Z0.S, Z0.S, Z0.S[3]
+ fmla z0.s, z0.s, z5.s[3]
+ FMLA Z0.S, Z0.S, Z5.S[3]
+ fmla z0.d, z0.d, z0.d[0]
+ FMLA Z0.D, Z0.D, Z0.D[0]
+ fmla z1.d, z0.d, z0.d[0]
+ FMLA Z1.D, Z0.D, Z0.D[0]
+ fmla z31.d, z0.d, z0.d[0]
+ FMLA Z31.D, Z0.D, Z0.D[0]
+ fmla z0.d, z2.d, z0.d[0]
+ FMLA Z0.D, Z2.D, Z0.D[0]
+ fmla z0.d, z31.d, z0.d[0]
+ FMLA Z0.D, Z31.D, Z0.D[0]
+ fmla z0.d, z0.d, z3.d[0]
+ FMLA Z0.D, Z0.D, Z3.D[0]
+ fmla z0.d, z0.d, z15.d[0]
+ FMLA Z0.D, Z0.D, Z15.D[0]
+ fmla z0.d, z0.d, z0.d[1]
+ FMLA Z0.D, Z0.D, Z0.D[1]
+ fmla z0.d, z0.d, z11.d[1]
+ FMLA Z0.D, Z0.D, Z11.D[1]
+ fmls z0.h, p0/m, z0.h, z0.h
+ FMLS Z0.H, P0/M, Z0.H, Z0.H
+ fmls z1.h, p0/m, z0.h, z0.h
+ FMLS Z1.H, P0/M, Z0.H, Z0.H
+ fmls z31.h, p0/m, z0.h, z0.h
+ FMLS Z31.H, P0/M, Z0.H, Z0.H
+ fmls z0.h, p2/m, z0.h, z0.h
+ FMLS Z0.H, P2/M, Z0.H, Z0.H
+ fmls z0.h, p7/m, z0.h, z0.h
+ FMLS Z0.H, P7/M, Z0.H, Z0.H
+ fmls z0.h, p0/m, z3.h, z0.h
+ FMLS Z0.H, P0/M, Z3.H, Z0.H
+ fmls z0.h, p0/m, z31.h, z0.h
+ FMLS Z0.H, P0/M, Z31.H, Z0.H
+ fmls z0.h, p0/m, z0.h, z4.h
+ FMLS Z0.H, P0/M, Z0.H, Z4.H
+ fmls z0.h, p0/m, z0.h, z31.h
+ FMLS Z0.H, P0/M, Z0.H, Z31.H
fmls z0.s, p0/m, z0.s, z0.s
FMLS Z0.S, P0/M, Z0.S, Z0.S
fmls z1.s, p0/m, z0.s, z0.s
@@ -9689,6 +10799,90 @@
FMLS Z0.D, P0/M, Z0.D, Z4.D
fmls z0.d, p0/m, z0.d, z31.d
FMLS Z0.D, P0/M, Z0.D, Z31.D
+ fmls z0.h, z0.h, z0.h[0]
+ FMLS Z0.H, Z0.H, Z0.H[0]
+ fmls z1.h, z0.h, z0.h[0]
+ FMLS Z1.H, Z0.H, Z0.H[0]
+ fmls z31.h, z0.h, z0.h[0]
+ FMLS Z31.H, Z0.H, Z0.H[0]
+ fmls z0.h, z2.h, z0.h[0]
+ FMLS Z0.H, Z2.H, Z0.H[0]
+ fmls z0.h, z31.h, z0.h[0]
+ FMLS Z0.H, Z31.H, Z0.H[0]
+ fmls z0.h, z0.h, z3.h[0]
+ FMLS Z0.H, Z0.H, Z3.H[0]
+ fmls z0.h, z0.h, z7.h[0]
+ FMLS Z0.H, Z0.H, Z7.H[0]
+ fmls z0.h, z0.h, z0.h[1]
+ FMLS Z0.H, Z0.H, Z0.H[1]
+ fmls z0.h, z0.h, z4.h[1]
+ FMLS Z0.H, Z0.H, Z4.H[1]
+ fmls z0.h, z0.h, z3.h[4]
+ FMLS Z0.H, Z0.H, Z3.H[4]
+ fmls z0.h, z0.h, z0.h[7]
+ FMLS Z0.H, Z0.H, Z0.H[7]
+ fmls z0.h, z0.h, z5.h[7]
+ FMLS Z0.H, Z0.H, Z5.H[7]
+ fmls z0.s, z0.s, z0.s[0]
+ FMLS Z0.S, Z0.S, Z0.S[0]
+ fmls z1.s, z0.s, z0.s[0]
+ FMLS Z1.S, Z0.S, Z0.S[0]
+ fmls z31.s, z0.s, z0.s[0]
+ FMLS Z31.S, Z0.S, Z0.S[0]
+ fmls z0.s, z2.s, z0.s[0]
+ FMLS Z0.S, Z2.S, Z0.S[0]
+ fmls z0.s, z31.s, z0.s[0]
+ FMLS Z0.S, Z31.S, Z0.S[0]
+ fmls z0.s, z0.s, z3.s[0]
+ FMLS Z0.S, Z0.S, Z3.S[0]
+ fmls z0.s, z0.s, z7.s[0]
+ FMLS Z0.S, Z0.S, Z7.S[0]
+ fmls z0.s, z0.s, z0.s[1]
+ FMLS Z0.S, Z0.S, Z0.S[1]
+ fmls z0.s, z0.s, z4.s[1]
+ FMLS Z0.S, Z0.S, Z4.S[1]
+ fmls z0.s, z0.s, z3.s[2]
+ FMLS Z0.S, Z0.S, Z3.S[2]
+ fmls z0.s, z0.s, z0.s[3]
+ FMLS Z0.S, Z0.S, Z0.S[3]
+ fmls z0.s, z0.s, z5.s[3]
+ FMLS Z0.S, Z0.S, Z5.S[3]
+ fmls z0.d, z0.d, z0.d[0]
+ FMLS Z0.D, Z0.D, Z0.D[0]
+ fmls z1.d, z0.d, z0.d[0]
+ FMLS Z1.D, Z0.D, Z0.D[0]
+ fmls z31.d, z0.d, z0.d[0]
+ FMLS Z31.D, Z0.D, Z0.D[0]
+ fmls z0.d, z2.d, z0.d[0]
+ FMLS Z0.D, Z2.D, Z0.D[0]
+ fmls z0.d, z31.d, z0.d[0]
+ FMLS Z0.D, Z31.D, Z0.D[0]
+ fmls z0.d, z0.d, z3.d[0]
+ FMLS Z0.D, Z0.D, Z3.D[0]
+ fmls z0.d, z0.d, z15.d[0]
+ FMLS Z0.D, Z0.D, Z15.D[0]
+ fmls z0.d, z0.d, z0.d[1]
+ FMLS Z0.D, Z0.D, Z0.D[1]
+ fmls z0.d, z0.d, z11.d[1]
+ FMLS Z0.D, Z0.D, Z11.D[1]
+ fmsb z0.h, p0/m, z0.h, z0.h
+ FMSB Z0.H, P0/M, Z0.H, Z0.H
+ fmsb z1.h, p0/m, z0.h, z0.h
+ FMSB Z1.H, P0/M, Z0.H, Z0.H
+ fmsb z31.h, p0/m, z0.h, z0.h
+ FMSB Z31.H, P0/M, Z0.H, Z0.H
+ fmsb z0.h, p2/m, z0.h, z0.h
+ FMSB Z0.H, P2/M, Z0.H, Z0.H
+ fmsb z0.h, p7/m, z0.h, z0.h
+ FMSB Z0.H, P7/M, Z0.H, Z0.H
+ fmsb z0.h, p0/m, z3.h, z0.h
+ FMSB Z0.H, P0/M, Z3.H, Z0.H
+ fmsb z0.h, p0/m, z31.h, z0.h
+ FMSB Z0.H, P0/M, Z31.H, Z0.H
+ fmsb z0.h, p0/m, z0.h, z4.h
+ FMSB Z0.H, P0/M, Z0.H, Z4.H
+ fmsb z0.h, p0/m, z0.h, z31.h
+ FMSB Z0.H, P0/M, Z0.H, Z31.H
fmsb z0.s, p0/m, z0.s, z0.s
FMSB Z0.S, P0/M, Z0.S, Z0.S
fmsb z1.s, p0/m, z0.s, z0.s
@@ -9725,6 +10919,20 @@
FMSB Z0.D, P0/M, Z0.D, Z4.D
fmsb z0.d, p0/m, z0.d, z31.d
FMSB Z0.D, P0/M, Z0.D, Z31.D
+ fmul z0.h, z0.h, z0.h
+ FMUL Z0.H, Z0.H, Z0.H
+ fmul z1.h, z0.h, z0.h
+ FMUL Z1.H, Z0.H, Z0.H
+ fmul z31.h, z0.h, z0.h
+ FMUL Z31.H, Z0.H, Z0.H
+ fmul z0.h, z2.h, z0.h
+ FMUL Z0.H, Z2.H, Z0.H
+ fmul z0.h, z31.h, z0.h
+ FMUL Z0.H, Z31.H, Z0.H
+ fmul z0.h, z0.h, z3.h
+ FMUL Z0.H, Z0.H, Z3.H
+ fmul z0.h, z0.h, z31.h
+ FMUL Z0.H, Z0.H, Z31.H
fmul z0.s, z0.s, z0.s
FMUL Z0.S, Z0.S, Z0.S
fmul z1.s, z0.s, z0.s
@@ -9753,6 +10961,22 @@
FMUL Z0.D, Z0.D, Z3.D
fmul z0.d, z0.d, z31.d
FMUL Z0.D, Z0.D, Z31.D
+ fmul z0.h, p0/m, z0.h, z0.h
+ FMUL Z0.H, P0/M, Z0.H, Z0.H
+ fmul z1.h, p0/m, z1.h, z0.h
+ FMUL Z1.H, P0/M, Z1.H, Z0.H
+ fmul z31.h, p0/m, z31.h, z0.h
+ FMUL Z31.H, P0/M, Z31.H, Z0.H
+ fmul z0.h, p2/m, z0.h, z0.h
+ FMUL Z0.H, P2/M, Z0.H, Z0.H
+ fmul z0.h, p7/m, z0.h, z0.h
+ FMUL Z0.H, P7/M, Z0.H, Z0.H
+ fmul z3.h, p0/m, z3.h, z0.h
+ FMUL Z3.H, P0/M, Z3.H, Z0.H
+ fmul z0.h, p0/m, z0.h, z4.h
+ FMUL Z0.H, P0/M, Z0.H, Z4.H
+ fmul z0.h, p0/m, z0.h, z31.h
+ FMUL Z0.H, P0/M, Z0.H, Z31.H
fmul z0.s, p0/m, z0.s, z0.s
FMUL Z0.S, P0/M, Z0.S, Z0.S
fmul z1.s, p0/m, z1.s, z0.s
@@ -9785,6 +11009,34 @@
FMUL Z0.D, P0/M, Z0.D, Z4.D
fmul z0.d, p0/m, z0.d, z31.d
FMUL Z0.D, P0/M, Z0.D, Z31.D
+ fmul z0.h, p0/m, z0.h, #0.5
+ FMUL Z0.H, P0/M, Z0.H, #0.5
+ fmul z0.h, p0/m, z0.h, #0.50000
+ fmul z0.h, p0/m, z0.h, #5.0000000000e-01
+ fmul z1.h, p0/m, z1.h, #0.5
+ FMUL Z1.H, P0/M, Z1.H, #0.5
+ fmul z1.h, p0/m, z1.h, #0.50000
+ fmul z1.h, p0/m, z1.h, #5.0000000000e-01
+ fmul z31.h, p0/m, z31.h, #0.5
+ FMUL Z31.H, P0/M, Z31.H, #0.5
+ fmul z31.h, p0/m, z31.h, #0.50000
+ fmul z31.h, p0/m, z31.h, #5.0000000000e-01
+ fmul z0.h, p2/m, z0.h, #0.5
+ FMUL Z0.H, P2/M, Z0.H, #0.5
+ fmul z0.h, p2/m, z0.h, #0.50000
+ fmul z0.h, p2/m, z0.h, #5.0000000000e-01
+ fmul z0.h, p7/m, z0.h, #0.5
+ FMUL Z0.H, P7/M, Z0.H, #0.5
+ fmul z0.h, p7/m, z0.h, #0.50000
+ fmul z0.h, p7/m, z0.h, #5.0000000000e-01
+ fmul z3.h, p0/m, z3.h, #0.5
+ FMUL Z3.H, P0/M, Z3.H, #0.5
+ fmul z3.h, p0/m, z3.h, #0.50000
+ fmul z3.h, p0/m, z3.h, #5.0000000000e-01
+ fmul z0.h, p0/m, z0.h, #2.0
+ FMUL Z0.H, P0/M, Z0.H, #2.0
+ fmul z0.h, p0/m, z0.h, #2.00000
+ fmul z0.h, p0/m, z0.h, #2.0000000000e+00
fmul z0.s, p0/m, z0.s, #0.5
FMUL Z0.S, P0/M, Z0.S, #0.5
fmul z0.s, p0/m, z0.s, #0.50000
@@ -9841,6 +11093,88 @@
FMUL Z0.D, P0/M, Z0.D, #2.0
fmul z0.d, p0/m, z0.d, #2.00000
fmul z0.d, p0/m, z0.d, #2.0000000000e+00
+ fmul z0.h, z0.h, z0.h[0]
+ FMUL Z0.H, Z0.H, Z0.H[0]
+ fmul z1.h, z0.h, z0.h[0]
+ FMUL Z1.H, Z0.H, Z0.H[0]
+ fmul z31.h, z0.h, z0.h[0]
+ FMUL Z31.H, Z0.H, Z0.H[0]
+ fmul z0.h, z2.h, z0.h[0]
+ FMUL Z0.H, Z2.H, Z0.H[0]
+ fmul z0.h, z31.h, z0.h[0]
+ FMUL Z0.H, Z31.H, Z0.H[0]
+ fmul z0.h, z0.h, z3.h[0]
+ FMUL Z0.H, Z0.H, Z3.H[0]
+ fmul z0.h, z0.h, z7.h[0]
+ FMUL Z0.H, Z0.H, Z7.H[0]
+ fmul z0.h, z0.h, z0.h[1]
+ FMUL Z0.H, Z0.H, Z0.H[1]
+ fmul z0.h, z0.h, z4.h[1]
+ FMUL Z0.H, Z0.H, Z4.H[1]
+ fmul z0.h, z0.h, z3.h[4]
+ FMUL Z0.H, Z0.H, Z3.H[4]
+ fmul z0.h, z0.h, z0.h[7]
+ FMUL Z0.H, Z0.H, Z0.H[7]
+ fmul z0.h, z0.h, z5.h[7]
+ FMUL Z0.H, Z0.H, Z5.H[7]
+ fmul z0.s, z0.s, z0.s[0]
+ FMUL Z0.S, Z0.S, Z0.S[0]
+ fmul z1.s, z0.s, z0.s[0]
+ FMUL Z1.S, Z0.S, Z0.S[0]
+ fmul z31.s, z0.s, z0.s[0]
+ FMUL Z31.S, Z0.S, Z0.S[0]
+ fmul z0.s, z2.s, z0.s[0]
+ FMUL Z0.S, Z2.S, Z0.S[0]
+ fmul z0.s, z31.s, z0.s[0]
+ FMUL Z0.S, Z31.S, Z0.S[0]
+ fmul z0.s, z0.s, z3.s[0]
+ FMUL Z0.S, Z0.S, Z3.S[0]
+ fmul z0.s, z0.s, z7.s[0]
+ FMUL Z0.S, Z0.S, Z7.S[0]
+ fmul z0.s, z0.s, z0.s[1]
+ FMUL Z0.S, Z0.S, Z0.S[1]
+ fmul z0.s, z0.s, z4.s[1]
+ FMUL Z0.S, Z0.S, Z4.S[1]
+ fmul z0.s, z0.s, z3.s[2]
+ FMUL Z0.S, Z0.S, Z3.S[2]
+ fmul z0.s, z0.s, z0.s[3]
+ FMUL Z0.S, Z0.S, Z0.S[3]
+ fmul z0.s, z0.s, z5.s[3]
+ FMUL Z0.S, Z0.S, Z5.S[3]
+ fmul z0.d, z0.d, z0.d[0]
+ FMUL Z0.D, Z0.D, Z0.D[0]
+ fmul z1.d, z0.d, z0.d[0]
+ FMUL Z1.D, Z0.D, Z0.D[0]
+ fmul z31.d, z0.d, z0.d[0]
+ FMUL Z31.D, Z0.D, Z0.D[0]
+ fmul z0.d, z2.d, z0.d[0]
+ FMUL Z0.D, Z2.D, Z0.D[0]
+ fmul z0.d, z31.d, z0.d[0]
+ FMUL Z0.D, Z31.D, Z0.D[0]
+ fmul z0.d, z0.d, z3.d[0]
+ FMUL Z0.D, Z0.D, Z3.D[0]
+ fmul z0.d, z0.d, z15.d[0]
+ FMUL Z0.D, Z0.D, Z15.D[0]
+ fmul z0.d, z0.d, z0.d[1]
+ FMUL Z0.D, Z0.D, Z0.D[1]
+ fmul z0.d, z0.d, z11.d[1]
+ FMUL Z0.D, Z0.D, Z11.D[1]
+ fmulx z0.h, p0/m, z0.h, z0.h
+ FMULX Z0.H, P0/M, Z0.H, Z0.H
+ fmulx z1.h, p0/m, z1.h, z0.h
+ FMULX Z1.H, P0/M, Z1.H, Z0.H
+ fmulx z31.h, p0/m, z31.h, z0.h
+ FMULX Z31.H, P0/M, Z31.H, Z0.H
+ fmulx z0.h, p2/m, z0.h, z0.h
+ FMULX Z0.H, P2/M, Z0.H, Z0.H
+ fmulx z0.h, p7/m, z0.h, z0.h
+ FMULX Z0.H, P7/M, Z0.H, Z0.H
+ fmulx z3.h, p0/m, z3.h, z0.h
+ FMULX Z3.H, P0/M, Z3.H, Z0.H
+ fmulx z0.h, p0/m, z0.h, z4.h
+ FMULX Z0.H, P0/M, Z0.H, Z4.H
+ fmulx z0.h, p0/m, z0.h, z31.h
+ FMULX Z0.H, P0/M, Z0.H, Z31.H
fmulx z0.s, p0/m, z0.s, z0.s
FMULX Z0.S, P0/M, Z0.S, Z0.S
fmulx z1.s, p0/m, z1.s, z0.s
@@ -9873,6 +11207,20 @@
FMULX Z0.D, P0/M, Z0.D, Z4.D
fmulx z0.d, p0/m, z0.d, z31.d
FMULX Z0.D, P0/M, Z0.D, Z31.D
+ fneg z0.h, p0/m, z0.h
+ FNEG Z0.H, P0/M, Z0.H
+ fneg z1.h, p0/m, z0.h
+ FNEG Z1.H, P0/M, Z0.H
+ fneg z31.h, p0/m, z0.h
+ FNEG Z31.H, P0/M, Z0.H
+ fneg z0.h, p2/m, z0.h
+ FNEG Z0.H, P2/M, Z0.H
+ fneg z0.h, p7/m, z0.h
+ FNEG Z0.H, P7/M, Z0.H
+ fneg z0.h, p0/m, z3.h
+ FNEG Z0.H, P0/M, Z3.H
+ fneg z0.h, p0/m, z31.h
+ FNEG Z0.H, P0/M, Z31.H
fneg z0.s, p0/m, z0.s
FNEG Z0.S, P0/M, Z0.S
fneg z1.s, p0/m, z0.s
@@ -9901,6 +11249,24 @@
FNEG Z0.D, P0/M, Z3.D
fneg z0.d, p0/m, z31.d
FNEG Z0.D, P0/M, Z31.D
+ fnmad z0.h, p0/m, z0.h, z0.h
+ FNMAD Z0.H, P0/M, Z0.H, Z0.H
+ fnmad z1.h, p0/m, z0.h, z0.h
+ FNMAD Z1.H, P0/M, Z0.H, Z0.H
+ fnmad z31.h, p0/m, z0.h, z0.h
+ FNMAD Z31.H, P0/M, Z0.H, Z0.H
+ fnmad z0.h, p2/m, z0.h, z0.h
+ FNMAD Z0.H, P2/M, Z0.H, Z0.H
+ fnmad z0.h, p7/m, z0.h, z0.h
+ FNMAD Z0.H, P7/M, Z0.H, Z0.H
+ fnmad z0.h, p0/m, z3.h, z0.h
+ FNMAD Z0.H, P0/M, Z3.H, Z0.H
+ fnmad z0.h, p0/m, z31.h, z0.h
+ FNMAD Z0.H, P0/M, Z31.H, Z0.H
+ fnmad z0.h, p0/m, z0.h, z4.h
+ FNMAD Z0.H, P0/M, Z0.H, Z4.H
+ fnmad z0.h, p0/m, z0.h, z31.h
+ FNMAD Z0.H, P0/M, Z0.H, Z31.H
fnmad z0.s, p0/m, z0.s, z0.s
FNMAD Z0.S, P0/M, Z0.S, Z0.S
fnmad z1.s, p0/m, z0.s, z0.s
@@ -9937,6 +11303,24 @@
FNMAD Z0.D, P0/M, Z0.D, Z4.D
fnmad z0.d, p0/m, z0.d, z31.d
FNMAD Z0.D, P0/M, Z0.D, Z31.D
+ fnmla z0.h, p0/m, z0.h, z0.h
+ FNMLA Z0.H, P0/M, Z0.H, Z0.H
+ fnmla z1.h, p0/m, z0.h, z0.h
+ FNMLA Z1.H, P0/M, Z0.H, Z0.H
+ fnmla z31.h, p0/m, z0.h, z0.h
+ FNMLA Z31.H, P0/M, Z0.H, Z0.H
+ fnmla z0.h, p2/m, z0.h, z0.h
+ FNMLA Z0.H, P2/M, Z0.H, Z0.H
+ fnmla z0.h, p7/m, z0.h, z0.h
+ FNMLA Z0.H, P7/M, Z0.H, Z0.H
+ fnmla z0.h, p0/m, z3.h, z0.h
+ FNMLA Z0.H, P0/M, Z3.H, Z0.H
+ fnmla z0.h, p0/m, z31.h, z0.h
+ FNMLA Z0.H, P0/M, Z31.H, Z0.H
+ fnmla z0.h, p0/m, z0.h, z4.h
+ FNMLA Z0.H, P0/M, Z0.H, Z4.H
+ fnmla z0.h, p0/m, z0.h, z31.h
+ FNMLA Z0.H, P0/M, Z0.H, Z31.H
fnmla z0.s, p0/m, z0.s, z0.s
FNMLA Z0.S, P0/M, Z0.S, Z0.S
fnmla z1.s, p0/m, z0.s, z0.s
@@ -9973,6 +11357,24 @@
FNMLA Z0.D, P0/M, Z0.D, Z4.D
fnmla z0.d, p0/m, z0.d, z31.d
FNMLA Z0.D, P0/M, Z0.D, Z31.D
+ fnmls z0.h, p0/m, z0.h, z0.h
+ FNMLS Z0.H, P0/M, Z0.H, Z0.H
+ fnmls z1.h, p0/m, z0.h, z0.h
+ FNMLS Z1.H, P0/M, Z0.H, Z0.H
+ fnmls z31.h, p0/m, z0.h, z0.h
+ FNMLS Z31.H, P0/M, Z0.H, Z0.H
+ fnmls z0.h, p2/m, z0.h, z0.h
+ FNMLS Z0.H, P2/M, Z0.H, Z0.H
+ fnmls z0.h, p7/m, z0.h, z0.h
+ FNMLS Z0.H, P7/M, Z0.H, Z0.H
+ fnmls z0.h, p0/m, z3.h, z0.h
+ FNMLS Z0.H, P0/M, Z3.H, Z0.H
+ fnmls z0.h, p0/m, z31.h, z0.h
+ FNMLS Z0.H, P0/M, Z31.H, Z0.H
+ fnmls z0.h, p0/m, z0.h, z4.h
+ FNMLS Z0.H, P0/M, Z0.H, Z4.H
+ fnmls z0.h, p0/m, z0.h, z31.h
+ FNMLS Z0.H, P0/M, Z0.H, Z31.H
fnmls z0.s, p0/m, z0.s, z0.s
FNMLS Z0.S, P0/M, Z0.S, Z0.S
fnmls z1.s, p0/m, z0.s, z0.s
@@ -10009,6 +11411,24 @@
FNMLS Z0.D, P0/M, Z0.D, Z4.D
fnmls z0.d, p0/m, z0.d, z31.d
FNMLS Z0.D, P0/M, Z0.D, Z31.D
+ fnmsb z0.h, p0/m, z0.h, z0.h
+ FNMSB Z0.H, P0/M, Z0.H, Z0.H
+ fnmsb z1.h, p0/m, z0.h, z0.h
+ FNMSB Z1.H, P0/M, Z0.H, Z0.H
+ fnmsb z31.h, p0/m, z0.h, z0.h
+ FNMSB Z31.H, P0/M, Z0.H, Z0.H
+ fnmsb z0.h, p2/m, z0.h, z0.h
+ FNMSB Z0.H, P2/M, Z0.H, Z0.H
+ fnmsb z0.h, p7/m, z0.h, z0.h
+ FNMSB Z0.H, P7/M, Z0.H, Z0.H
+ fnmsb z0.h, p0/m, z3.h, z0.h
+ FNMSB Z0.H, P0/M, Z3.H, Z0.H
+ fnmsb z0.h, p0/m, z31.h, z0.h
+ FNMSB Z0.H, P0/M, Z31.H, Z0.H
+ fnmsb z0.h, p0/m, z0.h, z4.h
+ FNMSB Z0.H, P0/M, Z0.H, Z4.H
+ fnmsb z0.h, p0/m, z0.h, z31.h
+ FNMSB Z0.H, P0/M, Z0.H, Z31.H
fnmsb z0.s, p0/m, z0.s, z0.s
FNMSB Z0.S, P0/M, Z0.S, Z0.S
fnmsb z1.s, p0/m, z0.s, z0.s
@@ -10045,6 +11465,16 @@
FNMSB Z0.D, P0/M, Z0.D, Z4.D
fnmsb z0.d, p0/m, z0.d, z31.d
FNMSB Z0.D, P0/M, Z0.D, Z31.D
+ frecpe z0.h, z0.h
+ FRECPE Z0.H, Z0.H
+ frecpe z1.h, z0.h
+ FRECPE Z1.H, Z0.H
+ frecpe z31.h, z0.h
+ FRECPE Z31.H, Z0.H
+ frecpe z0.h, z2.h
+ FRECPE Z0.H, Z2.H
+ frecpe z0.h, z31.h
+ FRECPE Z0.H, Z31.H
frecpe z0.s, z0.s
FRECPE Z0.S, Z0.S
frecpe z1.s, z0.s
@@ -10065,6 +11495,20 @@
FRECPE Z0.D, Z2.D
frecpe z0.d, z31.d
FRECPE Z0.D, Z31.D
+ frecps z0.h, z0.h, z0.h
+ FRECPS Z0.H, Z0.H, Z0.H
+ frecps z1.h, z0.h, z0.h
+ FRECPS Z1.H, Z0.H, Z0.H
+ frecps z31.h, z0.h, z0.h
+ FRECPS Z31.H, Z0.H, Z0.H
+ frecps z0.h, z2.h, z0.h
+ FRECPS Z0.H, Z2.H, Z0.H
+ frecps z0.h, z31.h, z0.h
+ FRECPS Z0.H, Z31.H, Z0.H
+ frecps z0.h, z0.h, z3.h
+ FRECPS Z0.H, Z0.H, Z3.H
+ frecps z0.h, z0.h, z31.h
+ FRECPS Z0.H, Z0.H, Z31.H
frecps z0.s, z0.s, z0.s
FRECPS Z0.S, Z0.S, Z0.S
frecps z1.s, z0.s, z0.s
@@ -10093,6 +11537,20 @@
FRECPS Z0.D, Z0.D, Z3.D
frecps z0.d, z0.d, z31.d
FRECPS Z0.D, Z0.D, Z31.D
+ frecpx z0.h, p0/m, z0.h
+ FRECPX Z0.H, P0/M, Z0.H
+ frecpx z1.h, p0/m, z0.h
+ FRECPX Z1.H, P0/M, Z0.H
+ frecpx z31.h, p0/m, z0.h
+ FRECPX Z31.H, P0/M, Z0.H
+ frecpx z0.h, p2/m, z0.h
+ FRECPX Z0.H, P2/M, Z0.H
+ frecpx z0.h, p7/m, z0.h
+ FRECPX Z0.H, P7/M, Z0.H
+ frecpx z0.h, p0/m, z3.h
+ FRECPX Z0.H, P0/M, Z3.H
+ frecpx z0.h, p0/m, z31.h
+ FRECPX Z0.H, P0/M, Z31.H
frecpx z0.s, p0/m, z0.s
FRECPX Z0.S, P0/M, Z0.S
frecpx z1.s, p0/m, z0.s
@@ -10121,6 +11579,20 @@
FRECPX Z0.D, P0/M, Z3.D
frecpx z0.d, p0/m, z31.d
FRECPX Z0.D, P0/M, Z31.D
+ frinta z0.h, p0/m, z0.h
+ FRINTA Z0.H, P0/M, Z0.H
+ frinta z1.h, p0/m, z0.h
+ FRINTA Z1.H, P0/M, Z0.H
+ frinta z31.h, p0/m, z0.h
+ FRINTA Z31.H, P0/M, Z0.H
+ frinta z0.h, p2/m, z0.h
+ FRINTA Z0.H, P2/M, Z0.H
+ frinta z0.h, p7/m, z0.h
+ FRINTA Z0.H, P7/M, Z0.H
+ frinta z0.h, p0/m, z3.h
+ FRINTA Z0.H, P0/M, Z3.H
+ frinta z0.h, p0/m, z31.h
+ FRINTA Z0.H, P0/M, Z31.H
frinta z0.s, p0/m, z0.s
FRINTA Z0.S, P0/M, Z0.S
frinta z1.s, p0/m, z0.s
@@ -10149,6 +11621,20 @@
FRINTA Z0.D, P0/M, Z3.D
frinta z0.d, p0/m, z31.d
FRINTA Z0.D, P0/M, Z31.D
+ frinti z0.h, p0/m, z0.h
+ FRINTI Z0.H, P0/M, Z0.H
+ frinti z1.h, p0/m, z0.h
+ FRINTI Z1.H, P0/M, Z0.H
+ frinti z31.h, p0/m, z0.h
+ FRINTI Z31.H, P0/M, Z0.H
+ frinti z0.h, p2/m, z0.h
+ FRINTI Z0.H, P2/M, Z0.H
+ frinti z0.h, p7/m, z0.h
+ FRINTI Z0.H, P7/M, Z0.H
+ frinti z0.h, p0/m, z3.h
+ FRINTI Z0.H, P0/M, Z3.H
+ frinti z0.h, p0/m, z31.h
+ FRINTI Z0.H, P0/M, Z31.H
frinti z0.s, p0/m, z0.s
FRINTI Z0.S, P0/M, Z0.S
frinti z1.s, p0/m, z0.s
@@ -10177,6 +11663,20 @@
FRINTI Z0.D, P0/M, Z3.D
frinti z0.d, p0/m, z31.d
FRINTI Z0.D, P0/M, Z31.D
+ frintm z0.h, p0/m, z0.h
+ FRINTM Z0.H, P0/M, Z0.H
+ frintm z1.h, p0/m, z0.h
+ FRINTM Z1.H, P0/M, Z0.H
+ frintm z31.h, p0/m, z0.h
+ FRINTM Z31.H, P0/M, Z0.H
+ frintm z0.h, p2/m, z0.h
+ FRINTM Z0.H, P2/M, Z0.H
+ frintm z0.h, p7/m, z0.h
+ FRINTM Z0.H, P7/M, Z0.H
+ frintm z0.h, p0/m, z3.h
+ FRINTM Z0.H, P0/M, Z3.H
+ frintm z0.h, p0/m, z31.h
+ FRINTM Z0.H, P0/M, Z31.H
frintm z0.s, p0/m, z0.s
FRINTM Z0.S, P0/M, Z0.S
frintm z1.s, p0/m, z0.s
@@ -10205,6 +11705,20 @@
FRINTM Z0.D, P0/M, Z3.D
frintm z0.d, p0/m, z31.d
FRINTM Z0.D, P0/M, Z31.D
+ frintn z0.h, p0/m, z0.h
+ FRINTN Z0.H, P0/M, Z0.H
+ frintn z1.h, p0/m, z0.h
+ FRINTN Z1.H, P0/M, Z0.H
+ frintn z31.h, p0/m, z0.h
+ FRINTN Z31.H, P0/M, Z0.H
+ frintn z0.h, p2/m, z0.h
+ FRINTN Z0.H, P2/M, Z0.H
+ frintn z0.h, p7/m, z0.h
+ FRINTN Z0.H, P7/M, Z0.H
+ frintn z0.h, p0/m, z3.h
+ FRINTN Z0.H, P0/M, Z3.H
+ frintn z0.h, p0/m, z31.h
+ FRINTN Z0.H, P0/M, Z31.H
frintn z0.s, p0/m, z0.s
FRINTN Z0.S, P0/M, Z0.S
frintn z1.s, p0/m, z0.s
@@ -10233,6 +11747,20 @@
FRINTN Z0.D, P0/M, Z3.D
frintn z0.d, p0/m, z31.d
FRINTN Z0.D, P0/M, Z31.D
+ frintp z0.h, p0/m, z0.h
+ FRINTP Z0.H, P0/M, Z0.H
+ frintp z1.h, p0/m, z0.h
+ FRINTP Z1.H, P0/M, Z0.H
+ frintp z31.h, p0/m, z0.h
+ FRINTP Z31.H, P0/M, Z0.H
+ frintp z0.h, p2/m, z0.h
+ FRINTP Z0.H, P2/M, Z0.H
+ frintp z0.h, p7/m, z0.h
+ FRINTP Z0.H, P7/M, Z0.H
+ frintp z0.h, p0/m, z3.h
+ FRINTP Z0.H, P0/M, Z3.H
+ frintp z0.h, p0/m, z31.h
+ FRINTP Z0.H, P0/M, Z31.H
frintp z0.s, p0/m, z0.s
FRINTP Z0.S, P0/M, Z0.S
frintp z1.s, p0/m, z0.s
@@ -10261,6 +11789,20 @@
FRINTP Z0.D, P0/M, Z3.D
frintp z0.d, p0/m, z31.d
FRINTP Z0.D, P0/M, Z31.D
+ frintx z0.h, p0/m, z0.h
+ FRINTX Z0.H, P0/M, Z0.H
+ frintx z1.h, p0/m, z0.h
+ FRINTX Z1.H, P0/M, Z0.H
+ frintx z31.h, p0/m, z0.h
+ FRINTX Z31.H, P0/M, Z0.H
+ frintx z0.h, p2/m, z0.h
+ FRINTX Z0.H, P2/M, Z0.H
+ frintx z0.h, p7/m, z0.h
+ FRINTX Z0.H, P7/M, Z0.H
+ frintx z0.h, p0/m, z3.h
+ FRINTX Z0.H, P0/M, Z3.H
+ frintx z0.h, p0/m, z31.h
+ FRINTX Z0.H, P0/M, Z31.H
frintx z0.s, p0/m, z0.s
FRINTX Z0.S, P0/M, Z0.S
frintx z1.s, p0/m, z0.s
@@ -10289,6 +11831,20 @@
FRINTX Z0.D, P0/M, Z3.D
frintx z0.d, p0/m, z31.d
FRINTX Z0.D, P0/M, Z31.D
+ frintz z0.h, p0/m, z0.h
+ FRINTZ Z0.H, P0/M, Z0.H
+ frintz z1.h, p0/m, z0.h
+ FRINTZ Z1.H, P0/M, Z0.H
+ frintz z31.h, p0/m, z0.h
+ FRINTZ Z31.H, P0/M, Z0.H
+ frintz z0.h, p2/m, z0.h
+ FRINTZ Z0.H, P2/M, Z0.H
+ frintz z0.h, p7/m, z0.h
+ FRINTZ Z0.H, P7/M, Z0.H
+ frintz z0.h, p0/m, z3.h
+ FRINTZ Z0.H, P0/M, Z3.H
+ frintz z0.h, p0/m, z31.h
+ FRINTZ Z0.H, P0/M, Z31.H
frintz z0.s, p0/m, z0.s
FRINTZ Z0.S, P0/M, Z0.S
frintz z1.s, p0/m, z0.s
@@ -10317,6 +11873,16 @@
FRINTZ Z0.D, P0/M, Z3.D
frintz z0.d, p0/m, z31.d
FRINTZ Z0.D, P0/M, Z31.D
+ frsqrte z0.h, z0.h
+ FRSQRTE Z0.H, Z0.H
+ frsqrte z1.h, z0.h
+ FRSQRTE Z1.H, Z0.H
+ frsqrte z31.h, z0.h
+ FRSQRTE Z31.H, Z0.H
+ frsqrte z0.h, z2.h
+ FRSQRTE Z0.H, Z2.H
+ frsqrte z0.h, z31.h
+ FRSQRTE Z0.H, Z31.H
frsqrte z0.s, z0.s
FRSQRTE Z0.S, Z0.S
frsqrte z1.s, z0.s
@@ -10337,6 +11903,20 @@
FRSQRTE Z0.D, Z2.D
frsqrte z0.d, z31.d
FRSQRTE Z0.D, Z31.D
+ frsqrts z0.h, z0.h, z0.h
+ FRSQRTS Z0.H, Z0.H, Z0.H
+ frsqrts z1.h, z0.h, z0.h
+ FRSQRTS Z1.H, Z0.H, Z0.H
+ frsqrts z31.h, z0.h, z0.h
+ FRSQRTS Z31.H, Z0.H, Z0.H
+ frsqrts z0.h, z2.h, z0.h
+ FRSQRTS Z0.H, Z2.H, Z0.H
+ frsqrts z0.h, z31.h, z0.h
+ FRSQRTS Z0.H, Z31.H, Z0.H
+ frsqrts z0.h, z0.h, z3.h
+ FRSQRTS Z0.H, Z0.H, Z3.H
+ frsqrts z0.h, z0.h, z31.h
+ FRSQRTS Z0.H, Z0.H, Z31.H
frsqrts z0.s, z0.s, z0.s
FRSQRTS Z0.S, Z0.S, Z0.S
frsqrts z1.s, z0.s, z0.s
@@ -10365,6 +11945,22 @@
FRSQRTS Z0.D, Z0.D, Z3.D
frsqrts z0.d, z0.d, z31.d
FRSQRTS Z0.D, Z0.D, Z31.D
+ fscale z0.h, p0/m, z0.h, z0.h
+ FSCALE Z0.H, P0/M, Z0.H, Z0.H
+ fscale z1.h, p0/m, z1.h, z0.h
+ FSCALE Z1.H, P0/M, Z1.H, Z0.H
+ fscale z31.h, p0/m, z31.h, z0.h
+ FSCALE Z31.H, P0/M, Z31.H, Z0.H
+ fscale z0.h, p2/m, z0.h, z0.h
+ FSCALE Z0.H, P2/M, Z0.H, Z0.H
+ fscale z0.h, p7/m, z0.h, z0.h
+ FSCALE Z0.H, P7/M, Z0.H, Z0.H
+ fscale z3.h, p0/m, z3.h, z0.h
+ FSCALE Z3.H, P0/M, Z3.H, Z0.H
+ fscale z0.h, p0/m, z0.h, z4.h
+ FSCALE Z0.H, P0/M, Z0.H, Z4.H
+ fscale z0.h, p0/m, z0.h, z31.h
+ FSCALE Z0.H, P0/M, Z0.H, Z31.H
fscale z0.s, p0/m, z0.s, z0.s
FSCALE Z0.S, P0/M, Z0.S, Z0.S
fscale z1.s, p0/m, z1.s, z0.s
@@ -10397,6 +11993,20 @@
FSCALE Z0.D, P0/M, Z0.D, Z4.D
fscale z0.d, p0/m, z0.d, z31.d
FSCALE Z0.D, P0/M, Z0.D, Z31.D
+ fsqrt z0.h, p0/m, z0.h
+ FSQRT Z0.H, P0/M, Z0.H
+ fsqrt z1.h, p0/m, z0.h
+ FSQRT Z1.H, P0/M, Z0.H
+ fsqrt z31.h, p0/m, z0.h
+ FSQRT Z31.H, P0/M, Z0.H
+ fsqrt z0.h, p2/m, z0.h
+ FSQRT Z0.H, P2/M, Z0.H
+ fsqrt z0.h, p7/m, z0.h
+ FSQRT Z0.H, P7/M, Z0.H
+ fsqrt z0.h, p0/m, z3.h
+ FSQRT Z0.H, P0/M, Z3.H
+ fsqrt z0.h, p0/m, z31.h
+ FSQRT Z0.H, P0/M, Z31.H
fsqrt z0.s, p0/m, z0.s
FSQRT Z0.S, P0/M, Z0.S
fsqrt z1.s, p0/m, z0.s
@@ -10425,6 +12035,20 @@
FSQRT Z0.D, P0/M, Z3.D
fsqrt z0.d, p0/m, z31.d
FSQRT Z0.D, P0/M, Z31.D
+ fsub z0.h, z0.h, z0.h
+ FSUB Z0.H, Z0.H, Z0.H
+ fsub z1.h, z0.h, z0.h
+ FSUB Z1.H, Z0.H, Z0.H
+ fsub z31.h, z0.h, z0.h
+ FSUB Z31.H, Z0.H, Z0.H
+ fsub z0.h, z2.h, z0.h
+ FSUB Z0.H, Z2.H, Z0.H
+ fsub z0.h, z31.h, z0.h
+ FSUB Z0.H, Z31.H, Z0.H
+ fsub z0.h, z0.h, z3.h
+ FSUB Z0.H, Z0.H, Z3.H
+ fsub z0.h, z0.h, z31.h
+ FSUB Z0.H, Z0.H, Z31.H
fsub z0.s, z0.s, z0.s
FSUB Z0.S, Z0.S, Z0.S
fsub z1.s, z0.s, z0.s
@@ -10453,6 +12077,22 @@
FSUB Z0.D, Z0.D, Z3.D
fsub z0.d, z0.d, z31.d
FSUB Z0.D, Z0.D, Z31.D
+ fsub z0.h, p0/m, z0.h, z0.h
+ FSUB Z0.H, P0/M, Z0.H, Z0.H
+ fsub z1.h, p0/m, z1.h, z0.h
+ FSUB Z1.H, P0/M, Z1.H, Z0.H
+ fsub z31.h, p0/m, z31.h, z0.h
+ FSUB Z31.H, P0/M, Z31.H, Z0.H
+ fsub z0.h, p2/m, z0.h, z0.h
+ FSUB Z0.H, P2/M, Z0.H, Z0.H
+ fsub z0.h, p7/m, z0.h, z0.h
+ FSUB Z0.H, P7/M, Z0.H, Z0.H
+ fsub z3.h, p0/m, z3.h, z0.h
+ FSUB Z3.H, P0/M, Z3.H, Z0.H
+ fsub z0.h, p0/m, z0.h, z4.h
+ FSUB Z0.H, P0/M, Z0.H, Z4.H
+ fsub z0.h, p0/m, z0.h, z31.h
+ FSUB Z0.H, P0/M, Z0.H, Z31.H
fsub z0.s, p0/m, z0.s, z0.s
FSUB Z0.S, P0/M, Z0.S, Z0.S
fsub z1.s, p0/m, z1.s, z0.s
@@ -10485,6 +12125,34 @@
FSUB Z0.D, P0/M, Z0.D, Z4.D
fsub z0.d, p0/m, z0.d, z31.d
FSUB Z0.D, P0/M, Z0.D, Z31.D
+ fsub z0.h, p0/m, z0.h, #0.5
+ FSUB Z0.H, P0/M, Z0.H, #0.5
+ fsub z0.h, p0/m, z0.h, #0.50000
+ fsub z0.h, p0/m, z0.h, #5.0000000000e-01
+ fsub z1.h, p0/m, z1.h, #0.5
+ FSUB Z1.H, P0/M, Z1.H, #0.5
+ fsub z1.h, p0/m, z1.h, #0.50000
+ fsub z1.h, p0/m, z1.h, #5.0000000000e-01
+ fsub z31.h, p0/m, z31.h, #0.5
+ FSUB Z31.H, P0/M, Z31.H, #0.5
+ fsub z31.h, p0/m, z31.h, #0.50000
+ fsub z31.h, p0/m, z31.h, #5.0000000000e-01
+ fsub z0.h, p2/m, z0.h, #0.5
+ FSUB Z0.H, P2/M, Z0.H, #0.5
+ fsub z0.h, p2/m, z0.h, #0.50000
+ fsub z0.h, p2/m, z0.h, #5.0000000000e-01
+ fsub z0.h, p7/m, z0.h, #0.5
+ FSUB Z0.H, P7/M, Z0.H, #0.5
+ fsub z0.h, p7/m, z0.h, #0.50000
+ fsub z0.h, p7/m, z0.h, #5.0000000000e-01
+ fsub z3.h, p0/m, z3.h, #0.5
+ FSUB Z3.H, P0/M, Z3.H, #0.5
+ fsub z3.h, p0/m, z3.h, #0.50000
+ fsub z3.h, p0/m, z3.h, #5.0000000000e-01
+ fsub z0.h, p0/m, z0.h, #1.0
+ FSUB Z0.H, P0/M, Z0.H, #1.0
+ fsub z0.h, p0/m, z0.h, #1.00000
+ fsub z0.h, p0/m, z0.h, #1.0000000000e+00
fsub z0.s, p0/m, z0.s, #0.5
FSUB Z0.S, P0/M, Z0.S, #0.5
fsub z0.s, p0/m, z0.s, #0.50000
@@ -10541,6 +12209,22 @@
FSUB Z0.D, P0/M, Z0.D, #1.0
fsub z0.d, p0/m, z0.d, #1.00000
fsub z0.d, p0/m, z0.d, #1.0000000000e+00
+ fsubr z0.h, p0/m, z0.h, z0.h
+ FSUBR Z0.H, P0/M, Z0.H, Z0.H
+ fsubr z1.h, p0/m, z1.h, z0.h
+ FSUBR Z1.H, P0/M, Z1.H, Z0.H
+ fsubr z31.h, p0/m, z31.h, z0.h
+ FSUBR Z31.H, P0/M, Z31.H, Z0.H
+ fsubr z0.h, p2/m, z0.h, z0.h
+ FSUBR Z0.H, P2/M, Z0.H, Z0.H
+ fsubr z0.h, p7/m, z0.h, z0.h
+ FSUBR Z0.H, P7/M, Z0.H, Z0.H
+ fsubr z3.h, p0/m, z3.h, z0.h
+ FSUBR Z3.H, P0/M, Z3.H, Z0.H
+ fsubr z0.h, p0/m, z0.h, z4.h
+ FSUBR Z0.H, P0/M, Z0.H, Z4.H
+ fsubr z0.h, p0/m, z0.h, z31.h
+ FSUBR Z0.H, P0/M, Z0.H, Z31.H
fsubr z0.s, p0/m, z0.s, z0.s
FSUBR Z0.S, P0/M, Z0.S, Z0.S
fsubr z1.s, p0/m, z1.s, z0.s
@@ -10573,6 +12257,34 @@
FSUBR Z0.D, P0/M, Z0.D, Z4.D
fsubr z0.d, p0/m, z0.d, z31.d
FSUBR Z0.D, P0/M, Z0.D, Z31.D
+ fsubr z0.h, p0/m, z0.h, #0.5
+ FSUBR Z0.H, P0/M, Z0.H, #0.5
+ fsubr z0.h, p0/m, z0.h, #0.50000
+ fsubr z0.h, p0/m, z0.h, #5.0000000000e-01
+ fsubr z1.h, p0/m, z1.h, #0.5
+ FSUBR Z1.H, P0/M, Z1.H, #0.5
+ fsubr z1.h, p0/m, z1.h, #0.50000
+ fsubr z1.h, p0/m, z1.h, #5.0000000000e-01
+ fsubr z31.h, p0/m, z31.h, #0.5
+ FSUBR Z31.H, P0/M, Z31.H, #0.5
+ fsubr z31.h, p0/m, z31.h, #0.50000
+ fsubr z31.h, p0/m, z31.h, #5.0000000000e-01
+ fsubr z0.h, p2/m, z0.h, #0.5
+ FSUBR Z0.H, P2/M, Z0.H, #0.5
+ fsubr z0.h, p2/m, z0.h, #0.50000
+ fsubr z0.h, p2/m, z0.h, #5.0000000000e-01
+ fsubr z0.h, p7/m, z0.h, #0.5
+ FSUBR Z0.H, P7/M, Z0.H, #0.5
+ fsubr z0.h, p7/m, z0.h, #0.50000
+ fsubr z0.h, p7/m, z0.h, #5.0000000000e-01
+ fsubr z3.h, p0/m, z3.h, #0.5
+ FSUBR Z3.H, P0/M, Z3.H, #0.5
+ fsubr z3.h, p0/m, z3.h, #0.50000
+ fsubr z3.h, p0/m, z3.h, #5.0000000000e-01
+ fsubr z0.h, p0/m, z0.h, #1.0
+ FSUBR Z0.H, P0/M, Z0.H, #1.0
+ fsubr z0.h, p0/m, z0.h, #1.00000
+ fsubr z0.h, p0/m, z0.h, #1.0000000000e+00
fsubr z0.s, p0/m, z0.s, #0.5
FSUBR Z0.S, P0/M, Z0.S, #0.5
fsubr z0.s, p0/m, z0.s, #0.50000
@@ -10629,6 +12341,26 @@
FSUBR Z0.D, P0/M, Z0.D, #1.0
fsubr z0.d, p0/m, z0.d, #1.00000
fsubr z0.d, p0/m, z0.d, #1.0000000000e+00
+ ftmad z0.h, z0.h, z0.h, #0
+ FTMAD Z0.H, Z0.H, Z0.H, #0
+ ftmad z1.h, z1.h, z0.h, #0
+ FTMAD Z1.H, Z1.H, Z0.H, #0
+ ftmad z31.h, z31.h, z0.h, #0
+ FTMAD Z31.H, Z31.H, Z0.H, #0
+ ftmad z2.h, z2.h, z0.h, #0
+ FTMAD Z2.H, Z2.H, Z0.H, #0
+ ftmad z0.h, z0.h, z3.h, #0
+ FTMAD Z0.H, Z0.H, Z3.H, #0
+ ftmad z0.h, z0.h, z31.h, #0
+ FTMAD Z0.H, Z0.H, Z31.H, #0
+ ftmad z0.h, z0.h, z0.h, #3
+ FTMAD Z0.H, Z0.H, Z0.H, #3
+ ftmad z0.h, z0.h, z0.h, #4
+ FTMAD Z0.H, Z0.H, Z0.H, #4
+ ftmad z0.h, z0.h, z0.h, #5
+ FTMAD Z0.H, Z0.H, Z0.H, #5
+ ftmad z0.h, z0.h, z0.h, #7
+ FTMAD Z0.H, Z0.H, Z0.H, #7
ftmad z0.s, z0.s, z0.s, #0
FTMAD Z0.S, Z0.S, Z0.S, #0
ftmad z1.s, z1.s, z0.s, #0
@@ -10669,6 +12401,20 @@
FTMAD Z0.D, Z0.D, Z0.D, #5
ftmad z0.d, z0.d, z0.d, #7
FTMAD Z0.D, Z0.D, Z0.D, #7
+ ftsmul z0.h, z0.h, z0.h
+ FTSMUL Z0.H, Z0.H, Z0.H
+ ftsmul z1.h, z0.h, z0.h
+ FTSMUL Z1.H, Z0.H, Z0.H
+ ftsmul z31.h, z0.h, z0.h
+ FTSMUL Z31.H, Z0.H, Z0.H
+ ftsmul z0.h, z2.h, z0.h
+ FTSMUL Z0.H, Z2.H, Z0.H
+ ftsmul z0.h, z31.h, z0.h
+ FTSMUL Z0.H, Z31.H, Z0.H
+ ftsmul z0.h, z0.h, z3.h
+ FTSMUL Z0.H, Z0.H, Z3.H
+ ftsmul z0.h, z0.h, z31.h
+ FTSMUL Z0.H, Z0.H, Z31.H
ftsmul z0.s, z0.s, z0.s
FTSMUL Z0.S, Z0.S, Z0.S
ftsmul z1.s, z0.s, z0.s
@@ -10697,6 +12443,20 @@
FTSMUL Z0.D, Z0.D, Z3.D
ftsmul z0.d, z0.d, z31.d
FTSMUL Z0.D, Z0.D, Z31.D
+ ftssel z0.h, z0.h, z0.h
+ FTSSEL Z0.H, Z0.H, Z0.H
+ ftssel z1.h, z0.h, z0.h
+ FTSSEL Z1.H, Z0.H, Z0.H
+ ftssel z31.h, z0.h, z0.h
+ FTSSEL Z31.H, Z0.H, Z0.H
+ ftssel z0.h, z2.h, z0.h
+ FTSSEL Z0.H, Z2.H, Z0.H
+ ftssel z0.h, z31.h, z0.h
+ FTSSEL Z0.H, Z31.H, Z0.H
+ ftssel z0.h, z0.h, z3.h
+ FTSSEL Z0.H, Z0.H, Z3.H
+ ftssel z0.h, z0.h, z31.h
+ FTSSEL Z0.H, Z0.H, Z31.H
ftssel z0.s, z0.s, z0.s
FTSSEL Z0.S, Z0.S, Z0.S
ftssel z1.s, z0.s, z0.s
@@ -13846,6 +15606,227 @@
LD1RSW {Z0.D}, P0/Z, [X0,#132]
ld1rsw {z0.d}, p0/z, [x0,#252]
LD1RSW {Z0.D}, P0/Z, [X0,#252]
+ ld1rqb z0.b, p0/z, [x0,#0]
+ ld1rqb {z0.b}, p0/z, [x0,#0]
+ LD1RQB {Z0.B}, P0/Z, [X0,#0]
+ ld1rqb {z0.b}, p0/z, [x0]
+ ld1rqb z1.b, p0/z, [x0,#0]
+ ld1rqb {z1.b}, p0/z, [x0,#0]
+ LD1RQB {Z1.B}, P0/Z, [X0,#0]
+ ld1rqb {z1.b}, p0/z, [x0]
+ ld1rqb z31.b, p0/z, [x0,#0]
+ ld1rqb {z31.b}, p0/z, [x0,#0]
+ LD1RQB {Z31.B}, P0/Z, [X0,#0]
+ ld1rqb {z31.b}, p0/z, [x0]
+ ld1rqb {z0.b}, p2/z, [x0,#0]
+ LD1RQB {Z0.B}, P2/Z, [X0,#0]
+ ld1rqb {z0.b}, p2/z, [x0]
+ ld1rqb {z0.b}, p7/z, [x0,#0]
+ LD1RQB {Z0.B}, P7/Z, [X0,#0]
+ ld1rqb {z0.b}, p7/z, [x0]
+ ld1rqb {z0.b}, p0/z, [x3,#0]
+ LD1RQB {Z0.B}, P0/Z, [X3,#0]
+ ld1rqb {z0.b}, p0/z, [x3]
+ ld1rqb {z0.b}, p0/z, [sp,#0]
+ LD1RQB {Z0.B}, P0/Z, [SP,#0]
+ ld1rqb {z0.b}, p0/z, [sp]
+ ld1rqb {z0.b}, p0/z, [x0,#-128]
+ LD1RQB {Z0.B}, P0/Z, [X0,#-128]
+ ld1rqb {z0.b}, p0/z, [x0,#-16]
+ LD1RQB {Z0.B}, P0/Z, [X0,#-16]
+ ld1rqb {z0.b}, p0/z, [x0,#16]
+ LD1RQB {Z0.B}, P0/Z, [X0,#16]
+ ld1rqb {z0.b}, p0/z, [x0,#112]
+ LD1RQB {Z0.B}, P0/Z, [X0,#112]
+ ld1rqb z0.b, p0/z, [x0,x0]
+ ld1rqb {z0.b}, p0/z, [x0,x0]
+ LD1RQB {Z0.B}, P0/Z, [X0,X0]
+ ld1rqb {z0.b}, p0/z, [x0,x0,lsl #0]
+ ld1rqb z1.b, p0/z, [x0,x0]
+ ld1rqb {z1.b}, p0/z, [x0,x0]
+ LD1RQB {Z1.B}, P0/Z, [X0,X0]
+ ld1rqb {z1.b}, p0/z, [x0,x0,lsl #0]
+ ld1rqb z31.b, p0/z, [x0,x0]
+ ld1rqb {z31.b}, p0/z, [x0,x0]
+ LD1RQB {Z31.B}, P0/Z, [X0,X0]
+ ld1rqb {z31.b}, p0/z, [x0,x0,lsl #0]
+ ld1rqb {z0.b}, p2/z, [x0,x0]
+ LD1RQB {Z0.B}, P2/Z, [X0,X0]
+ ld1rqb {z0.b}, p2/z, [x0,x0,lsl #0]
+ ld1rqb {z0.b}, p7/z, [x0,x0]
+ LD1RQB {Z0.B}, P7/Z, [X0,X0]
+ ld1rqb {z0.b}, p7/z, [x0,x0,lsl #0]
+ ld1rqb {z0.b}, p0/z, [x3,x0]
+ LD1RQB {Z0.B}, P0/Z, [X3,X0]
+ ld1rqb {z0.b}, p0/z, [x3,x0,lsl #0]
+ ld1rqb {z0.b}, p0/z, [sp,x0]
+ LD1RQB {Z0.B}, P0/Z, [SP,X0]
+ ld1rqb {z0.b}, p0/z, [sp,x0,lsl #0]
+ ld1rqb {z0.b}, p0/z, [x0,x4]
+ LD1RQB {Z0.B}, P0/Z, [X0,X4]
+ ld1rqb {z0.b}, p0/z, [x0,x4,lsl #0]
+ ld1rqb {z0.b}, p0/z, [x0,x30]
+ LD1RQB {Z0.B}, P0/Z, [X0,X30]
+ ld1rqb {z0.b}, p0/z, [x0,x30,lsl #0]
+ ld1rqd z0.d, p0/z, [x0,#0]
+ ld1rqd {z0.d}, p0/z, [x0,#0]
+ LD1RQD {Z0.D}, P0/Z, [X0,#0]
+ ld1rqd {z0.d}, p0/z, [x0]
+ ld1rqd z1.d, p0/z, [x0,#0]
+ ld1rqd {z1.d}, p0/z, [x0,#0]
+ LD1RQD {Z1.D}, P0/Z, [X0,#0]
+ ld1rqd {z1.d}, p0/z, [x0]
+ ld1rqd z31.d, p0/z, [x0,#0]
+ ld1rqd {z31.d}, p0/z, [x0,#0]
+ LD1RQD {Z31.D}, P0/Z, [X0,#0]
+ ld1rqd {z31.d}, p0/z, [x0]
+ ld1rqd {z0.d}, p2/z, [x0,#0]
+ LD1RQD {Z0.D}, P2/Z, [X0,#0]
+ ld1rqd {z0.d}, p2/z, [x0]
+ ld1rqd {z0.d}, p7/z, [x0,#0]
+ LD1RQD {Z0.D}, P7/Z, [X0,#0]
+ ld1rqd {z0.d}, p7/z, [x0]
+ ld1rqd {z0.d}, p0/z, [x3,#0]
+ LD1RQD {Z0.D}, P0/Z, [X3,#0]
+ ld1rqd {z0.d}, p0/z, [x3]
+ ld1rqd {z0.d}, p0/z, [sp,#0]
+ LD1RQD {Z0.D}, P0/Z, [SP,#0]
+ ld1rqd {z0.d}, p0/z, [sp]
+ ld1rqd {z0.d}, p0/z, [x0,#-128]
+ LD1RQD {Z0.D}, P0/Z, [X0,#-128]
+ ld1rqd {z0.d}, p0/z, [x0,#-16]
+ LD1RQD {Z0.D}, P0/Z, [X0,#-16]
+ ld1rqd {z0.d}, p0/z, [x0,#16]
+ LD1RQD {Z0.D}, P0/Z, [X0,#16]
+ ld1rqd {z0.d}, p0/z, [x0,#112]
+ LD1RQD {Z0.D}, P0/Z, [X0,#112]
+ ld1rqd z0.d, p0/z, [x0,x0,lsl #3]
+ ld1rqd {z0.d}, p0/z, [x0,x0,lsl #3]
+ LD1RQD {Z0.D}, P0/Z, [X0,X0,LSL #3]
+ ld1rqd z1.d, p0/z, [x0,x0,lsl #3]
+ ld1rqd {z1.d}, p0/z, [x0,x0,lsl #3]
+ LD1RQD {Z1.D}, P0/Z, [X0,X0,LSL #3]
+ ld1rqd z31.d, p0/z, [x0,x0,lsl #3]
+ ld1rqd {z31.d}, p0/z, [x0,x0,lsl #3]
+ LD1RQD {Z31.D}, P0/Z, [X0,X0,LSL #3]
+ ld1rqd {z0.d}, p2/z, [x0,x0,lsl #3]
+ LD1RQD {Z0.D}, P2/Z, [X0,X0,LSL #3]
+ ld1rqd {z0.d}, p7/z, [x0,x0,lsl #3]
+ LD1RQD {Z0.D}, P7/Z, [X0,X0,LSL #3]
+ ld1rqd {z0.d}, p0/z, [x3,x0,lsl #3]
+ LD1RQD {Z0.D}, P0/Z, [X3,X0,LSL #3]
+ ld1rqd {z0.d}, p0/z, [sp,x0,lsl #3]
+ LD1RQD {Z0.D}, P0/Z, [SP,X0,LSL #3]
+ ld1rqd {z0.d}, p0/z, [x0,x4,lsl #3]
+ LD1RQD {Z0.D}, P0/Z, [X0,X4,LSL #3]
+ ld1rqd {z0.d}, p0/z, [x0,x30,lsl #3]
+ LD1RQD {Z0.D}, P0/Z, [X0,X30,LSL #3]
+ ld1rqh z0.h, p0/z, [x0,#0]
+ ld1rqh {z0.h}, p0/z, [x0,#0]
+ LD1RQH {Z0.H}, P0/Z, [X0,#0]
+ ld1rqh {z0.h}, p0/z, [x0]
+ ld1rqh z1.h, p0/z, [x0,#0]
+ ld1rqh {z1.h}, p0/z, [x0,#0]
+ LD1RQH {Z1.H}, P0/Z, [X0,#0]
+ ld1rqh {z1.h}, p0/z, [x0]
+ ld1rqh z31.h, p0/z, [x0,#0]
+ ld1rqh {z31.h}, p0/z, [x0,#0]
+ LD1RQH {Z31.H}, P0/Z, [X0,#0]
+ ld1rqh {z31.h}, p0/z, [x0]
+ ld1rqh {z0.h}, p2/z, [x0,#0]
+ LD1RQH {Z0.H}, P2/Z, [X0,#0]
+ ld1rqh {z0.h}, p2/z, [x0]
+ ld1rqh {z0.h}, p7/z, [x0,#0]
+ LD1RQH {Z0.H}, P7/Z, [X0,#0]
+ ld1rqh {z0.h}, p7/z, [x0]
+ ld1rqh {z0.h}, p0/z, [x3,#0]
+ LD1RQH {Z0.H}, P0/Z, [X3,#0]
+ ld1rqh {z0.h}, p0/z, [x3]
+ ld1rqh {z0.h}, p0/z, [sp,#0]
+ LD1RQH {Z0.H}, P0/Z, [SP,#0]
+ ld1rqh {z0.h}, p0/z, [sp]
+ ld1rqh {z0.h}, p0/z, [x0,#-128]
+ LD1RQH {Z0.H}, P0/Z, [X0,#-128]
+ ld1rqh {z0.h}, p0/z, [x0,#-16]
+ LD1RQH {Z0.H}, P0/Z, [X0,#-16]
+ ld1rqh {z0.h}, p0/z, [x0,#16]
+ LD1RQH {Z0.H}, P0/Z, [X0,#16]
+ ld1rqh {z0.h}, p0/z, [x0,#112]
+ LD1RQH {Z0.H}, P0/Z, [X0,#112]
+ ld1rqh z0.h, p0/z, [x0,x0,lsl #1]
+ ld1rqh {z0.h}, p0/z, [x0,x0,lsl #1]
+ LD1RQH {Z0.H}, P0/Z, [X0,X0,LSL #1]
+ ld1rqh z1.h, p0/z, [x0,x0,lsl #1]
+ ld1rqh {z1.h}, p0/z, [x0,x0,lsl #1]
+ LD1RQH {Z1.H}, P0/Z, [X0,X0,LSL #1]
+ ld1rqh z31.h, p0/z, [x0,x0,lsl #1]
+ ld1rqh {z31.h}, p0/z, [x0,x0,lsl #1]
+ LD1RQH {Z31.H}, P0/Z, [X0,X0,LSL #1]
+ ld1rqh {z0.h}, p2/z, [x0,x0,lsl #1]
+ LD1RQH {Z0.H}, P2/Z, [X0,X0,LSL #1]
+ ld1rqh {z0.h}, p7/z, [x0,x0,lsl #1]
+ LD1RQH {Z0.H}, P7/Z, [X0,X0,LSL #1]
+ ld1rqh {z0.h}, p0/z, [x3,x0,lsl #1]
+ LD1RQH {Z0.H}, P0/Z, [X3,X0,LSL #1]
+ ld1rqh {z0.h}, p0/z, [sp,x0,lsl #1]
+ LD1RQH {Z0.H}, P0/Z, [SP,X0,LSL #1]
+ ld1rqh {z0.h}, p0/z, [x0,x4,lsl #1]
+ LD1RQH {Z0.H}, P0/Z, [X0,X4,LSL #1]
+ ld1rqh {z0.h}, p0/z, [x0,x30,lsl #1]
+ LD1RQH {Z0.H}, P0/Z, [X0,X30,LSL #1]
+ ld1rqw z0.s, p0/z, [x0,#0]
+ ld1rqw {z0.s}, p0/z, [x0,#0]
+ LD1RQW {Z0.S}, P0/Z, [X0,#0]
+ ld1rqw {z0.s}, p0/z, [x0]
+ ld1rqw z1.s, p0/z, [x0,#0]
+ ld1rqw {z1.s}, p0/z, [x0,#0]
+ LD1RQW {Z1.S}, P0/Z, [X0,#0]
+ ld1rqw {z1.s}, p0/z, [x0]
+ ld1rqw z31.s, p0/z, [x0,#0]
+ ld1rqw {z31.s}, p0/z, [x0,#0]
+ LD1RQW {Z31.S}, P0/Z, [X0,#0]
+ ld1rqw {z31.s}, p0/z, [x0]
+ ld1rqw {z0.s}, p2/z, [x0,#0]
+ LD1RQW {Z0.S}, P2/Z, [X0,#0]
+ ld1rqw {z0.s}, p2/z, [x0]
+ ld1rqw {z0.s}, p7/z, [x0,#0]
+ LD1RQW {Z0.S}, P7/Z, [X0,#0]
+ ld1rqw {z0.s}, p7/z, [x0]
+ ld1rqw {z0.s}, p0/z, [x3,#0]
+ LD1RQW {Z0.S}, P0/Z, [X3,#0]
+ ld1rqw {z0.s}, p0/z, [x3]
+ ld1rqw {z0.s}, p0/z, [sp,#0]
+ LD1RQW {Z0.S}, P0/Z, [SP,#0]
+ ld1rqw {z0.s}, p0/z, [sp]
+ ld1rqw {z0.s}, p0/z, [x0,#-128]
+ LD1RQW {Z0.S}, P0/Z, [X0,#-128]
+ ld1rqw {z0.s}, p0/z, [x0,#-16]
+ LD1RQW {Z0.S}, P0/Z, [X0,#-16]
+ ld1rqw {z0.s}, p0/z, [x0,#16]
+ LD1RQW {Z0.S}, P0/Z, [X0,#16]
+ ld1rqw {z0.s}, p0/z, [x0,#112]
+ LD1RQW {Z0.S}, P0/Z, [X0,#112]
+ ld1rqw z0.s, p0/z, [x0,x0,lsl #2]
+ ld1rqw {z0.s}, p0/z, [x0,x0,lsl #2]
+ LD1RQW {Z0.S}, P0/Z, [X0,X0,LSL #2]
+ ld1rqw z1.s, p0/z, [x0,x0,lsl #2]
+ ld1rqw {z1.s}, p0/z, [x0,x0,lsl #2]
+ LD1RQW {Z1.S}, P0/Z, [X0,X0,LSL #2]
+ ld1rqw z31.s, p0/z, [x0,x0,lsl #2]
+ ld1rqw {z31.s}, p0/z, [x0,x0,lsl #2]
+ LD1RQW {Z31.S}, P0/Z, [X0,X0,LSL #2]
+ ld1rqw {z0.s}, p2/z, [x0,x0,lsl #2]
+ LD1RQW {Z0.S}, P2/Z, [X0,X0,LSL #2]
+ ld1rqw {z0.s}, p7/z, [x0,x0,lsl #2]
+ LD1RQW {Z0.S}, P7/Z, [X0,X0,LSL #2]
+ ld1rqw {z0.s}, p0/z, [x3,x0,lsl #2]
+ LD1RQW {Z0.S}, P0/Z, [X3,X0,LSL #2]
+ ld1rqw {z0.s}, p0/z, [sp,x0,lsl #2]
+ LD1RQW {Z0.S}, P0/Z, [SP,X0,LSL #2]
+ ld1rqw {z0.s}, p0/z, [x0,x4,lsl #2]
+ LD1RQW {Z0.S}, P0/Z, [X0,X4,LSL #2]
+ ld1rqw {z0.s}, p0/z, [x0,x30,lsl #2]
+ LD1RQW {Z0.S}, P0/Z, [X0,X30,LSL #2]
ld1rw z0.s, p0/z, [x0,#0]
ld1rw {z0.s}, p0/z, [x0,#0]
LD1RW {Z0.S}, P0/Z, [X0,#0]
@@ -25027,6 +27008,34 @@
SADDV D0, P0, Z3.S
saddv d0, p0, z31.s
SADDV D0, P0, Z31.S
+ scvtf z0.h, p0/m, z0.h
+ SCVTF Z0.H, P0/M, Z0.H
+ scvtf z1.h, p0/m, z0.h
+ SCVTF Z1.H, P0/M, Z0.H
+ scvtf z31.h, p0/m, z0.h
+ SCVTF Z31.H, P0/M, Z0.H
+ scvtf z0.h, p2/m, z0.h
+ SCVTF Z0.H, P2/M, Z0.H
+ scvtf z0.h, p7/m, z0.h
+ SCVTF Z0.H, P7/M, Z0.H
+ scvtf z0.h, p0/m, z3.h
+ SCVTF Z0.H, P0/M, Z3.H
+ scvtf z0.h, p0/m, z31.h
+ SCVTF Z0.H, P0/M, Z31.H
+ scvtf z0.h, p0/m, z0.s
+ SCVTF Z0.H, P0/M, Z0.S
+ scvtf z1.h, p0/m, z0.s
+ SCVTF Z1.H, P0/M, Z0.S
+ scvtf z31.h, p0/m, z0.s
+ SCVTF Z31.H, P0/M, Z0.S
+ scvtf z0.h, p2/m, z0.s
+ SCVTF Z0.H, P2/M, Z0.S
+ scvtf z0.h, p7/m, z0.s
+ SCVTF Z0.H, P7/M, Z0.S
+ scvtf z0.h, p0/m, z3.s
+ SCVTF Z0.H, P0/M, Z3.S
+ scvtf z0.h, p0/m, z31.s
+ SCVTF Z0.H, P0/M, Z31.S
scvtf z0.s, p0/m, z0.s
SCVTF Z0.S, P0/M, Z0.S
scvtf z1.s, p0/m, z0.s
@@ -25055,6 +27064,20 @@
SCVTF Z0.D, P0/M, Z3.S
scvtf z0.d, p0/m, z31.s
SCVTF Z0.D, P0/M, Z31.S
+ scvtf z0.h, p0/m, z0.d
+ SCVTF Z0.H, P0/M, Z0.D
+ scvtf z1.h, p0/m, z0.d
+ SCVTF Z1.H, P0/M, Z0.D
+ scvtf z31.h, p0/m, z0.d
+ SCVTF Z31.H, P0/M, Z0.D
+ scvtf z0.h, p2/m, z0.d
+ SCVTF Z0.H, P2/M, Z0.D
+ scvtf z0.h, p7/m, z0.d
+ SCVTF Z0.H, P7/M, Z0.D
+ scvtf z0.h, p0/m, z3.d
+ SCVTF Z0.H, P0/M, Z3.D
+ scvtf z0.h, p0/m, z31.d
+ SCVTF Z0.H, P0/M, Z31.D
scvtf z0.s, p0/m, z0.d
SCVTF Z0.S, P0/M, Z0.D
scvtf z1.s, p0/m, z0.d
@@ -25147,6 +27170,76 @@
SDIVR Z0.D, P0/M, Z0.D, Z4.D
sdivr z0.d, p0/m, z0.d, z31.d
SDIVR Z0.D, P0/M, Z0.D, Z31.D
+ sdot z0.s, z0.b, z0.b
+ SDOT Z0.S, Z0.B, Z0.B
+ sdot z1.s, z0.b, z0.b
+ SDOT Z1.S, Z0.B, Z0.B
+ sdot z31.s, z0.b, z0.b
+ SDOT Z31.S, Z0.B, Z0.B
+ sdot z0.s, z2.b, z0.b
+ SDOT Z0.S, Z2.B, Z0.B
+ sdot z0.s, z31.b, z0.b
+ SDOT Z0.S, Z31.B, Z0.B
+ sdot z0.s, z0.b, z3.b
+ SDOT Z0.S, Z0.B, Z3.B
+ sdot z0.s, z0.b, z31.b
+ SDOT Z0.S, Z0.B, Z31.B
+ sdot z0.d, z0.h, z0.h
+ SDOT Z0.D, Z0.H, Z0.H
+ sdot z1.d, z0.h, z0.h
+ SDOT Z1.D, Z0.H, Z0.H
+ sdot z31.d, z0.h, z0.h
+ SDOT Z31.D, Z0.H, Z0.H
+ sdot z0.d, z2.h, z0.h
+ SDOT Z0.D, Z2.H, Z0.H
+ sdot z0.d, z31.h, z0.h
+ SDOT Z0.D, Z31.H, Z0.H
+ sdot z0.d, z0.h, z3.h
+ SDOT Z0.D, Z0.H, Z3.H
+ sdot z0.d, z0.h, z31.h
+ SDOT Z0.D, Z0.H, Z31.H
+ sdot z0.s, z0.b, z0.b[0]
+ SDOT Z0.S, Z0.B, Z0.B[0]
+ sdot z1.s, z0.b, z0.b[0]
+ SDOT Z1.S, Z0.B, Z0.B[0]
+ sdot z31.s, z0.b, z0.b[0]
+ SDOT Z31.S, Z0.B, Z0.B[0]
+ sdot z0.s, z2.b, z0.b[0]
+ SDOT Z0.S, Z2.B, Z0.B[0]
+ sdot z0.s, z31.b, z0.b[0]
+ SDOT Z0.S, Z31.B, Z0.B[0]
+ sdot z0.s, z0.b, z3.b[0]
+ SDOT Z0.S, Z0.B, Z3.B[0]
+ sdot z0.s, z0.b, z7.b[0]
+ SDOT Z0.S, Z0.B, Z7.B[0]
+ sdot z0.s, z0.b, z0.b[1]
+ SDOT Z0.S, Z0.B, Z0.B[1]
+ sdot z0.s, z0.b, z4.b[1]
+ SDOT Z0.S, Z0.B, Z4.B[1]
+ sdot z0.s, z0.b, z3.b[2]
+ SDOT Z0.S, Z0.B, Z3.B[2]
+ sdot z0.s, z0.b, z0.b[3]
+ SDOT Z0.S, Z0.B, Z0.B[3]
+ sdot z0.s, z0.b, z5.b[3]
+ SDOT Z0.S, Z0.B, Z5.B[3]
+ sdot z0.d, z0.h, z0.h[0]
+ SDOT Z0.D, Z0.H, Z0.H[0]
+ sdot z1.d, z0.h, z0.h[0]
+ SDOT Z1.D, Z0.H, Z0.H[0]
+ sdot z31.d, z0.h, z0.h[0]
+ SDOT Z31.D, Z0.H, Z0.H[0]
+ sdot z0.d, z2.h, z0.h[0]
+ SDOT Z0.D, Z2.H, Z0.H[0]
+ sdot z0.d, z31.h, z0.h[0]
+ SDOT Z0.D, Z31.H, Z0.H[0]
+ sdot z0.d, z0.h, z3.h[0]
+ SDOT Z0.D, Z0.H, Z3.H[0]
+ sdot z0.d, z0.h, z15.h[0]
+ SDOT Z0.D, Z0.H, Z15.H[0]
+ sdot z0.d, z0.h, z0.h[1]
+ SDOT Z0.D, Z0.H, Z0.H[1]
+ sdot z0.d, z0.h, z11.h[1]
+ SDOT Z0.D, Z0.H, Z11.H[1]
sel z0.b, p0, z0.b, z0.b
SEL Z0.B, P0, Z0.B, Z0.B
sel z1.b, p0, z0.b, z0.b
@@ -32926,6 +35019,34 @@
UADDV D0, P0, Z3.D
uaddv d0, p0, z31.d
UADDV D0, P0, Z31.D
+ ucvtf z0.h, p0/m, z0.h
+ UCVTF Z0.H, P0/M, Z0.H
+ ucvtf z1.h, p0/m, z0.h
+ UCVTF Z1.H, P0/M, Z0.H
+ ucvtf z31.h, p0/m, z0.h
+ UCVTF Z31.H, P0/M, Z0.H
+ ucvtf z0.h, p2/m, z0.h
+ UCVTF Z0.H, P2/M, Z0.H
+ ucvtf z0.h, p7/m, z0.h
+ UCVTF Z0.H, P7/M, Z0.H
+ ucvtf z0.h, p0/m, z3.h
+ UCVTF Z0.H, P0/M, Z3.H
+ ucvtf z0.h, p0/m, z31.h
+ UCVTF Z0.H, P0/M, Z31.H
+ ucvtf z0.h, p0/m, z0.s
+ UCVTF Z0.H, P0/M, Z0.S
+ ucvtf z1.h, p0/m, z0.s
+ UCVTF Z1.H, P0/M, Z0.S
+ ucvtf z31.h, p0/m, z0.s
+ UCVTF Z31.H, P0/M, Z0.S
+ ucvtf z0.h, p2/m, z0.s
+ UCVTF Z0.H, P2/M, Z0.S
+ ucvtf z0.h, p7/m, z0.s
+ UCVTF Z0.H, P7/M, Z0.S
+ ucvtf z0.h, p0/m, z3.s
+ UCVTF Z0.H, P0/M, Z3.S
+ ucvtf z0.h, p0/m, z31.s
+ UCVTF Z0.H, P0/M, Z31.S
ucvtf z0.s, p0/m, z0.s
UCVTF Z0.S, P0/M, Z0.S
ucvtf z1.s, p0/m, z0.s
@@ -32954,6 +35075,20 @@
UCVTF Z0.D, P0/M, Z3.S
ucvtf z0.d, p0/m, z31.s
UCVTF Z0.D, P0/M, Z31.S
+ ucvtf z0.h, p0/m, z0.d
+ UCVTF Z0.H, P0/M, Z0.D
+ ucvtf z1.h, p0/m, z0.d
+ UCVTF Z1.H, P0/M, Z0.D
+ ucvtf z31.h, p0/m, z0.d
+ UCVTF Z31.H, P0/M, Z0.D
+ ucvtf z0.h, p2/m, z0.d
+ UCVTF Z0.H, P2/M, Z0.D
+ ucvtf z0.h, p7/m, z0.d
+ UCVTF Z0.H, P7/M, Z0.D
+ ucvtf z0.h, p0/m, z3.d
+ UCVTF Z0.H, P0/M, Z3.D
+ ucvtf z0.h, p0/m, z31.d
+ UCVTF Z0.H, P0/M, Z31.D
ucvtf z0.s, p0/m, z0.d
UCVTF Z0.S, P0/M, Z0.D
ucvtf z1.s, p0/m, z0.d
@@ -33046,6 +35181,76 @@
UDIVR Z0.D, P0/M, Z0.D, Z4.D
udivr z0.d, p0/m, z0.d, z31.d
UDIVR Z0.D, P0/M, Z0.D, Z31.D
+ udot z0.s, z0.b, z0.b
+ UDOT Z0.S, Z0.B, Z0.B
+ udot z1.s, z0.b, z0.b
+ UDOT Z1.S, Z0.B, Z0.B
+ udot z31.s, z0.b, z0.b
+ UDOT Z31.S, Z0.B, Z0.B
+ udot z0.s, z2.b, z0.b
+ UDOT Z0.S, Z2.B, Z0.B
+ udot z0.s, z31.b, z0.b
+ UDOT Z0.S, Z31.B, Z0.B
+ udot z0.s, z0.b, z3.b
+ UDOT Z0.S, Z0.B, Z3.B
+ udot z0.s, z0.b, z31.b
+ UDOT Z0.S, Z0.B, Z31.B
+ udot z0.d, z0.h, z0.h
+ UDOT Z0.D, Z0.H, Z0.H
+ udot z1.d, z0.h, z0.h
+ UDOT Z1.D, Z0.H, Z0.H
+ udot z31.d, z0.h, z0.h
+ UDOT Z31.D, Z0.H, Z0.H
+ udot z0.d, z2.h, z0.h
+ UDOT Z0.D, Z2.H, Z0.H
+ udot z0.d, z31.h, z0.h
+ UDOT Z0.D, Z31.H, Z0.H
+ udot z0.d, z0.h, z3.h
+ UDOT Z0.D, Z0.H, Z3.H
+ udot z0.d, z0.h, z31.h
+ UDOT Z0.D, Z0.H, Z31.H
+ udot z0.s, z0.b, z0.b[0]
+ UDOT Z0.S, Z0.B, Z0.B[0]
+ udot z1.s, z0.b, z0.b[0]
+ UDOT Z1.S, Z0.B, Z0.B[0]
+ udot z31.s, z0.b, z0.b[0]
+ UDOT Z31.S, Z0.B, Z0.B[0]
+ udot z0.s, z2.b, z0.b[0]
+ UDOT Z0.S, Z2.B, Z0.B[0]
+ udot z0.s, z31.b, z0.b[0]
+ UDOT Z0.S, Z31.B, Z0.B[0]
+ udot z0.s, z0.b, z3.b[0]
+ UDOT Z0.S, Z0.B, Z3.B[0]
+ udot z0.s, z0.b, z7.b[0]
+ UDOT Z0.S, Z0.B, Z7.B[0]
+ udot z0.s, z0.b, z0.b[1]
+ UDOT Z0.S, Z0.B, Z0.B[1]
+ udot z0.s, z0.b, z4.b[1]
+ UDOT Z0.S, Z0.B, Z4.B[1]
+ udot z0.s, z0.b, z3.b[2]
+ UDOT Z0.S, Z0.B, Z3.B[2]
+ udot z0.s, z0.b, z0.b[3]
+ UDOT Z0.S, Z0.B, Z0.B[3]
+ udot z0.s, z0.b, z5.b[3]
+ UDOT Z0.S, Z0.B, Z5.B[3]
+ udot z0.d, z0.h, z0.h[0]
+ UDOT Z0.D, Z0.H, Z0.H[0]
+ udot z1.d, z0.h, z0.h[0]
+ UDOT Z1.D, Z0.H, Z0.H[0]
+ udot z31.d, z0.h, z0.h[0]
+ UDOT Z31.D, Z0.H, Z0.H[0]
+ udot z0.d, z2.h, z0.h[0]
+ UDOT Z0.D, Z2.H, Z0.H[0]
+ udot z0.d, z31.h, z0.h[0]
+ UDOT Z0.D, Z31.H, Z0.H[0]
+ udot z0.d, z0.h, z3.h[0]
+ UDOT Z0.D, Z0.H, Z3.H[0]
+ udot z0.d, z0.h, z15.h[0]
+ UDOT Z0.D, Z0.H, Z15.H[0]
+ udot z0.d, z0.h, z0.h[1]
+ UDOT Z0.D, Z0.H, Z0.H[1]
+ udot z0.d, z0.h, z11.h[1]
+ UDOT Z0.D, Z0.H, Z11.H[1]
umax z0.b, z0.b, #0
UMAX Z0.B, Z0.B, #0
umax z1.b, z1.b, #0
@@ -38008,6 +40213,24 @@
eon z0.d, z0.d, #0x10000000100
eon z0.d, z0.d, #0x1
EON Z0.D, Z0.D, #0X1
+ facle p0.h, p0/z, z0.h, z0.h
+ FACLE P0.H, P0/Z, Z0.H, Z0.H
+ facle p1.h, p0/z, z0.h, z0.h
+ FACLE P1.H, P0/Z, Z0.H, Z0.H
+ facle p15.h, p0/z, z0.h, z0.h
+ FACLE P15.H, P0/Z, Z0.H, Z0.H
+ facle p0.h, p2/z, z0.h, z0.h
+ FACLE P0.H, P2/Z, Z0.H, Z0.H
+ facle p0.h, p7/z, z0.h, z0.h
+ FACLE P0.H, P7/Z, Z0.H, Z0.H
+ facle p0.h, p0/z, z3.h, z0.h
+ FACLE P0.H, P0/Z, Z3.H, Z0.H
+ facle p0.h, p0/z, z31.h, z0.h
+ FACLE P0.H, P0/Z, Z31.H, Z0.H
+ facle p0.h, p0/z, z0.h, z4.h
+ FACLE P0.H, P0/Z, Z0.H, Z4.H
+ facle p0.h, p0/z, z0.h, z31.h
+ FACLE P0.H, P0/Z, Z0.H, Z31.H
facle p0.s, p0/z, z0.s, z0.s
FACLE P0.S, P0/Z, Z0.S, Z0.S
facle p1.s, p0/z, z0.s, z0.s
@@ -38044,6 +40267,24 @@
FACLE P0.D, P0/Z, Z0.D, Z4.D
facle p0.d, p0/z, z0.d, z31.d
FACLE P0.D, P0/Z, Z0.D, Z31.D
+ faclt p0.h, p0/z, z0.h, z0.h
+ FACLT P0.H, P0/Z, Z0.H, Z0.H
+ faclt p1.h, p0/z, z0.h, z0.h
+ FACLT P1.H, P0/Z, Z0.H, Z0.H
+ faclt p15.h, p0/z, z0.h, z0.h
+ FACLT P15.H, P0/Z, Z0.H, Z0.H
+ faclt p0.h, p2/z, z0.h, z0.h
+ FACLT P0.H, P2/Z, Z0.H, Z0.H
+ faclt p0.h, p7/z, z0.h, z0.h
+ FACLT P0.H, P7/Z, Z0.H, Z0.H
+ faclt p0.h, p0/z, z3.h, z0.h
+ FACLT P0.H, P0/Z, Z3.H, Z0.H
+ faclt p0.h, p0/z, z31.h, z0.h
+ FACLT P0.H, P0/Z, Z31.H, Z0.H
+ faclt p0.h, p0/z, z0.h, z4.h
+ FACLT P0.H, P0/Z, Z0.H, Z4.H
+ faclt p0.h, p0/z, z0.h, z31.h
+ FACLT P0.H, P0/Z, Z0.H, Z31.H
faclt p0.s, p0/z, z0.s, z0.s
FACLT P0.S, P0/Z, Z0.S, Z0.S
faclt p1.s, p0/z, z0.s, z0.s
@@ -38080,6 +40321,24 @@
FACLT P0.D, P0/Z, Z0.D, Z4.D
faclt p0.d, p0/z, z0.d, z31.d
FACLT P0.D, P0/Z, Z0.D, Z31.D
+ fcmle p0.h, p0/z, z0.h, z0.h
+ FCMLE P0.H, P0/Z, Z0.H, Z0.H
+ fcmle p1.h, p0/z, z0.h, z0.h
+ FCMLE P1.H, P0/Z, Z0.H, Z0.H
+ fcmle p15.h, p0/z, z0.h, z0.h
+ FCMLE P15.H, P0/Z, Z0.H, Z0.H
+ fcmle p0.h, p2/z, z0.h, z0.h
+ FCMLE P0.H, P2/Z, Z0.H, Z0.H
+ fcmle p0.h, p7/z, z0.h, z0.h
+ FCMLE P0.H, P7/Z, Z0.H, Z0.H
+ fcmle p0.h, p0/z, z3.h, z0.h
+ FCMLE P0.H, P0/Z, Z3.H, Z0.H
+ fcmle p0.h, p0/z, z31.h, z0.h
+ FCMLE P0.H, P0/Z, Z31.H, Z0.H
+ fcmle p0.h, p0/z, z0.h, z4.h
+ FCMLE P0.H, P0/Z, Z0.H, Z4.H
+ fcmle p0.h, p0/z, z0.h, z31.h
+ FCMLE P0.H, P0/Z, Z0.H, Z31.H
fcmle p0.s, p0/z, z0.s, z0.s
FCMLE P0.S, P0/Z, Z0.S, Z0.S
fcmle p1.s, p0/z, z0.s, z0.s
@@ -38116,6 +40375,24 @@
FCMLE P0.D, P0/Z, Z0.D, Z4.D
fcmle p0.d, p0/z, z0.d, z31.d
FCMLE P0.D, P0/Z, Z0.D, Z31.D
+ fcmlt p0.h, p0/z, z0.h, z0.h
+ FCMLT P0.H, P0/Z, Z0.H, Z0.H
+ fcmlt p1.h, p0/z, z0.h, z0.h
+ FCMLT P1.H, P0/Z, Z0.H, Z0.H
+ fcmlt p15.h, p0/z, z0.h, z0.h
+ FCMLT P15.H, P0/Z, Z0.H, Z0.H
+ fcmlt p0.h, p2/z, z0.h, z0.h
+ FCMLT P0.H, P2/Z, Z0.H, Z0.H
+ fcmlt p0.h, p7/z, z0.h, z0.h
+ FCMLT P0.H, P7/Z, Z0.H, Z0.H
+ fcmlt p0.h, p0/z, z3.h, z0.h
+ FCMLT P0.H, P0/Z, Z3.H, Z0.H
+ fcmlt p0.h, p0/z, z31.h, z0.h
+ FCMLT P0.H, P0/Z, Z31.H, Z0.H
+ fcmlt p0.h, p0/z, z0.h, z4.h
+ FCMLT P0.H, P0/Z, Z0.H, Z4.H
+ fcmlt p0.h, p0/z, z0.h, z31.h
+ FCMLT P0.H, P0/Z, Z0.H, Z31.H
fcmlt p0.s, p0/z, z0.s, z0.s
FCMLT P0.S, P0/Z, Z0.S, Z0.S
fcmlt p1.s, p0/z, z0.s, z0.s
@@ -38152,6 +40429,12 @@
FCMLT P0.D, P0/Z, Z0.D, Z4.D
fcmlt p0.d, p0/z, z0.d, z31.d
FCMLT P0.D, P0/Z, Z0.D, Z31.D
+ fmov z0.h, #0.0
+ FMOV Z0.H, #0.0
+ fmov z1.h, #0.0
+ FMOV Z1.H, #0.0
+ fmov z31.h, #0.0
+ FMOV Z31.H, #0.0
fmov z0.s, #0.0
FMOV Z0.S, #0.0
fmov z1.s, #0.0
@@ -38164,6 +40447,16 @@
FMOV Z1.D, #0.0
fmov z31.d, #0.0
FMOV Z31.D, #0.0
+ fmov z0.h, p0/m, #0.0
+ FMOV Z0.H, P0/M, #0.0
+ fmov z1.h, p0/m, #0.0
+ FMOV Z1.H, P0/M, #0.0
+ fmov z31.h, p0/m, #0.0
+ FMOV Z31.H, P0/M, #0.0
+ fmov z0.h, p2/m, #0.0
+ FMOV Z0.H, P2/M, #0.0
+ fmov z0.h, p15/m, #0.0
+ FMOV Z0.H, P15/M, #0.0
fmov z0.s, p0/m, #0.0
FMOV Z0.S, P0/M, #0.0
fmov z1.s, p0/m, #0.0
@@ -38245,3 +40538,5 @@
orn z0.d, z0.d, #0x10000000100
orn z0.d, z0.d, #0x1
ORN Z0.D, Z0.D, #0X1
+
+ .include "advsimd-compnum.s"
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8dbb540..37e2486 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -247,6 +247,7 @@ enum aarch64_opnd
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
+ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
@@ -298,6 +299,8 @@ enum aarch64_opnd
AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
+ AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
+ AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
@@ -335,6 +338,9 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
+ AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
+ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
+ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 47d56f9..516bdab 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -436,38 +436,27 @@ aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
return NULL;
}
-/* Insert field rot for the rotate immediate in
- FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>. */
+/* Insert 1-bit rotation immediate (#90 or #270). */
const char *
-aarch64_ins_imm_rotate (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code, const aarch64_inst *inst)
+aarch64_ins_imm_rotate1 (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
{
- uint64_t rot = info->imm.value / 90;
-
- switch (info->type)
- {
- case AARCH64_OPND_IMM_ROT1:
- case AARCH64_OPND_IMM_ROT2:
- /* value rot
- 0 0
- 90 1
- 180 2
- 270 3 */
- assert (rot < 4U);
- break;
- case AARCH64_OPND_IMM_ROT3:
- /* value rot
- 90 0
- 270 1 */
- rot = (rot - 1) / 2;
- assert (rot < 2U);
- break;
- default:
- assert (0);
- }
+ uint64_t rot = (info->imm.value - 90) / 180;
+ assert (rot < 2U);
insert_field (self->fields[0], code, rot, inst->opcode->mask);
+ return NULL;
+}
+/* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */
+const char *
+aarch64_ins_imm_rotate2 (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code, const aarch64_inst *inst)
+{
+ uint64_t rot = info->imm.value / 90;
+ assert (rot < 4U);
+ insert_field (self->fields[0], code, rot, inst->opcode->mask);
return NULL;
}
@@ -883,6 +872,20 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
return NULL;
}
+/* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
+ is a 4-bit signed number and where <shift> is SELF's operand-dependent
+ value. fields[0] specifies the base register field. */
+const char *
+aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int factor = 1 << get_operand_specific_data (self);
+ insert_field (self->fields[0], code, info->addr.base_regno, 0);
+ insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
+ return NULL;
+}
+
/* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
@@ -1040,6 +1043,21 @@ aarch64_ins_sve_limm_mov (const aarch64_operand *self,
return aarch64_ins_limm (self, info, code, inst);
}
+/* Encode Zn[MM], where Zn occupies the least-significant part of the field
+ and where MM occupies the most-significant part. The operand-dependent
+ value specifies the number of bits in Zn. */
+const char *
+aarch64_ins_sve_quad_index (const aarch64_operand *self,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ unsigned int reg_bits = get_operand_specific_data (self);
+ assert (info->reglane.regno < (1U << reg_bits));
+ unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
+ insert_all_fields (self, code, val);
+ return NULL;
+}
+
/* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
to use for Zn. */
const char *
@@ -1265,8 +1283,8 @@ do_misc_encoding (aarch64_inst *inst)
break;
case OP_MOV_Z_V:
/* Fill in the zero immediate. */
- insert_field (FLD_SVE_tsz, &inst->value,
- 1 << aarch64_get_variant (inst), 0);
+ insert_fields (&inst->value, 1 << aarch64_get_variant (inst), 0,
+ 2, FLD_imm5, FLD_SVE_tszh);
break;
case OP_MOV_Z_Z:
/* Copy Zn to Zm. */
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index df49db4..45749e5 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -71,6 +71,7 @@ AARCH64_DECL_OPD_INSERTER (ins_hint);
AARCH64_DECL_OPD_INSERTER (ins_prfop);
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
+AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
@@ -88,11 +89,13 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
+AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
-AARCH64_DECL_OPD_INSERTER (ins_imm_rotate);
+AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
+AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
#undef AARCH64_DECL_OPD_INSERTER
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index d08e81f..b528af6 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -711,36 +711,26 @@ aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
return 1;
}
-/* Decode rotate immediate for FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #rotate. */
+/* Decode a 1-bit rotate immediate (#90 or #270). */
int
-aarch64_ext_imm_rotate (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
- const aarch64_inst *inst ATTRIBUTE_UNUSED)
+aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
{
uint64_t rot = extract_field (self->fields[0], code, 0);
+ assert (rot < 2U);
+ info->imm.value = rot * 180 + 90;
+ return 1;
+}
- switch (info->type)
- {
- case AARCH64_OPND_IMM_ROT1:
- case AARCH64_OPND_IMM_ROT2:
- /* rot value
- 0 0
- 1 90
- 2 180
- 3 270 */
- assert (rot < 4U);
- break;
- case AARCH64_OPND_IMM_ROT3:
- /* rot value
- 0 90
- 1 270 */
- assert (rot < 2U);
- rot = 2 * rot + 1;
- break;
- default:
- assert (0);
- return 0;
- }
+/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
+int
+aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ uint64_t rot = extract_field (self->fields[0], code, 0);
+ assert (rot < 4U);
info->imm.value = rot * 90;
return 1;
}
@@ -1364,6 +1354,18 @@ aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
return 1;
}
+/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
+ is a 4-bit signed number and where <shift> is SELF's operand-dependent
+ value. fields[0] specifies the base register field. */
+int
+aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
+ return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
+}
+
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
value. fields[0] specifies the base register field. */
@@ -1591,7 +1593,7 @@ aarch64_ext_sve_index (const aarch64_operand *self,
info->reglane.regno = extract_field (self->fields[0], code, 0);
val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
- if ((val & 15) == 0)
+ if ((val & 31) == 0)
return 0;
while ((val & 1) == 0)
val /= 2;
@@ -1610,6 +1612,21 @@ aarch64_ext_sve_limm_mov (const aarch64_operand *self,
&& aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
}
+/* Decode Zn[MM], where Zn occupies the least-significant part of the field
+ and where MM occupies the most-significant part. The operand-dependent
+ value specifies the number of bits in Zn. */
+int
+aarch64_ext_sve_quad_index (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ unsigned int reg_bits = get_operand_specific_data (self);
+ unsigned int val = extract_all_fields (self, code);
+ info->reglane.regno = val & ((1 << reg_bits) - 1);
+ info->reglane.index = val >> reg_bits;
+ return 1;
+}
+
/* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
to use for Zn. The opcode-dependent value specifies the number
of registers in the list. */
@@ -1907,7 +1924,7 @@ do_misc_decoding (aarch64_inst *inst)
case OP_MOV_Z_V:
/* Index must be zero. */
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
- return value == 1 || value == 2 || value == 4 || value == 8;
+ return value > 0 && value <= 16 && value == (value & -value);
case OP_MOV_Z_Z:
return (extract_field (FLD_SVE_Zn, inst->value, 0)
@@ -1916,7 +1933,7 @@ do_misc_decoding (aarch64_inst *inst)
case OP_MOV_Z_Zi:
/* Index must be nonzero. */
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
- return value != 1 && value != 2 && value != 4 && value != 8;
+ return value > 0 && value != (value & -value);
case OP_MOVM_P_P_P:
return (extract_field (FLD_SVE_Pd, inst->value, 0)
@@ -2573,8 +2590,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
break;
case sve_index:
- i = extract_field (FLD_SVE_tsz, inst->value, 0);
- if (i == 0)
+ i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
+ if ((i & 31) == 0)
return FALSE;
while ((i & 1) == 0)
{
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index ddf70dc..6411c7a 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -93,6 +93,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
@@ -110,11 +111,13 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
-AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate);
+AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
+AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
#undef AARCH64_DECL_OPD_EXTRACTOR
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dac6159..cc99c10 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -290,6 +290,7 @@ const aarch64_field fields[] =
{ 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
{ 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
{ 5, 1 }, /* SVE_i1: single-bit immediate. */
+ { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
{ 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
{ 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
{ 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
@@ -303,6 +304,8 @@ const aarch64_field fields[] =
{ 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
{ 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
{ 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
+ { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
+ { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
@@ -1474,6 +1477,29 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_CLASS_SVE_REG:
switch (type)
{
+ case AARCH64_OPND_SVE_Zm3_INDEX:
+ case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm4_INDEX:
+ size = get_operand_fields_width (get_operand_from_code (type));
+ shift = get_operand_specific_data (&aarch64_operands[type]);
+ mask = (1 << shift) - 1;
+ if (opnd->reg.regno > mask)
+ {
+ assert (mask == 7 || mask == 15);
+ set_other_error (mismatch_detail, idx,
+ mask == 15
+ ? _("z0-z15 expected")
+ : _("z0-z7 expected"));
+ return 0;
+ }
+ mask = (1 << (size - shift)) - 1;
+ if (!value_in_range_p (opnd->reglane.index, 0, mask))
+ {
+ set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
+ return 0;
+ }
+ break;
+
case AARCH64_OPND_SVE_Zn_INDEX:
size = aarch64_get_qualifier_esize (opnd->qualifier);
if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
@@ -1798,6 +1824,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ min_value = -8;
+ max_value = 7;
+ goto sve_imm_offset;
+
case AARCH64_OPND_SVE_ADDR_RR:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
@@ -2103,6 +2134,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_IMM_ROT1:
case AARCH64_OPND_IMM_ROT2:
+ case AARCH64_OPND_SVE_IMM_ROT2:
if (opnd->imm.value != 0
&& opnd->imm.value != 90
&& opnd->imm.value != 180
@@ -2115,6 +2147,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case AARCH64_OPND_IMM_ROT3:
+ case AARCH64_OPND_SVE_IMM_ROT1:
if (opnd->imm.value != 90 && opnd->imm.value != 270)
{
set_other_error (mismatch_detail, idx,
@@ -3174,6 +3207,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
print_register_list (buf, size, opnd, "z");
break;
+ case AARCH64_OPND_SVE_Zm3_INDEX:
+ case AARCH64_OPND_SVE_Zm3_22_INDEX:
+ case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
aarch64_get_qualifier_name (opnd->qualifier),
@@ -3214,6 +3250,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_IMM_ROT1:
case AARCH64_OPND_IMM_ROT2:
case AARCH64_OPND_IMM_ROT3:
+ case AARCH64_OPND_SVE_IMM_ROT1:
+ case AARCH64_OPND_SVE_IMM_ROT2:
snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
break;
@@ -3461,6 +3499,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_ADDR_SIMM9:
case AARCH64_OPND_ADDR_SIMM9_2:
case AARCH64_OPND_ADDR_SIMM10:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 2129e7b..9f73eba 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -117,6 +117,7 @@ enum aarch64_field_kind
FLD_SVE_Zn,
FLD_SVE_Zt,
FLD_SVE_i1,
+ FLD_SVE_i3h,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
@@ -130,6 +131,8 @@ enum aarch64_field_kind
FLD_SVE_msz,
FLD_SVE_pattern,
FLD_SVE_prfop,
+ FLD_SVE_rot1,
+ FLD_SVE_rot2,
FLD_SVE_sz,
FLD_SVE_tsz,
FLD_SVE_tszh,
@@ -186,9 +189,9 @@ extern const aarch64_operand aarch64_operands[];
value by 2 to get the value
of an immediate operand. */
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
-#define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */
+#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
#define OPD_F_OD_LSB 5
-#define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */
+#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
static inline bfd_boolean
operand_has_inserter (const aarch64_operand *operand)
@@ -227,6 +230,14 @@ get_operand_specific_data (const aarch64_operand *operand)
return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
}
+/* Return the width of field number N of operand *OPERAND. */
+static inline unsigned
+get_operand_field_width (const aarch64_operand *operand, unsigned n)
+{
+ assert (operand->fields[n] != FLD_NIL);
+ return fields[operand->fields[n]].width;
+}
+
/* Return the total width of the operand *OPERAND. */
static inline unsigned
get_operand_fields_width (const aarch64_operand *operand)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 705ace6..72b9952 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1515,6 +1515,10 @@
{ \
QLF2(S_H,S_B), \
}
+#define OP_SVE_HMH \
+{ \
+ QLF3(S_H,P_M,S_H), \
+}
#define OP_SVE_HMD \
{ \
QLF3(S_H,P_M,S_D), \
@@ -1605,8 +1609,9 @@
QLF3(S_S,P_M,W), \
QLF3(S_D,P_M,X), \
}
-#define OP_SVE_VMU_SD \
+#define OP_SVE_VMU_HSD \
{ \
+ QLF3(S_H,P_M,NIL), \
QLF3(S_S,P_M,NIL), \
QLF3(S_D,P_M,NIL), \
}
@@ -1623,8 +1628,9 @@
QLF4(S_S,P_M,S_S,NIL), \
QLF4(S_D,P_M,S_D,NIL), \
}
-#define OP_SVE_VMVU_SD \
+#define OP_SVE_VMVU_HSD \
{ \
+ QLF4(S_H,P_M,S_H,NIL), \
QLF4(S_S,P_M,S_S,NIL), \
QLF4(S_D,P_M,S_D,NIL), \
}
@@ -1635,11 +1641,23 @@
QLF4(S_S,P_M,S_S,S_S), \
QLF4(S_D,P_M,S_D,S_D), \
}
+#define OP_SVE_VMVV_HSD \
+{ \
+ QLF4(S_H,P_M,S_H,S_H), \
+ QLF4(S_S,P_M,S_S,S_S), \
+ QLF4(S_D,P_M,S_D,S_D), \
+}
#define OP_SVE_VMVV_SD \
{ \
QLF4(S_S,P_M,S_S,S_S), \
QLF4(S_D,P_M,S_D,S_D), \
}
+#define OP_SVE_VMVVU_HSD \
+{ \
+ QLF5(S_H,P_M,S_H,S_H,NIL), \
+ QLF5(S_S,P_M,S_S,S_S,NIL), \
+ QLF5(S_D,P_M,S_D,S_D,NIL), \
+}
#define OP_SVE_VMV_BHSD \
{ \
QLF3(S_B,P_M,S_B), \
@@ -1658,8 +1676,9 @@
QLF3(S_S,P_M,S_S), \
QLF3(S_D,P_M,S_D), \
}
-#define OP_SVE_VM_SD \
+#define OP_SVE_VM_HSD \
{ \
+ QLF2(S_H,P_M), \
QLF2(S_S,P_M), \
QLF2(S_D,P_M), \
}
@@ -1727,8 +1746,9 @@
QLF4(S_S,NIL,S_S,S_S), \
QLF4(S_D,NIL,S_D,S_D), \
}
-#define OP_SVE_VUVV_SD \
+#define OP_SVE_VUVV_HSD \
{ \
+ QLF4(S_H,NIL,S_H,S_H), \
QLF4(S_S,NIL,S_S,S_S), \
QLF4(S_D,NIL,S_D,S_D), \
}
@@ -1739,6 +1759,12 @@
QLF3(S_S,NIL,S_S), \
QLF3(S_D,NIL,S_D), \
}
+#define OP_SVE_VUV_HSD \
+{ \
+ QLF3(S_H,NIL,S_H), \
+ QLF3(S_S,NIL,S_S), \
+ QLF3(S_D,NIL,S_D), \
+}
#define OP_SVE_VUV_SD \
{ \
QLF3(S_S,NIL,S_S), \
@@ -1757,8 +1783,9 @@
QLF2(S_S,NIL), \
QLF2(S_D,NIL), \
}
-#define OP_SVE_VU_SD \
+#define OP_SVE_VU_HSD \
{ \
+ QLF2(S_H,NIL), \
QLF2(S_S,NIL), \
QLF2(S_D,NIL), \
}
@@ -1775,9 +1802,18 @@
QLF3(S_S,S_S,NIL), \
QLF3(S_D,S_D,NIL), \
}
-#define OP_SVE_VVVU_SD \
+#define OP_SVE_VVVU_H \
+{ \
+ QLF4(S_H,S_H,S_H,NIL), \
+}
+#define OP_SVE_VVVU_S \
{ \
QLF4(S_S,S_S,S_S,NIL), \
+}
+#define OP_SVE_VVVU_HSD \
+{ \
+ QLF4(S_H,S_H,S_H,NIL), \
+ QLF4(S_S,S_S,S_S,NIL), \
QLF4(S_D,S_D,S_D,NIL), \
}
#define OP_SVE_VVV_BHSD \
@@ -1787,11 +1823,37 @@
QLF3(S_S,S_S,S_S), \
QLF3(S_D,S_D,S_D), \
}
-#define OP_SVE_VVV_SD \
+#define OP_SVE_VVV_D \
+{ \
+ QLF3(S_D,S_D,S_D), \
+}
+#define OP_SVE_VVV_D_H \
+{ \
+ QLF3(S_D,S_H,S_H), \
+}
+#define OP_SVE_VVV_H \
{ \
+ QLF3(S_H,S_H,S_H), \
+}
+#define OP_SVE_VVV_HSD \
+{ \
+ QLF3(S_H,S_H,S_H), \
QLF3(S_S,S_S,S_S), \
QLF3(S_D,S_D,S_D), \
}
+#define OP_SVE_VVV_S \
+{ \
+ QLF3(S_S,S_S,S_S), \
+}
+#define OP_SVE_VVV_S_B \
+{ \
+ QLF3(S_S,S_B,S_B), \
+}
+#define OP_SVE_VVV_SD_BH \
+{ \
+ QLF3(S_S,S_B,S_B), \
+ QLF3(S_D,S_H,S_H), \
+}
#define OP_SVE_VV_BHSD \
{ \
QLF2(S_B,S_B), \
@@ -1799,6 +1861,20 @@
QLF2(S_S,S_S), \
QLF2(S_D,S_D), \
}
+#define OP_SVE_VV_BHSDQ \
+{ \
+ QLF2(S_B,S_B), \
+ QLF2(S_H,S_H), \
+ QLF2(S_S,S_S), \
+ QLF2(S_D,S_D), \
+ QLF2(S_Q,S_Q), \
+}
+#define OP_SVE_VV_HSD \
+{ \
+ QLF2(S_H,S_H), \
+ QLF2(S_S,S_S), \
+ QLF2(S_D,S_D), \
+}
#define OP_SVE_VV_HSD_BHS \
{ \
QLF2(S_H,S_B), \
@@ -1844,18 +1920,21 @@
QLF4(S_S,P_Z,S_S,S_S), \
QLF4(S_D,P_Z,S_D,S_D), \
}
-#define OP_SVE_VZVV_SD \
+#define OP_SVE_VZVV_HSD \
{ \
+ QLF4(S_H,P_Z,S_H,S_H), \
QLF4(S_S,P_Z,S_S,S_S), \
QLF4(S_D,P_Z,S_D,S_D), \
}
-#define OP_SVE_VZV_SD \
+#define OP_SVE_VZV_HSD \
{ \
+ QLF3(S_H,P_Z,S_H), \
QLF3(S_S,P_Z,S_S), \
QLF3(S_D,P_Z,S_D), \
}
-#define OP_SVE_V_SD \
+#define OP_SVE_V_HSD \
{ \
+ QLF1(S_H), \
QLF1(S_S), \
QLF1(S_D), \
}
@@ -3281,13 +3360,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
/* SVE instructions. */
- _SVE_INSN ("fmov", 0x25b9c000, 0xffbfe000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_SD, F_ALIAS, 0),
- _SVE_INSN ("fmov", 0x0590c000, 0xffb0e000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_SD, F_ALIAS, 0),
+ _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
+ _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0),
_SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSD, F_ALIAS | F_MISC, 0),
+ _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
_SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
_SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSD, F_ALIAS | F_MISC, 0),
+ _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
_SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
_SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
_SVE_INSN ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, 0),
@@ -3393,7 +3472,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0),
_SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
_SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
_SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
@@ -3403,92 +3482,111 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
_SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
_SVE_INSN ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, 1),
- _SVE_INSN ("fabd", 0x65888000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fabs", 0x049ca000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("facge", 0x6580c010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
- _SVE_INSN ("facgt", 0x6580e010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fadd", 0x65800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("fadd", 0x65808000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fadd", 0x65988000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fadda", 0x65982000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_SD, 0, 2),
- _SVE_INSN ("faddv", 0x65802000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
- _SVE_INSN ("fcmeq", 0x65922000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmeq", 0x65806000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
- _SVE_INSN ("fcmge", 0x65902000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmge", 0x65804000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fcmgt", 0x65902010, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmgt", 0x65804010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fcmle", 0x65912010, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmlt", 0x65912000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmne", 0x65932000, 0xffbfe010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_SD, 0, 0),
- _SVE_INSN ("fcmne", 0x65806010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
- _SVE_INSN ("fcmuo", 0x6580c000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
- _SVE_INSN ("fcpy", 0x0590c000, 0xffb0e000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_SD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2),
+ _SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
+ _SVE_INSN ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, 2),
+ _SVE_INSN ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, 0),
+ _SVE_INSN ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, 0),
+ _SVE_INSN ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, 0),
+ _SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
+ _SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmge", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("fcmgt", 0x65102010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmgt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("fcmle", 0x65112010, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmlt", 0x65112000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
+ _SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
+ _SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
+ _SVE_INSN ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, 0),
_SVE_INSN ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
_SVE_INSN ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
_SVE_INSN ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
_SVE_INSN ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
_SVE_INSN ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
_SVE_INSN ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
+ _SVE_INSN ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
+ _SVE_INSN ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
+ _SVE_INSN ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
_SVE_INSN ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
_SVE_INSN ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
_SVE_INSN ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
_SVE_INSN ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
+ _SVE_INSN ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
+ _SVE_INSN ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
+ _SVE_INSN ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
_SVE_INSN ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
_SVE_INSN ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
_SVE_INSN ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
_SVE_INSN ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
- _SVE_INSN ("fdiv", 0x658d8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fdivr", 0x658c8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fdup", 0x25b9c000, 0xffbfe000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_SD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fexpa", 0x04a0b800, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
- _SVE_INSN ("fmad", 0x65a08000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fmax", 0x65868000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fmax", 0x659e8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fmaxnm", 0x65848000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fmaxnm", 0x659c8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fmaxnmv", 0x65842000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
- _SVE_INSN ("fmaxv", 0x65862000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
- _SVE_INSN ("fmin", 0x65878000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fmin", 0x659f8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fminnm", 0x65858000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fminnm", 0x659d8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fminnmv", 0x65852000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
- _SVE_INSN ("fminv", 0x65872000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
- _SVE_INSN ("fmla", 0x65a00000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fmls", 0x65a02000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fmsb", 0x65a0a000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fmul", 0x65800800, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("fmul", 0x65828000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fmul", 0x659a8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fmulx", 0x658a8000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fneg", 0x049da000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("fnmad", 0x65a0c000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fnmla", 0x65a04000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fnmls", 0x65a06000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("fnmsb", 0x65a0e000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_SD, 0, 0),
- _SVE_INSN ("frecpe", 0x658e3000, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
- _SVE_INSN ("frecps", 0x65801800, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("frecpx", 0x658ca000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frinta", 0x6584a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frinti", 0x6587a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frintm", 0x6582a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frintn", 0x6580a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frintp", 0x6581a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frintx", 0x6586a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frintz", 0x6583a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("frsqrte", 0x658f3000, 0xffbffc00, sve_size_sd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_SD, 0, 0),
- _SVE_INSN ("frsqrts", 0x65801c00, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("fscale", 0x65898000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fsqrt", 0x658da000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
- _SVE_INSN ("fsub", 0x65800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("fsub", 0x65818000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fsub", 0x65998000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("fsubr", 0x65838000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
- _SVE_INSN ("fsubr", 0x659b8000, 0xffbfe3c0, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_SD, 0, 2),
- _SVE_INSN ("ftmad", 0x65908000, 0xffb8fc00, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_SD, 0, 1),
- _SVE_INSN ("ftsmul", 0x65800c00, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
- _SVE_INSN ("ftssel", 0x04a0b000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, 0),
+ _SVE_INSN ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
+ _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
+ _SVE_INSN ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
+ _SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
+ _SVE_INSN ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
+ _SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
+ _SVE_INSN ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
+ _SVE_INSN ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
+ _SVE_INSN ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
+ _SVE_INSN ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
+ _SVE_INSN ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
+ _SVE_INSN ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
+ _SVE_INSN ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
+ _SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
+ _SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
+ _SVE_INSN ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
+ _SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
+ _SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
+ _SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
+ _SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
+ _SVE_INSN ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
+ _SVE_INSN ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, 1),
+ _SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
+ _SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
_SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
@@ -3550,6 +3648,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("ld1rh", 0x84c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ld1rh", 0x84c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ld1rh", 0x84c0e000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6x2), OP_SVE_DZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqb", 0xa4002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_BZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqb", 0xa4000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqd", 0xa5802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_DZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqd", 0xa5800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqh", 0xa4802000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_HZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqh", 0xa4800000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqw", 0xa5002000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x16), OP_SVE_SZU, F_OD(1), 0),
+ _SVE_INSN ("ld1rqw", 0xa5000000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ld1rsb", 0x85c08000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ld1rsb", 0x85c0a000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ld1rsb", 0x85c0c000, 0xffc0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_U6), OP_SVE_HZU, F_OD(1), 0),
@@ -3792,12 +3898,18 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
_SVE_INSN ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
_SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0),
+ _SVE_INSN ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
+ _SVE_INSN ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
_SVE_INSN ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
_SVE_INSN ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
+ _SVE_INSN ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
_SVE_INSN ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
_SVE_INSN ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
_SVE_INSN ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
_SVE_INSN ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
+ _SVE_INSN ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
+ _SVE_INSN ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
+ _SVE_INSN ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
_SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0),
_SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0),
_SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0),
@@ -3938,12 +4050,18 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
_SVE_INSN ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
_SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0),
+ _SVE_INSN ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
+ _SVE_INSN ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
_SVE_INSN ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
_SVE_INSN ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
+ _SVE_INSN ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
_SVE_INSN ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
_SVE_INSN ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
_SVE_INSN ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
_SVE_INSN ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
+ _SVE_INSN ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
+ _SVE_INSN ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
+ _SVE_INSN ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
_SVE_INSN ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, 1),
_SVE_INSN ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
_SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
@@ -4011,12 +4129,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
_SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
_SVE_INSN ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
- _SVE_INSN ("facle", 0x6580c010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("faclt", 0x6580e010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fcmle", 0x65804000, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fcmlt", 0x65804010, 0xffa0e010, sve_size_sd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_SD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fmov", 0x25b8c000, 0xffbfffe0, sve_size_sd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_SD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fmov", 0x05904000, 0xffb0ffe0, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_SD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0),
+ _SVE_INSN ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, 0),
_SVE_INSN ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, NULL},
@@ -4147,11 +4265,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
"the number of bits after the binary point in the fixed-point value")\
X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
- Y(IMMEDIATE, imm_rotate, "IMM_ROT1", 0, F(FLD_rotate1), \
+ Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \
"a 2-bit rotation specifier for complex arithmetic operations") \
- Y(IMMEDIATE, imm_rotate, "IMM_ROT2", 0, F(FLD_rotate2), \
+ Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \
"a 2-bit rotation specifier for complex arithmetic operations") \
- Y(IMMEDIATE, imm_rotate, "IMM_ROT3", 0, F(FLD_rotate3), \
+ Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \
"a 1-bit rotation specifier for complex arithmetic operations") \
Y(COND, cond, "COND", 0, F(), "a condition") \
Y(COND, cond, "COND1", 0, F(), \
@@ -4203,6 +4321,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a prefetch operation specifier") \
Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
"the PSB option name CSYNC") \
+ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
+ 4 << OPD_F_OD_LSB, F(FLD_Rn), \
+ "an address with a 4-bit signed offset, multiplied by 16") \
Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \
0 << OPD_F_OD_LSB, F(FLD_Rn), \
"an address with a 4-bit signed offset, multiplied by VL") \
@@ -4320,6 +4441,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SVE_i1), "either 0.5 or 2.0") \
Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \
F(FLD_SVE_i1), "either 0.0 or 1.0") \
+ Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \
+ "a 1-bit rotation specifier for complex arithmetic operations") \
+ Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
+ "a 2-bit rotation specifier for complex arithmetic operations") \
Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
"an inverted 13-bit logical immediate") \
@@ -4393,6 +4518,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
"an SVE vector register") \
Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \
"an SVE vector register") \
+ Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \
+ 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
+ "an indexed SVE vector register") \
+ Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
+ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
+ "an indexed SVE vector register") \
+ Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
+ 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
+ "an indexed SVE vector register") \
Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \
"an SVE vector register") \
Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \