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Re: [PATCH] x86: ignore high register select bit(s) in 32- and 16-bit modes
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: "Binutils" <binutils at sourceware dot org>
- Date: Thu, 23 Feb 2017 09:16:23 -0700
- Subject: Re: [PATCH] x86: ignore high register select bit(s) in 32- and 16-bit modes
- Authentication-results: sourceware.org; auth=none
- References: <58AC7878020000780013C5AD@prv-mh.provo.novell.com> <CAMe9rOr5OyeQ35ss_Y73dz5yfLGxCKuZt=jPf8fSAxyfrdE=0Q@mail.gmail.com> <58AE9F8F020000780013D0AF@prv-mh.provo.novell.com> <CAMe9rOpTT5fgA-WocAS=2z3aWYWMQndBPwR0Zo8_haXg9GVdNA@mail.gmail.com>
>>> On 23.02.17 at 16:54, <firstname.lastname@example.org> wrote:
> On Wed, Feb 22, 2017 at 11:38 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 22.02.17 at 20:03, <email@example.com> wrote:
>>> On Tue, Feb 21, 2017 at 8:27 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> @@ -16937,7 +16928,7 @@ OP_VEX (int bytemode, int sizeflag ATTRI
>>>> names = names_xmm;
>>>> case dq_mode:
>>>> - if (vex.w)
>>>> + if (rex & REX_W)
>>>> names = names64;
>>>> names = names32;
>>> Do you have a testcase where vex.w != rex & REX_W?
>> I'm sorry, but I don't think I understand the question in the light
>> of there being a testcase added covering all of the previous
>> misbehaviors I'm aware of.
> My question is why vex.w and rex & REX_W are out of sync
> at this point.
That's because for 64-bit code REX_W gets ser from vex.w
during VEX decoding. For 16- and 32-bit code this doesn't happen,
and hence looking at vex.w (possibly set) is wrong here, while
rex & REX_W (always clear for these modes) gives the correct