From e41a0a2ed4e8ef87eb3fc6835423209665a72d38 Mon Sep 17 00:00:00 2001
From: Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Date: Tue, 20 Dec 2016 20:32:33 +0300
Subject: [PATCH] Enable Intel AVX512_VPOPCNTDQ instructions

 gas/

  * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
   (cpu_noarch): Add noavx512_vpopcntdq.
  * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
  * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
  * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: Ditto.
  * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
  * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
  * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
  * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
  * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.

 opcodes/

  * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
  * i386-dis-evex.h (evex_table): Updated.
  * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
    CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
    (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
  * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
    (i386_cpu_flags): Add cpuavx512_vpopcntdq.
  * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
  * i386-init.h: Regenerate.
  * i386-tbl.h: Ditto.
---
 gas/config/tc-i386.c                               |     3 +
 gas/doc/c-i386.texi                                |     4 +-
 gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d    |    68 +
 gas/testsuite/gas/i386/avx512_vpopcntdq.d          |    68 +
 gas/testsuite/gas/i386/avx512_vpopcntdq.s          |    63 +
 gas/testsuite/gas/i386/i386.exp                    |     4 +
 .../gas/i386/x86-64-avx512_vpopcntdq-intel.d       |    68 +
 gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.d   |    68 +
 gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.s   |    63 +
 opcodes/i386-dis-evex.h                            |    13 +-
 opcodes/i386-dis.c                                 |     2 +
 opcodes/i386-gen.c                                 |     7 +-
 opcodes/i386-init.h                                |   278 +-
 opcodes/i386-opc.h                                 |     3 +
 opcodes/i386-opc.tbl                               |    10 +-
 opcodes/i386-tbl.h                                 | 10450 ++++++++++---------
 16 files changed, 5827 insertions(+), 5345 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx512_vpopcntdq.d
 create mode 100644 gas/testsuite/gas/i386/avx512_vpopcntdq.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ca26127..12117ca 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -966,6 +966,8 @@ static const arch_entry cpu_arch[] =
     CPU_AVX512_4FMAPS_FLAGS, 0 },
   { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
     CPU_AVX512_4VNNIW_FLAGS, 0 },
+  { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
+    CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
   { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
     CPU_CLZERO_FLAGS, 0 },
   { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
@@ -1005,6 +1007,7 @@ static const noarch_entry cpu_noarch[] =
   { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
   { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
   { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
+  { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
 };
 
 #ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index c3c632d..f79f6b1 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -182,6 +182,7 @@ accept various extension mnemonics.  For example,
 @code{avx512vbmi},
 @code{avx512_4fmaps},
 @code{avx512_4vnniw},
+@code{avx512_vpopcntdq},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -193,6 +194,7 @@ accept various extension mnemonics.  For example,
 @code{noavx512vbmi},
 @code{noavx512_4fmaps},
 @code{noavx512_4vnniw},
+@code{noavx512_vpopcntdq},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -1195,7 +1197,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
-@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
+@item @samp{.avx512_vpopcntdq} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d b/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
new file mode 100644
index 0000000..d311c45
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq-intel.d
@@ -0,0 +1,68 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512/VPOPCNTDQ insns (Intel disassembly)
+#source: avx512_vpopcntdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 f5[ 	]*vpopcntd zmm6,zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 4f 55 f5[ 	]*vpopcntd zmm6\{k7\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d cf 55 f5[ 	]*vpopcntd zmm6\{k7\}\{z\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 31[ 	]*vpopcntd zmm6,ZMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 30[ 	]*vpopcntd zmm6,DWORD PTR \[eax\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 7f[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 80[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 7f[ 	]*vpopcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 80[ 	]*vpopcntd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 f5[ 	]*vpopcntq zmm6,zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 4f 55 f5[ 	]*vpopcntq zmm6\{k7\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd cf 55 f5[ 	]*vpopcntq zmm6\{k7\}\{z\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 31[ 	]*vpopcntq zmm6,ZMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 30[ 	]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 7f[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 80[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 7f[ 	]*vpopcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 80[ 	]*vpopcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 f5[ 	]*vpopcntd zmm6,zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 4f 55 f5[ 	]*vpopcntd zmm6\{k7\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d cf 55 f5[ 	]*vpopcntd zmm6\{k7\}\{z\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 31[ 	]*vpopcntd zmm6,ZMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 30[ 	]*vpopcntd zmm6,DWORD PTR \[eax\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 7f[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 80[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd zmm6,ZMMWORD PTR \[edx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 7f[ 	]*vpopcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 80[ 	]*vpopcntd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 f5[ 	]*vpopcntq zmm6,zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 4f 55 f5[ 	]*vpopcntq zmm6\{k7\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd cf 55 f5[ 	]*vpopcntq zmm6\{k7\}\{z\},zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 31[ 	]*vpopcntq zmm6,ZMMWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 30[ 	]*vpopcntq zmm6,QWORD PTR \[eax\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 7f[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 80[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq zmm6,ZMMWORD PTR \[edx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 7f[ 	]*vpopcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 80[ 	]*vpopcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq.d b/gas/testsuite/gas/i386/avx512_vpopcntdq.d
new file mode 100644
index 0000000..3f10887
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq.d
@@ -0,0 +1,68 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512/VPOPCNTDQ insns
+#source: avx512_vpopcntdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 f5[ 	]*vpopcntd %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 4f 55 f5[ 	]*vpopcntd %zmm5,%zmm6\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d cf 55 f5[ 	]*vpopcntd %zmm5,%zmm6\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 31[ 	]*vpopcntd \(%ecx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntd -0x1e240\(%esp,%esi,8\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 30[ 	]*vpopcntd \(%eax\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 7f[ 	]*vpopcntd 0x1fc0\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd 0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 80[ 	]*vpopcntd -0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd -0x2040\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 7f[ 	]*vpopcntd 0x1fc\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd 0x200\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 80[ 	]*vpopcntd -0x200\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd -0x204\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 f5[ 	]*vpopcntq %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 4f 55 f5[ 	]*vpopcntq %zmm5,%zmm6\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd cf 55 f5[ 	]*vpopcntq %zmm5,%zmm6\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 31[ 	]*vpopcntq \(%ecx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntq -0x1e240\(%esp,%esi,8\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 30[ 	]*vpopcntq \(%eax\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 7f[ 	]*vpopcntq 0x1fc0\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq 0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 80[ 	]*vpopcntq -0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq -0x2040\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 7f[ 	]*vpopcntq 0x3f8\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq 0x400\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 80[ 	]*vpopcntq -0x400\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq -0x408\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 f5[ 	]*vpopcntd %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 4f 55 f5[ 	]*vpopcntd %zmm5,%zmm6\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d cf 55 f5[ 	]*vpopcntd %zmm5,%zmm6\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 31[ 	]*vpopcntd \(%ecx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntd -0x1e240\(%esp,%esi,8\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 30[ 	]*vpopcntd \(%eax\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 7f[ 	]*vpopcntd 0x1fc0\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd 0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 72 80[ 	]*vpopcntd -0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd -0x2040\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 7f[ 	]*vpopcntd 0x1fc\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd 0x200\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 72 80[ 	]*vpopcntd -0x200\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd -0x204\(%edx\)\{1to16\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 f5[ 	]*vpopcntq %zmm5,%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 4f 55 f5[ 	]*vpopcntq %zmm5,%zmm6\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd cf 55 f5[ 	]*vpopcntq %zmm5,%zmm6\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 31[ 	]*vpopcntq \(%ecx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b4 f4 c0 1d fe ff[ 	]*vpopcntq -0x1e240\(%esp,%esi,8\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 30[ 	]*vpopcntq \(%eax\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 7f[ 	]*vpopcntq 0x1fc0\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq 0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 72 80[ 	]*vpopcntq -0x2000\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq -0x2040\(%edx\),%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 7f[ 	]*vpopcntq 0x3f8\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq 0x400\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 72 80[ 	]*vpopcntq -0x400\(%edx\)\{1to8\},%zmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq -0x408\(%edx\)\{1to8\},%zmm6
+#pass
diff --git a/gas/testsuite/gas/i386/avx512_vpopcntdq.s b/gas/testsuite/gas/i386/avx512_vpopcntdq.s
new file mode 100644
index 0000000..2691a46
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512_vpopcntdq.s
@@ -0,0 +1,63 @@
+# Check 32bit AVX512_VPOPCNTDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpopcntd	%zmm5, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	%zmm5, %zmm6{%k7}	 # AVX512_VPOPCNTDQ
+	vpopcntd	%zmm5, %zmm6{%k7}{z}	 # AVX512_VPOPCNTDQ
+	vpopcntd	(%ecx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	-123456(%esp,%esi,8), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	(%eax){1to16}, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	8128(%edx), %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	8192(%edx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	-8192(%edx), %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	-8256(%edx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	508(%edx){1to16}, %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	512(%edx){1to16}, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntd	-512(%edx){1to16}, %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	-516(%edx){1to16}, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm5, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm5, %zmm6{%k7}	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm5, %zmm6{%k7}{z}	 # AVX512_VPOPCNTDQ
+	vpopcntq	(%ecx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	-123456(%esp,%esi,8), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	(%eax){1to8}, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	8128(%edx), %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	8192(%edx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	-8192(%edx), %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	-8256(%edx), %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	1016(%edx){1to8}, %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	1024(%edx){1to8}, %zmm6	 # AVX512_VPOPCNTDQ
+	vpopcntq	-1024(%edx){1to8}, %zmm6	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	-1032(%edx){1to8}, %zmm6	 # AVX512_VPOPCNTDQ
+
+	.intel_syntax noprefix
+	vpopcntd	zmm6, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6{k7}, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6{k7}{z}, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, ZMMWORD PTR [ecx]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, [eax]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, ZMMWORD PTR [edx+8128]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm6, ZMMWORD PTR [edx+8192]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, ZMMWORD PTR [edx-8192]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm6, ZMMWORD PTR [edx-8256]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, [edx+508]{1to16}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm6, [edx+512]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm6, [edx-512]{1to16}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm6, [edx-516]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6{k7}, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6{k7}{z}, zmm5	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, ZMMWORD PTR [ecx]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, ZMMWORD PTR [esp+esi*8-123456]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, [eax]{1to8}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, ZMMWORD PTR [edx+8128]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm6, ZMMWORD PTR [edx+8192]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, ZMMWORD PTR [edx-8192]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm6, ZMMWORD PTR [edx-8256]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, [edx+1016]{1to8}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm6, [edx+1024]{1to8}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm6, [edx-1024]{1to8}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm6, [edx-1032]{1to8}	 # AVX512_VPOPCNTDQ
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 29282b8..10d9aa1 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -368,6 +368,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx512_4vnniw-intel"
     run_dump_test "avx512_4vnniw_vl"
     run_dump_test "avx512_4vnniw_vl-intel"
+    run_dump_test "avx512_vpopcntdq"
+    run_dump_test "avx512_vpopcntdq-intel"
     run_dump_test "clzero"
     run_dump_test "disassem"
     run_dump_test "mwaitx-bdver4"
@@ -781,6 +783,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx512_4vnniw-intel"
     run_dump_test "x86-64-avx512_4vnniw_vl"
     run_dump_test "x86-64-avx512_4vnniw_vl-intel"
+    run_dump_test "x86-64-avx512_vpopcntdq"
+    run_dump_test "x86-64-avx512_vpopcntdq-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq-intel.d b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq-intel.d
new file mode 100644
index 0000000..476d586
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq-intel.d
@@ -0,0 +1,68 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX512/VPOPCNTDQ insns (Intel disassembly)
+#source: x86-64-avx512_vpopcntdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 55 f5[ 	]*vpopcntd zmm30,zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 4f 55 f5[ 	]*vpopcntd zmm30\{k7\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d cf 55 f5[ 	]*vpopcntd zmm30\{k7\}\{z\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 31[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 22 7d 48 55 b4 f0 23 01 00 00[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 31[ 	]*vpopcntd zmm30,DWORD PTR \[rcx\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 7f[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 80[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 7f[ 	]*vpopcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 80[ 	]*vpopcntd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 48 55 f5[ 	]*vpopcntq zmm30,zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 4f 55 f5[ 	]*vpopcntq zmm30\{k7\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd cf 55 f5[ 	]*vpopcntq zmm30\{k7\}\{z\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 31[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 22 fd 48 55 b4 f0 23 01 00 00[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 31[ 	]*vpopcntq zmm30,QWORD PTR \[rcx\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 7f[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 80[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 7f[ 	]*vpopcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 80[ 	]*vpopcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 55 f5[ 	]*vpopcntd zmm30,zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 4f 55 f5[ 	]*vpopcntd zmm30\{k7\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d cf 55 f5[ 	]*vpopcntd zmm30\{k7\}\{z\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 31[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 22 7d 48 55 b4 f0 34 12 00 00[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 31[ 	]*vpopcntd zmm30,DWORD PTR \[rcx\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 7f[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 80[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd zmm30,ZMMWORD PTR \[rdx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 7f[ 	]*vpopcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 80[ 	]*vpopcntd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 48 55 f5[ 	]*vpopcntq zmm30,zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 4f 55 f5[ 	]*vpopcntq zmm30\{k7\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd cf 55 f5[ 	]*vpopcntq zmm30\{k7\}\{z\},zmm29
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 31[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 22 fd 48 55 b4 f0 34 12 00 00[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 31[ 	]*vpopcntq zmm30,QWORD PTR \[rcx\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 7f[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 80[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx-0x2000\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq zmm30,ZMMWORD PTR \[rdx-0x2040\]
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 7f[ 	]*vpopcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 80[ 	]*vpopcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.d b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.d
new file mode 100644
index 0000000..0926917
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.d
@@ -0,0 +1,68 @@
+#as:
+#objdump: -dw
+#name: x86_64 AVX512/VPOPCNTDQ insns
+#source: x86-64-avx512_vpopcntdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 55 f5[ 	]*vpopcntd %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 4f 55 f5[ 	]*vpopcntd %zmm29,%zmm30\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d cf 55 f5[ 	]*vpopcntd %zmm29,%zmm30\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 31[ 	]*vpopcntd \(%rcx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 22 7d 48 55 b4 f0 23 01 00 00[ 	]*vpopcntd 0x123\(%rax,%r14,8\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 31[ 	]*vpopcntd \(%rcx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 7f[ 	]*vpopcntd 0x1fc0\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd 0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 80[ 	]*vpopcntd -0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd -0x2040\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 7f[ 	]*vpopcntd 0x1fc\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd 0x200\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 80[ 	]*vpopcntd -0x200\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd -0x204\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 48 55 f5[ 	]*vpopcntq %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 4f 55 f5[ 	]*vpopcntq %zmm29,%zmm30\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd cf 55 f5[ 	]*vpopcntq %zmm29,%zmm30\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 31[ 	]*vpopcntq \(%rcx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 22 fd 48 55 b4 f0 23 01 00 00[ 	]*vpopcntq 0x123\(%rax,%r14,8\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 31[ 	]*vpopcntq \(%rcx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 7f[ 	]*vpopcntq 0x1fc0\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq 0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 80[ 	]*vpopcntq -0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq -0x2040\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 7f[ 	]*vpopcntq 0x3f8\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq 0x400\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 80[ 	]*vpopcntq -0x400\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq -0x408\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 48 55 f5[ 	]*vpopcntd %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d 4f 55 f5[ 	]*vpopcntd %zmm29,%zmm30\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 7d cf 55 f5[ 	]*vpopcntd %zmm29,%zmm30\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 31[ 	]*vpopcntd \(%rcx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 22 7d 48 55 b4 f0 34 12 00 00[ 	]*vpopcntd 0x1234\(%rax,%r14,8\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 31[ 	]*vpopcntd \(%rcx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 7f[ 	]*vpopcntd 0x1fc0\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 00 20 00 00[ 	]*vpopcntd 0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 72 80[ 	]*vpopcntd -0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 48 55 b2 c0 df ff ff[ 	]*vpopcntd -0x2040\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 7f[ 	]*vpopcntd 0x1fc\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 00 02 00 00[ 	]*vpopcntd 0x200\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 72 80[ 	]*vpopcntd -0x200\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 7d 58 55 b2 fc fd ff ff[ 	]*vpopcntd -0x204\(%rdx\)\{1to16\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 48 55 f5[ 	]*vpopcntq %zmm29,%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd 4f 55 f5[ 	]*vpopcntq %zmm29,%zmm30\{%k7\}
+[ 	]*[a-f0-9]+:[ 	]*62 02 fd cf 55 f5[ 	]*vpopcntq %zmm29,%zmm30\{%k7\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 31[ 	]*vpopcntq \(%rcx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 22 fd 48 55 b4 f0 34 12 00 00[ 	]*vpopcntq 0x1234\(%rax,%r14,8\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 31[ 	]*vpopcntq \(%rcx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 7f[ 	]*vpopcntq 0x1fc0\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 00 20 00 00[ 	]*vpopcntq 0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 72 80[ 	]*vpopcntq -0x2000\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 48 55 b2 c0 df ff ff[ 	]*vpopcntq -0x2040\(%rdx\),%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 7f[ 	]*vpopcntq 0x3f8\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 00 04 00 00[ 	]*vpopcntq 0x400\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 72 80[ 	]*vpopcntq -0x400\(%rdx\)\{1to8\},%zmm30
+[ 	]*[a-f0-9]+:[ 	]*62 62 fd 58 55 b2 f8 fb ff ff[ 	]*vpopcntq -0x408\(%rdx\)\{1to8\},%zmm30
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.s b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.s
new file mode 100644
index 0000000..06e5ad2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx512_vpopcntdq.s
@@ -0,0 +1,63 @@
+# Check 64bit AVX512_VPOPCNTDQ instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vpopcntd	%zmm29, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	%zmm29, %zmm30{%k7}	 # AVX512_VPOPCNTDQ
+	vpopcntd	%zmm29, %zmm30{%k7}{z}	 # AVX512_VPOPCNTDQ
+	vpopcntd	(%rcx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	0x123(%rax,%r14,8), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	(%rcx){1to16}, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	8128(%rdx), %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	8192(%rdx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	-8192(%rdx), %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	-8256(%rdx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	508(%rdx){1to16}, %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	512(%rdx){1to16}, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntd	-512(%rdx){1to16}, %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	-516(%rdx){1to16}, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm29, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm29, %zmm30{%k7}	 # AVX512_VPOPCNTDQ
+	vpopcntq	%zmm29, %zmm30{%k7}{z}	 # AVX512_VPOPCNTDQ
+	vpopcntq	(%rcx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	0x123(%rax,%r14,8), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	(%rcx){1to8}, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	8128(%rdx), %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	8192(%rdx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	-8192(%rdx), %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	-8256(%rdx), %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	1016(%rdx){1to8}, %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	1024(%rdx){1to8}, %zmm30	 # AVX512_VPOPCNTDQ
+	vpopcntq	-1024(%rdx){1to8}, %zmm30	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	-1032(%rdx){1to8}, %zmm30	 # AVX512_VPOPCNTDQ
+
+	.intel_syntax noprefix
+	vpopcntd	zmm30, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30{k7}, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30{k7}{z}, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, ZMMWORD PTR [rcx]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, [rcx]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, ZMMWORD PTR [rdx+8128]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm30, ZMMWORD PTR [rdx+8192]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, ZMMWORD PTR [rdx-8192]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm30, ZMMWORD PTR [rdx-8256]	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, [rdx+508]{1to16}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm30, [rdx+512]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntd	zmm30, [rdx-512]{1to16}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntd	zmm30, [rdx-516]{1to16}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30{k7}, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30{k7}{z}, zmm29	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, ZMMWORD PTR [rcx]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, ZMMWORD PTR [rax+r14*8+0x1234]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, [rcx]{1to8}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, ZMMWORD PTR [rdx+8128]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm30, ZMMWORD PTR [rdx+8192]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, ZMMWORD PTR [rdx-8192]	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm30, ZMMWORD PTR [rdx-8256]	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, [rdx+1016]{1to8}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm30, [rdx+1024]{1to8}	 # AVX512_VPOPCNTDQ
+	vpopcntq	zmm30, [rdx-1024]{1to8}	 # AVX512_VPOPCNTDQ Disp8
+	vpopcntq	zmm30, [rdx-1032]{1to8}	 # AVX512_VPOPCNTDQ
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 267bad7..c119f55 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -390,7 +390,7 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F3852) },
     { PREFIX_TABLE (PREFIX_EVEX_0F3853) },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3855) },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 58 */
@@ -2019,6 +2019,12 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { "vp4dpwssds",	{ XM, Vex, EXxmm }, 0 },
   },
+  /* PREFIX_EVEX_0F3855 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_0F3855_P_2) },
+  },
   /* PREFIX_EVEX_0F3858 */
   {
     { Bad_Opcode },
@@ -3577,6 +3583,11 @@ static const struct dis386 evex_table[][256] = {
     { "vpmulld",	{ XM, Vex, EXx }, 0 },
     { "vpmullq",	{ XM, Vex, EXx }, 0 },
   },
+  /* EVEX_W_0F3855_P_2 */
+  {
+    { "vpopcntd",	{ XM, EXx }, 0 },
+    { "vpopcntq",	{ XM, EXx }, 0 },
+  },
   /* EVEX_W_0F3858_P_2 */
   {
     { "vpbroadcastd",	{ XM, EXxmm_md }, 0 },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ad0baf1..7b6a7e9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1548,6 +1548,7 @@ enum
   PREFIX_EVEX_0F384F,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
+  PREFIX_EVEX_0F3855,
   PREFIX_EVEX_0F3858,
   PREFIX_EVEX_0F3859,
   PREFIX_EVEX_0F385A,
@@ -2377,6 +2378,7 @@ enum
   EVEX_W_0F3839_P_1,
   EVEX_W_0F383A_P_1,
   EVEX_W_0F3840_P_2,
+  EVEX_W_0F3855_P_2,
   EVEX_W_0F3858_P_2,
   EVEX_W_0F3859_P_2,
   EVEX_W_0F385A_P_2,
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index eec3514..7a375f9 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -221,6 +221,8 @@ static initializer cpu_flag_init[] =
     "CPU_AVX512F_FLAGS|CpuAVX512_4FMAPS" },
   { "CPU_AVX512_4VNNIW_FLAGS",
     "CPU_AVX512F_FLAGS|CpuAVX512_4VNNIW" },
+  { "CPU_AVX512_VPOPCNTDQ_FLAGS",
+    "CPU_AVX512F_FLAGS|CpuAVX512_VPOPCNTDQ" },
   { "CPU_L1OM_FLAGS",
     "unknown" },
   { "CPU_K1OM_FLAGS",
@@ -288,7 +290,7 @@ static initializer cpu_flag_init[] =
   { "CPU_ANY_AVX2_FLAGS",
     "CpuAVX2" },
   { "CPU_ANY_AVX512F_FLAGS",
-    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512F" },
+    "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512F" },
   { "CPU_ANY_AVX512CD_FLAGS",
     "CpuAVX512CD" },
   { "CPU_ANY_AVX512ER_FLAGS",
@@ -309,6 +311,8 @@ static initializer cpu_flag_init[] =
     "CpuAVX512_4FMAPS" },
   { "CPU_ANY_AVX512_4VNNIW_FLAGS",
     "CpuAVX512_4VNNIW" },
+  { "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS",
+    "CpuAVX512_VPOPCNTDQ" },
 };
 
 static initializer operand_type_init[] =
@@ -514,6 +518,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuAVX512VBMI),
   BITFIELD (CpuAVX512_4FMAPS),
   BITFIELD (CpuAVX512_4VNNIW),
+  BITFIELD (CpuAVX512_VPOPCNTDQ),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index ba04ce4..076ff4f 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -196,6 +196,8 @@ enum
   CpuAVX512_4FMAPS,
   /* Intel AVX-512 4VNNIW Instructions support required.  */
   CpuAVX512_4VNNIW,
+  /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
+  CpuAVX512_VPOPCNTDQ,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -321,6 +323,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512vbmi:1;
       unsigned int cpuavx512_4fmaps:1;
       unsigned int cpuavx512_4vnniw:1;
+      unsigned int cpuavx512_vpopcntdq:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index fba01b6..3af770d 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5941,7 +5941,15 @@ vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|VexOpco
 vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vp4dpwssds, 3, 0xf253, None, 1, CpuAVX512_4VNNIW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
 
-// AVX512_4VNNIW instructions
+// AVX512_4VNNIW instructions end
+
+// AVX512_VPOPCNTDQ instructions
+
+vpopcntd, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
+
+vpopcntq, 2, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
+
+// AVX512_VPOPCNTDQ instructions end
 
 // CLZERO instructions
 
-- 
1.8.3.1

