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[PATCH] [ARC] Fix printing 'b' mnemonics.
- From: Claudiu Zissulescu <Claudiu dot Zissulescu at synopsys dot com>
- To: <binutils at sourceware dot org>
- Cc: <Claudiu dot Zissulescu at synopsys dot com>, <Francois dot Bedard at synopsys dot com>
- Date: Fri, 18 Nov 2016 15:14:14 +0100
- Subject: [PATCH] [ARC] Fix printing 'b' mnemonics.
- Authentication-results: sourceware.org; auth=none
The order of C_CC and C_D is wrong leading to wrongly displaying a
predicated 'b' mnemonic which is having also a delay slot. This patch
solves this issue and fixes a testbench.
Ok to apply?
Claudiu
gas/
2016-11-09 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test result.
opcode/
2016-11-09 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
instructions.
---
gas/testsuite/gas/arc/b.d | 4 ++--
opcodes/arc-tbl.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gas/testsuite/gas/arc/b.d b/gas/testsuite/gas/arc/b.d
index 87afdc0..50bc305 100644
--- a/gas/testsuite/gas/arc/b.d
+++ b/gas/testsuite/gas/arc/b.d
@@ -39,8 +39,8 @@ Disassembly of section .text:
78: 0789 ffcf b 0 <text_label>
7c: 0785 ffef b.d 0 <text_label>
80: 264a 7000 mov 0,0
- 84: 077c ffe1 b.deq -132
+ 84: 077c ffe1 beq.d -132
88: 264a 7000 mov 0,0
8c: 0774 ffc2 bne -140
- 90: 0770 ffe6 b.dnc -144
+ 90: 0770 ffe6 bnc.d -144
94: 264a 7000 mov 0,0
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 3246d8d..c6e246e 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -1394,7 +1394,7 @@
{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */
-{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }},
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */
{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
--
1.9.1