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[PATCH 4/7] opcodes/arc: Make some macros 64-bit safe
- From: Graham Markall <graham dot markall at embecosm dot com>
- To: binutils at sourceware dot org
- Cc: claudiu dot zissulescu at synopsys dot com, noamca at mellanox dot com, rinat at mellanox dot com, guybe at mellanox dot com, andrew dot burgess at embecosm dot com, Graham Markall <graham dot markall at embecosm dot com>
- Date: Wed, 26 Oct 2016 13:46:03 +0100
- Subject: [PATCH 4/7] opcodes/arc: Make some macros 64-bit safe
- Authentication-results: sourceware.org; auth=none
- References: <cover.1477409669.git.graham.markall@embecosm.com>
- References: <cover.1477409669.git.graham.markall@embecosm.com>
In preparation to moving to a world where arc instructions can be 2, 4,
6, or 8 bytes long, make some macros 64-bit safe.
There should be no functional change after this commit.
include/ChangeLog:
* opcode/arc.h: Make macros 64-bit safe.
---
include/ChangeLog | 4 ++++
include/opcode/arc.h | 54 +++++++++++++++++++++++++++-------------------------
2 files changed, 32 insertions(+), 26 deletions(-)
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 34a7fa7..5e10d2a 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -529,26 +529,28 @@ extern const unsigned arc_num_relax_opcodes;
#define INSN3OP_C0LU(MOP,SOP) \
(INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
-#define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
-#define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
-#define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
-#define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
-#define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
-#define MINSN3OP_0LL (~(FIELDF))
-#define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
-#define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
-#define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
-#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
-#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
-#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
-#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
-#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
+#define MASK_32BIT(VAL) (0xffffffff & (VAL))
+
+#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
+#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
+#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
+#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
+#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
+#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
+#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
+#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
+#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
+#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
+#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
+#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
+#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
+#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
@@ -557,12 +559,12 @@ extern const unsigned arc_num_relax_opcodes;
#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
-#define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
-#define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
-#define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
-#define MINSN2OP_0L (~(FIELDF))
-#define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
-#define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
+#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
+#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
+#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
+#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
+#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
+#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
/* Various constants used when defining an extension instruction. */
#define ARC_SYNTAX_3OP (1 << 0)
--
2.7.4