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Re: [PATCH 1/6] RISC-V bfd port
On Tue, Oct 11, 2016 at 06:17:59PM -0700, Andrew Waterman wrote:
> On Tuesday, October 11, 2016, Alan Modra <email@example.com> wrote:
> > On Tue, Oct 11, 2016 at 04:46:06PM -0700, Andrew Waterman wrote:
> > > +/* Remember all PC-relative high-part relocs we've encountered to help
> > us
> > > + later resolve the corresponding low-part relocs. */
> > Why? This sort of thing is usually only needed on REL targets.
> We'll expound on this comment to explain our strategy. Of course, a simpler
> approach might suffice.
It's not a matter of explaining. I think you have something seriously
wrong here. You most likely need to remove all of the hi/lo recording
and use of high value to apply low relocs, or you have a broken ABI.
If the latter then it would pay to fix it sooner rather than later.
The reason hi/lo matching is needed on REL targets is that with the
addend stored in the insn you can only fit a partial addend in an
insn. You need to read both insns and combine the addends to create a
full addend (which is needed to properly perform pc subtraction).
With RELA targets you should have the full addend in the reloc.
Australia Development Lab, IBM