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Re: [GAS][ARM]Generate unpredictable warning for pc used in data processing instructions with register-shifted register operand

Hi Nick,

In ARMARM (ARMv7-A and ARMv7-R edition),

In section [A2.3.1 Writing to the PC], there is a sentence:
"The register-shifted register instructions, that are available only in the ARM instruction set and are summarized in Data-processing (register-shifted register) on page A5-198, cannot write to the PC."

[section A5.5.2 Data-processing (register-shifted register)]
There is table of data processing instructions which allow register-shifted register operand.

In each individual instruction description, there is piece of pseudo code to describe the unpredictable behavior conditions.
For example:

ADD (register-shifted register)
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
ADD{S}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>

d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
setflags = (S == ‘1’); shift_t = DecodeRegShift(type);
if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;


On 11/10/16 09:42, Nick Clifton wrote:
Hi Renlin,

According to ARMARM, the behavior of instructions with register-shifted register
is unpredictable when PC is used in any field.

Just for my own information really - please can you tell me where in the ARMARM
this restriction is specified.  I did a quick search and could not find it. :-(


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