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[2.26 backport][AArch64] PR target/20553, fix opcode mask for SIMD multiply by element
On 29/09/16 14:46, Jiong Wang wrote:
On 29/09/16 14:27, Ramana Radhakrishnan wrote:
On Thu, Sep 29, 2016 at 2:16 PM, Nick Clifton <nickc@redhat.com> wrote:
Hi Jiong,
opcode/
2016-09-27 Jiong Wang <jiong.wang@arm.com>
* aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask
field.
gas/
2016-09-27 Jiong Wang <jiong.wang@arm.com>
* testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New
high index
testcases for H and S variants. New low index testcases
for D variant.
* testsuite/gas/aarch64/advsimd-fp16.d: Update expected
results.
Approved - please apply.
Jiong while you are at it - What release branches should this go into?
I think it needs to be backported to 2.26 and 2.27.
Unfortunately, this patch won't apply cleanly on either. For
aarch64-tbl.h, after 2.26 we introduced some wrapper macros, and after
2.27 we adjusted parameters of those macros. The change will be
trivial, I will send out two backport patches shortly.
Thanks.
Here is the backport patch to 2.26, build & cross gas check OK against 2.26 branch.
OK to backport?
opcode/
2016-09-29 Jiong Wang <jiong.wang@arm.com>
PR target/20553
* aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
gas/
2016-09-29 Jiong Wang <jiong.wang@arm.com>
PR target/20553
* testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
testcases for H and S variants. New low index testcases for D variant.
* testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index b29c9da..d7ab5fe 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -435,6 +435,9 @@ Disassembly of section \.text:
[0-9a-f]+: 0f031041 fmla v1.4h, v2.4h, v3.h\[0\]
[0-9a-f]+: 4f001000 fmla v0.8h, v0.8h, v0.h\[0\]
[0-9a-f]+: 4f031041 fmla v1.8h, v2.8h, v3.h\[0\]
+ [0-9a-f]+: 4fca10a1 fmla v1.2d, v5.2d, v10.d\[0\]
+ [0-9a-f]+: 0fab1808 fmla v8.2s, v0.2s, v11.s\[3\]
+ [0-9a-f]+: 0f3f1920 fmla v0.4h, v9.4h, v15.h\[7\]
[0-9a-f]+: 4fc35841 fmls v1.2d, v2.2d, v3.d\[1\]
[0-9a-f]+: 0f835841 fmls v1.2s, v2.2s, v3.s\[2\]
[0-9a-f]+: 4fa35041 fmls v1.4s, v2.4s, v3.s\[1\]
@@ -442,6 +445,9 @@ Disassembly of section \.text:
[0-9a-f]+: 0f035041 fmls v1.4h, v2.4h, v3.h\[0\]
[0-9a-f]+: 4f005000 fmls v0.8h, v0.8h, v0.h\[0\]
[0-9a-f]+: 4f035041 fmls v1.8h, v2.8h, v3.h\[0\]
+ [0-9a-f]+: 4fca50a1 fmls v1.2d, v5.2d, v10.d\[0\]
+ [0-9a-f]+: 0fab5808 fmls v8.2s, v0.2s, v11.s\[3\]
+ [0-9a-f]+: 0f3f5920 fmls v0.4h, v9.4h, v15.h\[7\]
[0-9a-f]+: 4fc39841 fmul v1.2d, v2.2d, v3.d\[1\]
[0-9a-f]+: 0f839841 fmul v1.2s, v2.2s, v3.s\[2\]
[0-9a-f]+: 4fa39041 fmul v1.4s, v2.4s, v3.s\[1\]
@@ -449,6 +455,9 @@ Disassembly of section \.text:
[0-9a-f]+: 0f039041 fmul v1.4h, v2.4h, v3.h\[0\]
[0-9a-f]+: 4f009000 fmul v0.8h, v0.8h, v0.h\[0\]
[0-9a-f]+: 4f039041 fmul v1.8h, v2.8h, v3.h\[0\]
+ [0-9a-f]+: 4fca90a1 fmul v1.2d, v5.2d, v10.d\[0\]
+ [0-9a-f]+: 0fab9808 fmul v8.2s, v0.2s, v11.s\[3\]
+ [0-9a-f]+: 0f3f9920 fmul v0.4h, v9.4h, v15.h\[7\]
[0-9a-f]+: 6fc39841 fmulx v1.2d, v2.2d, v3.d\[1\]
[0-9a-f]+: 2f839841 fmulx v1.2s, v2.2s, v3.s\[2\]
[0-9a-f]+: 6fa39041 fmulx v1.4s, v2.4s, v3.s\[1\]
@@ -456,6 +465,9 @@ Disassembly of section \.text:
[0-9a-f]+: 2f039041 fmulx v1.4h, v2.4h, v3.h\[0\]
[0-9a-f]+: 6f009000 fmulx v0.8h, v0.8h, v0.h\[0\]
[0-9a-f]+: 6f039041 fmulx v1.8h, v2.8h, v3.h\[0\]
+ [0-9a-f]+: 6fca90a1 fmulx v1.2d, v5.2d, v10.d\[0\]
+ [0-9a-f]+: 2fab9808 fmulx v8.2s, v0.2s, v11.s\[3\]
+ [0-9a-f]+: 2f3f9920 fmulx v0.4h, v9.4h, v15.h\[7\]
[0-9a-f]+: 5fc31841 fmla d1, d2, v3.d\[1\]
[0-9a-f]+: 5fa31041 fmla s1, s2, v3.s\[1\]
[0-9a-f]+: 5f131041 fmla h1, h2, v3.h\[1\]
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 8be4854..6b86ded 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -165,6 +165,9 @@
\op v1.4h, v2.4h, v3.h[0]
\op v0.8h, v0.8h, v0.h[0]
\op v1.8h, v2.8h, v3.h[0]
+ \op v1.2d, v5.2d, v10.d[0]
+ \op v8.2s, v0.2s, v11.s[3]
+ \op v0.4h, v9.4h, v15.h[7]
.endm
indexed_elem fmla
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 11c97af..2c98c9f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1513,13 +1513,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
+ {"fmla", 0xf001000, 0xbfc0f400, asimdelem, 0, SIMD_F16,
OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
{"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
+ {"fmls", 0xf005000, 0xbfc0f400, asimdelem, 0, SIMD_F16,
OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
{"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
+ {"fmul", 0xf009000, 0xbfc0f400, asimdelem, 0, SIMD_F16,
OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
{"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
@@ -1530,7 +1530,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
{"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
{"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
- {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
+ {"fmulx", 0x2f009000, 0xbfc0f400, asimdelem, 0, SIMD_F16,
OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
{"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},