This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH 1/4] bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
- From: "Jose E. Marchesi" <jose dot marchesi at oracle dot com>
- To: binutils at sourceware dot org
- Date: Wed, 15 Jun 2016 18:00:50 +0200
- Subject: [PATCH 1/4] bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
- Authentication-results: sourceware.org; auth=none
- References: <1466006453-1022-1-git-send-email-jose dot marchesi at oracle dot com>
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
---
bfd/ChangeLog | 22 ++++++++
bfd/aoutx.h | 12 +++-
bfd/archures.c | 20 ++++++-
bfd/bfd-in2.h | 20 ++++++-
bfd/cpu-sparc.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++++
bfd/elf32-sparc.c | 5 ++
bfd/elfxx-sparc.c | 57 ++++++++++++++++++-
include/ChangeLog | 7 +++
include/opcode/sparc.h | 6 ++
opcodes/ChangeLog | 25 +++++++++
opcodes/sparc-dis.c | 22 +++++++-
opcodes/sparc-opc.c | 52 ++++++++++++++---
12 files changed, 382 insertions(+), 16 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 38d28f3..4031816 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,25 @@
+2016-06-15 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * archures.c (bfd_mach_sparc_v8plusc): Define.
+ (bfd_mach_sparc_v9c): Likewise.
+ (bfd_mach_sparc_v8plusd): Likewise.
+ (bfd_mach_sparc_v9d): Likewise.
+ (bfd_mach_sparc_v8pluse): Likewise.
+ (bfd_mach_sparc_v9e): Likewise.
+ (bfd_mach_sparc_v8plusv): Likewise
+ (bfd_mach_sparc_v9v): Likewise.
+ (bfd_mach_sparc_v8plusm): Likewise.
+ (bfd_mach_sparc_v9m): Likewise.
+ (bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
+ (bfd_mach_sparc_64bit_p): Likewise.
+ * bfd-in2.h: Regenerate.
+ * cpu-sparc.c (arch_info_struct): Add entries for
+ bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
+ * aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
+ and bfd_mach_sparc_v9{c,d,e,v,m}.
+ * elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
+ * elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
+
2016-06-14 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/20254
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index 75ba68b..be0126a 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -733,9 +733,19 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
|| machine == bfd_mach_sparc_v8plus
|| machine == bfd_mach_sparc_v8plusa
|| machine == bfd_mach_sparc_v8plusb
+ || machine == bfd_mach_sparc_v8plusc
+ || machine == bfd_mach_sparc_v8plusd
+ || machine == bfd_mach_sparc_v8pluse
+ || machine == bfd_mach_sparc_v8plusv
+ || machine == bfd_mach_sparc_v8plusm
|| machine == bfd_mach_sparc_v9
|| machine == bfd_mach_sparc_v9a
- || machine == bfd_mach_sparc_v9b)
+ || machine == bfd_mach_sparc_v9b
+ || machine == bfd_mach_sparc_v9c
+ || machine == bfd_mach_sparc_v9d
+ || machine == bfd_mach_sparc_v9e
+ || machine == bfd_mach_sparc_v9v
+ || machine == bfd_mach_sparc_v9m)
arch_flags = M_SPARC;
else if (machine == bfd_mach_sparc_sparclet)
arch_flags = M_SPARCLET;
diff --git a/bfd/archures.c b/bfd/archures.c
index 7ff1e82..a00c712 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -137,13 +137,29 @@ DESCRIPTION
.#define bfd_mach_sparc_v9a 8 {* with ultrasparc add'ns. *}
.#define bfd_mach_sparc_v8plusb 9 {* with cheetah add'ns. *}
.#define bfd_mach_sparc_v9b 10 {* with cheetah add'ns. *}
+.#define bfd_mach_sparc_v8plusc 11 {* with UA2005 and T1 add'ns. *}
+.#define bfd_mach_sparc_v9c 12 {* with UA2005 and T1 add'ns. *}
+.#define bfd_mach_sparc_v8plusd 13 {* with UA2007 and T3 add'ns. *}
+.#define bfd_mach_sparc_v9d 14 {* with UA2007 and T3 add'ns. *}
+.#define bfd_mach_sparc_v8pluse 15 {* with OSA2001 and T4 add'ns (no IMA). *}
+.#define bfd_mach_sparc_v9e 16 {* with OSA2001 and T4 add'ns (no IMA). *}
+.#define bfd_mach_sparc_v8plusv 17 {* with OSA2011 and T4 and IMA and FJMAU add'ns. *}
+.#define bfd_mach_sparc_v9v 18 {* with OSA2011 and T4 and IMA and FJMAU add'ns. *}
+.#define bfd_mach_sparc_v8plusm 19 {* with OSA2015 and M7 add'ns. *}
+.#define bfd_mach_sparc_v9m 20 {* with OSA2015 and M7 add'ns. *}
.{* Nonzero if MACH has the v9 instruction set. *}
.#define bfd_mach_sparc_v9_p(mach) \
-. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
+. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
. && (mach) != bfd_mach_sparc_sparclite_le)
.{* Nonzero if MACH is a 64 bit sparc architecture. *}
.#define bfd_mach_sparc_64bit_p(mach) \
-. ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
+. ((mach) >= bfd_mach_sparc_v9 \
+. && (mach) != bfd_mach_sparc_v8plusb \
+. && (mach) != bfd_mach_sparc_v8plusc \
+. && (mach) != bfd_mach_sparc_v8plusd \
+. && (mach) != bfd_mach_sparc_v8pluse \
+. && (mach) != bfd_mach_sparc_v8plusv \
+. && (mach) != bfd_mach_sparc_v8plusm)
. bfd_arch_spu, {* PowerPC SPU *}
.#define bfd_mach_spu 256
. bfd_arch_mips, {* MIPS Rxxxx *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 2d6237c..6489c60 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1948,13 +1948,29 @@ enum bfd_architecture
#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
+#define bfd_mach_sparc_v8plusc 11 /* with UA2005 and T1 add'ns. */
+#define bfd_mach_sparc_v9c 12 /* with UA2005 and T1 add'ns. */
+#define bfd_mach_sparc_v8plusd 13 /* with UA2007 and T3 add'ns. */
+#define bfd_mach_sparc_v9d 14 /* with UA2007 and T3 add'ns. */
+#define bfd_mach_sparc_v8pluse 15 /* with OSA2001 and T4 add'ns (no IMA). */
+#define bfd_mach_sparc_v9e 16 /* with OSA2001 and T4 add'ns (no IMA). */
+#define bfd_mach_sparc_v8plusv 17 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */
+#define bfd_mach_sparc_v9v 18 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */
+#define bfd_mach_sparc_v8plusm 19 /* with OSA2015 and M7 add'ns. */
+#define bfd_mach_sparc_v9m 20 /* with OSA2015 and M7 add'ns. */
/* Nonzero if MACH has the v9 instruction set. */
#define bfd_mach_sparc_v9_p(mach) \
- ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
+ ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
&& (mach) != bfd_mach_sparc_sparclite_le)
/* Nonzero if MACH is a 64 bit sparc architecture. */
#define bfd_mach_sparc_64bit_p(mach) \
- ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
+ ((mach) >= bfd_mach_sparc_v9 \
+ && (mach) != bfd_mach_sparc_v8plusb \
+ && (mach) != bfd_mach_sparc_v8plusc \
+ && (mach) != bfd_mach_sparc_v8plusd \
+ && (mach) != bfd_mach_sparc_v8pluse \
+ && (mach) != bfd_mach_sparc_v8plusv \
+ && (mach) != bfd_mach_sparc_v8plusm)
bfd_arch_spu, /* PowerPC SPU */
#define bfd_mach_spu 256
bfd_arch_mips, /* MIPS Rxxxx */
diff --git a/bfd/cpu-sparc.c b/bfd/cpu-sparc.c
index 0d25012..8de7250 100644
--- a/bfd/cpu-sparc.c
+++ b/bfd/cpu-sparc.c
@@ -157,6 +157,156 @@ static const bfd_arch_info_type arch_info_struct[] =
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
+ &arch_info_struct[9],
+ },
+ {
+ 32, /* bits in a word */
+ 32, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v8plusc,
+ "sparc",
+ "sparc:v8plusc",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[10],
+ },
+ {
+ 64, /* bits in a word */
+ 64, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v9c,
+ "sparc",
+ "sparc:v9c",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[11],
+ },
+ {
+ 32, /* bits in a word */
+ 32, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v8plusd,
+ "sparc",
+ "sparc:v8plusd",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[12],
+ },
+ {
+ 64, /* bits in a word */
+ 64, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v9d,
+ "sparc",
+ "sparc:v9d",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[13],
+ },
+ {
+ 32, /* bits in a word */
+ 32, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v8pluse,
+ "sparc",
+ "sparc:v8pluse",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[14],
+ },
+ {
+ 64, /* bits in a word */
+ 64, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v9e,
+ "sparc",
+ "sparc:v9e",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[15],
+ },
+ {
+ 32, /* bits in a word */
+ 32, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v8plusv,
+ "sparc",
+ "sparc:v8plusv",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[16],
+ },
+ {
+ 64, /* bits in a word */
+ 64, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v9v,
+ "sparc",
+ "sparc:v9v",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[17],
+ },
+ {
+ 32, /* bits in a word */
+ 32, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v8plusm,
+ "sparc",
+ "sparc:v8plusm",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ &arch_info_struct[18],
+ },
+ {
+ 64, /* bits in a word */
+ 64, /* bits in an address */
+ 8, /* bits in a byte */
+ bfd_arch_sparc,
+ bfd_mach_sparc_v9m,
+ "sparc",
+ "sparc:v9m",
+ 3,
+ FALSE,
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
0,
}
};
diff --git a/bfd/elf32-sparc.c b/bfd/elf32-sparc.c
index 5f20846..0e0d90c 100644
--- a/bfd/elf32-sparc.c
+++ b/bfd/elf32-sparc.c
@@ -136,6 +136,11 @@ elf32_sparc_final_write_processing (bfd *abfd,
elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1;
break;
case bfd_mach_sparc_v8plusb :
+ case bfd_mach_sparc_v8plusc :
+ case bfd_mach_sparc_v8plusd :
+ case bfd_mach_sparc_v8pluse :
+ case bfd_mach_sparc_v8plusv :
+ case bfd_mach_sparc_v8plusm :
elf_elfheader (abfd)->e_machine = EM_SPARC32PLUS;
elf_elfheader (abfd)->e_flags &=~ EF_SPARC_32PLUS_MASK;
elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1
diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index d2c24d8..3c47255 100644
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -4830,11 +4830,49 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *i
bfd_boolean
_bfd_sparc_elf_object_p (bfd *abfd)
{
+ obj_attribute *attrs = elf_known_obj_attributes (abfd)[OBJ_ATTR_GNU];
+ obj_attribute *hwcaps = &attrs[Tag_GNU_Sparc_HWCAPS];
+ obj_attribute *hwcaps2 = &attrs[Tag_GNU_Sparc_HWCAPS2];
+
+ unsigned int v9c_hwcaps_mask = ELF_SPARC_HWCAP_ASI_BLK_INIT;
+ unsigned int v9d_hwcaps_mask = (ELF_SPARC_HWCAP_FMAF
+ | ELF_SPARC_HWCAP_VIS3
+ | ELF_SPARC_HWCAP_HPC);
+ unsigned int v9e_hwcaps_mask = (ELF_SPARC_HWCAP_AES
+ | ELF_SPARC_HWCAP_DES
+ | ELF_SPARC_HWCAP_KASUMI
+ | ELF_SPARC_HWCAP_CAMELLIA
+ | ELF_SPARC_HWCAP_MD5
+ | ELF_SPARC_HWCAP_SHA1
+ | ELF_SPARC_HWCAP_SHA256
+ | ELF_SPARC_HWCAP_SHA512
+ | ELF_SPARC_HWCAP_MPMUL
+ | ELF_SPARC_HWCAP_MONT
+ | ELF_SPARC_HWCAP_CRC32C
+ | ELF_SPARC_HWCAP_CBCOND
+ | ELF_SPARC_HWCAP_PAUSE);
+ unsigned int v9v_hwcaps_mask = (ELF_SPARC_HWCAP_FJFMAU
+ | ELF_SPARC_HWCAP_IMA);
+ unsigned int v9m_hwcaps2_mask = (ELF_SPARC_HWCAP2_SPARC5
+ | ELF_SPARC_HWCAP2_MWAIT
+ | ELF_SPARC_HWCAP2_XMPMUL
+ | ELF_SPARC_HWCAP2_XMONT);
+
if (ABI_64_P (abfd))
{
unsigned long mach = bfd_mach_sparc_v9;
- if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
+ if (hwcaps2->i & v9m_hwcaps2_mask)
+ mach = bfd_mach_sparc_v9m;
+ else if (hwcaps->i & v9v_hwcaps_mask)
+ mach = bfd_mach_sparc_v9v;
+ else if (hwcaps->i & v9e_hwcaps_mask)
+ mach = bfd_mach_sparc_v9e;
+ else if (hwcaps->i & v9d_hwcaps_mask)
+ mach = bfd_mach_sparc_v9d;
+ else if (hwcaps->i & v9c_hwcaps_mask)
+ mach = bfd_mach_sparc_v9c;
+ else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
mach = bfd_mach_sparc_v9b;
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
mach = bfd_mach_sparc_v9a;
@@ -4844,7 +4882,22 @@ _bfd_sparc_elf_object_p (bfd *abfd)
{
if (elf_elfheader (abfd)->e_machine == EM_SPARC32PLUS)
{
- if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
+ if (hwcaps2->i & v9m_hwcaps2_mask)
+ return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+ bfd_mach_sparc_v8plusm);
+ else if (hwcaps->i & v9v_hwcaps_mask)
+ return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+ bfd_mach_sparc_v8plusv);
+ else if (hwcaps->i & v9e_hwcaps_mask)
+ return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+ bfd_mach_sparc_v8pluse);
+ else if (hwcaps->i & v9d_hwcaps_mask)
+ return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+ bfd_mach_sparc_v8plusd);
+ else if (hwcaps->i & v9c_hwcaps_mask)
+ return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
+ bfd_mach_sparc_v8plusc);
+ else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
bfd_mach_sparc_v8plusb);
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
diff --git a/include/ChangeLog b/include/ChangeLog
index 46a2f3a..e3cad70 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-15 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * opcode/sparc.h (enum sparc_opcode_arch_val): Add
+ SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
+ SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
+ SPARC_OPCODE_ARCH_V9M.
+
2016-06-14 John Baldwin <jhb@FreeBSD.org>
* opcode/msp430-decode.h (MSP430_Size): Remove.
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 29ed2e4..57225b6 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -52,6 +52,12 @@ enum sparc_opcode_arch_val
SPARC_OPCODE_ARCH_V9,
SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
+ SPARC_OPCODE_ARCH_V9C, /* V9 with UA2005 and T1 additions. */
+ SPARC_OPCODE_ARCH_V9D, /* V9 with UA2007 and T3 additions. */
+ SPARC_OPCODE_ARCH_V9E, /* V9 with OSA2011 and T4 additions modulus integer multiply-add. */
+ SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
+ multiply and Fujitsu fp multiply-add. */
+ SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9ca0760..5fbad96 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,28 @@
+2016-06-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
+ (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
+ bfd_mach_sparc_v9{c,d,e,v,m}.
+ * sparc-opc.c (MASK_V9C): Define.
+ (MASK_V9D): Likewise.
+ (MASK_V9E): Likewise.
+ (MASK_V9V): Likewise.
+ (MASK_V9M): Likewise.
+ (v6): Add MASK_V9{C,D,E,V,M}.
+ (v6notlet): Likewise.
+ (v7): Likewise.
+ (v8): Likewise.
+ (v9): Likewise.
+ (v9andleon): Likewise.
+ (v9a): Likewise.
+ (v9b): Likewise.
+ (v9c): Define.
+ (v9d): Likewise.
+ (v9e): Likewise.
+ (v9v): Likewise.
+ (v9m): Likewise.
+ (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
+
2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-opc.c (extract_rhv1): Extract value from insn.
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 435ad66..c6f73ff 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -28,7 +28,12 @@
/* Bitmask of v9 architectures. */
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
| (1 << SPARC_OPCODE_ARCH_V9A) \
- | (1 << SPARC_OPCODE_ARCH_V9B))
+ | (1 << SPARC_OPCODE_ARCH_V9B) \
+ | (1 << SPARC_OPCODE_ARCH_V9C) \
+ | (1 << SPARC_OPCODE_ARCH_V9D) \
+ | (1 << SPARC_OPCODE_ARCH_V9E) \
+ | (1 << SPARC_OPCODE_ARCH_V9V) \
+ | (1 << SPARC_OPCODE_ARCH_V9M))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
@@ -241,6 +246,21 @@ compute_arch_mask (unsigned long mach)
case bfd_mach_sparc_v8plusb :
case bfd_mach_sparc_v9b :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
+ case bfd_mach_sparc_v8plusc :
+ case bfd_mach_sparc_v9c :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C);
+ case bfd_mach_sparc_v8plusd :
+ case bfd_mach_sparc_v9d :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D);
+ case bfd_mach_sparc_v8pluse :
+ case bfd_mach_sparc_v9e :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E);
+ case bfd_mach_sparc_v8plusv :
+ case bfd_mach_sparc_v9v :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V);
+ case bfd_mach_sparc_v8plusm :
+ case bfd_mach_sparc_v9m :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
}
abort ();
}
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index e40ce37..14e4cce 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -37,17 +37,25 @@
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
+#define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
+#define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
+#define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
+#define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
+#define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
/* Bit masks of architectures supporting the insn. */
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLET | MASK_SPARCLITE \
- | MASK_V9 | MASK_V9A | MASK_V9B)
+ | MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
/* v6 insns not supported on the sparclet. */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
- | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
+ | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
#define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
- | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
+ | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
/* Although not all insns are implemented in hardware, sparclite is defined
to be a superset of v8. Unimplemented insns trap and are then theoretically
implemented in software.
@@ -55,16 +63,28 @@
suggest it is. Rather than complicating things, the sparclet assembler
recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
- | MASK_V9 | MASK_V9A | MASK_V9B)
+ | MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
#define sparclet (MASK_SPARCLET)
/* sparclet insns supported by leon. */
#define letandleon (MASK_SPARCLET | MASK_LEON)
#define sparclite (MASK_SPARCLITE)
-#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
+#define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
/* v9 insns supported by leon. */
-#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B | MASK_LEON)
-#define v9a (MASK_V9A | MASK_V9B)
-#define v9b (MASK_V9B)
+#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
+ | MASK_LEON)
+#define v9a (MASK_V9A | MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9b (MASK_V9B \
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9e (MASK_V9E | MASK_V9V | MASK_V9M)
+#define v9v (MASK_V9V | MASK_V9M)
+#define v9m (MASK_V9M)
+
/* v6 insns not supported by v9. */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLET | MASK_SPARCLITE)
@@ -89,6 +109,22 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
/* v9 with cheetah additions */
{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
+ /* v9 with UA2005 and T1 additions. */
+ { "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+ | MASK_V9C) },
+ /* v9 with UA2007 and T3 additions. */
+ { "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+ | MASK_V9C | MASK_V9D) },
+ /* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
+ { "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+ | MASK_V9C | MASK_V9D | MASK_V9E) },
+ /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
+ multiply-add. */
+ { "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V) },
+ /* v9 with OSA2015 and M7 additions. */
+ { "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) },
{ NULL, 0 }
};
--
2.3.4