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[PATCH, binutils/ARM] Add Thumb-2 long branch veneers

From: Thomas Preudhomme <thomas dot preudhomme at foss dot arm dot com>
To: binutils at sourceware dot org, nickc at redhat dot com, amodra at gmail dot com, richard dot earnshaw at arm dot com
Date: Tue, 14 Jun 2016 12:10:51 +0100
Subject: [PATCH, binutils/ARM] Add Thumb-2 long branch veneers
Authentication-results: sourceware.org; auth=none

Currently, the binutils will only generate thumb1 encoding veneer routine for 
long banch:

<__dest_veneer>:
push {r0}
ldr r0, [pc, #8] ; (800b17c <__dest_veneer+0xc>)
mov ip, r0
pop {r0}
bx ip
nop
.word 0x00000169

But the optimal way should be the following on target supporting thumb-2 
instruction set:

00008008 <__dest_veneer>:
ldr.w   ip, [pc, #4]  ; 8010 <__dest_veneer+0x8>
bx      ip
nop
.word   0x00108005
.word   0x00000000

This patch just use a new veneer instruction sequence called 
elf32_arm_stub_long_branch_thumb2_only to enable the thumb2 encoding veneer.

ChangeLog entries are as follow:


*** bfd/ChangeLog ***

2016-05-23  Thomas Preud'homme  <thomas.preudhomme@arm.com>
            Tony Wang  <tony.wang@arm.com>

        * elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub
        sequence.
        (stub_long_branch_thumb2_only): Define stub.
        (arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only.
        (arm_stub_long_branch_thumb2_only): Likewise.
        (arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2
        capable targets.


*** ld/testsuite/ChangeLog ***

2016-05-23  Thomas Preud'homme  <thomas.preudhomme@arm.com>
            Tony Wang  <tony.wang@arm.com>

        * ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile): Assemble for
        ARMv6-M.
        (Thumb2-Thumb2 farcall M profile): New testcase.
        * ld-arm/farcall-thumb2-thumb2-m.d: New file.
        * ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to reflect
        the use of Thumb-2 veneers for Thumb-2 capable targets.
        * ld-arm/jump-reloc-veneers-cond-long.d: Likewise.


Please find patch in attachment.

Testsuite shows no regression when run for arm-none-eabi target neither does 
GCC testsuite when targetting Thumb-2 target (-mcpu=cortex-m3).

Is this ok for master branch?

Best regards.

Thomas

diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bf93e9f5b345159a60910f3390a1580f60bee06c..4f7966244bc6b61a1671f0958c8a38925f9e57f1 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -2402,6 +2402,13 @@ static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
   DATA_WORD (0, R_ARM_ABS32, 0),     /* dcd  R_ARM_ABS32(X) */
 };
 
+/* Thumb -> Thumb long branch stub in thumb2 encoding.  Used on armv7.  */
+static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
+{
+  THUMB32_INSN (0xf85ff000),         /* ldr.w  pc, [pc, #-0] */
+  DATA_WORD (0, R_ARM_ABS32, 0),     /* dcd  R_ARM_ABS32(x) */
+};
+
 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
    allowed.  */
 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
@@ -2625,7 +2632,8 @@ static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
   DEF_STUB(a8_veneer_b_cond) \
   DEF_STUB(a8_veneer_b) \
   DEF_STUB(a8_veneer_bl) \
-  DEF_STUB(a8_veneer_blx)
+  DEF_STUB(a8_veneer_blx) \
+  DEF_STUB(long_branch_thumb2_only) \
 
 #define DEF_STUB(x) arm_stub_##x,
 enum elf32_arm_stub_type
@@ -3781,6 +3789,7 @@ arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
   switch (stub_type)
     {
     case arm_stub_long_branch_thumb_only:
+    case arm_stub_long_branch_thumb2_only:
     case arm_stub_long_branch_v4t_thumb_arm:
     case arm_stub_short_branch_v4t_thumb_arm:
     case arm_stub_long_branch_v4t_thumb_arm_pic:
@@ -3945,7 +3954,8 @@ arm_type_of_stub (struct bfd_link_info *info,
 		    /* PIC stub.  */
 		    ? arm_stub_long_branch_thumb_only_pic
 		    /* non-PIC stub.  */
-		    : arm_stub_long_branch_thumb_only;
+		    : (thumb2 ? arm_stub_long_branch_thumb2_only
+			      : arm_stub_long_branch_thumb_only);
 		}
 	    }
 	  else
@@ -4331,6 +4341,7 @@ arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
     case arm_stub_long_branch_any_any:
     case arm_stub_long_branch_v4t_arm_thumb:
     case arm_stub_long_branch_thumb_only:
+    case arm_stub_long_branch_thumb2_only:
     case arm_stub_long_branch_v4t_thumb_thumb:
     case arm_stub_long_branch_v4t_thumb_arm:
     case arm_stub_short_branch_v4t_thumb_arm:
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index db25a8d46c985f89e02ce68c8897923c23101661..a5d4c8757cbe96367ecc4defe75397b4d9645c51 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -474,9 +474,12 @@ set armeabitests_nonacl {
     {"Thumb-Thumb farcall with BLX" "--no-fix-arm1176 -Ttext 0x1000 --section-start .foo=0x2001014" "" "-march=armv5t" {farcall-thumb-thumb.s}
      {{objdump -d farcall-thumb-thumb-blx.d}}
      "farcall-thumb-thumb-blx"}
-    {"Thumb-Thumb farcall M profile" "-Ttext 0x1000 --section-start .foo=0x2001014" "" "-march=armv7-m" {farcall-thumb-thumb.s}
+    {"Thumb-Thumb farcall M profile" "-Ttext 0x1000 --section-start .foo=0x2001014" "" "-march=armv6-m" {farcall-thumb-thumb.s}
      {{objdump -d farcall-thumb-thumb-m.d}}
      "farcall-thumb-thumb-m"}
+    {"Thumb2-Thumb2 farcall M profile" "-Ttext 0x1000 --section-start .foo=0x2001014" "" "-march=armv7-m" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb2-thumb2-m.d}}
+     "farcall-thumb2-thumb2-m"}
     {"Thumb-Thumb farcall v8-M Baseline" "-Ttext 0x1000 --section-start .foo=0x2001014" "" "-march=armv8-m.base" {farcall-thumb-thumb.s}
      {{objdump -d farcall-thumb-thumb-m.d}}
      "farcall-thumb-thumb-v8-m-base"}
diff --git a/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d b/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d
new file mode 100644
index 0000000000000000000000000000000000000000..58099417943433eafdd40e178780f1954a273aca
--- /dev/null
+++ b/ld/testsuite/ld-arm/farcall-thumb2-thumb2-m.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_veneer>
+    1004:	0000      	movs	r0, r0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	f85f f000 	ldr.w	pc, \[pc\]	; 100c <__bar_veneer\+0x4>
+    100c:	02001015 	.word	0x02001015
+
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d b/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d
index ee0709ad1a81069666a68c70f9ef63322adbc479..94242072ec6fcbb82d0b1acc002278db6264cbf0 100644
--- a/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d
+++ b/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d
@@ -15,10 +15,5 @@ Disassembly of section .text:
 	...
 
 001080.. <[^>]*>:
-  1080..:	b401      	push	{r0}
-  1080..:	4802      	ldr	r0, \[pc, #8\]	; \(108014 <__dest_veneer\+0xc>\)
-  1080..:	4684      	mov	ip, r0
-  1080..:	bc01      	pop	{r0}
-  1080..:	4760      	bx	ip
-  1080..:	bf00      	nop
+  1080..:	f85f f000 	ldr.w	pc, \[pc\]	; 10800c <__dest_veneer\+0x4>
   1080..:	00008003 	.word	0x00008003
diff --git a/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long.d b/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long.d
index 276a24e4e8b4f1017dac1d0aca3ac8aa0f448f92..d818cf579ed1776f0c7e8422a4203121461accf1 100644
--- a/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long.d
+++ b/ld/testsuite/ld-arm/jump-reloc-veneers-cond-long.d
@@ -15,10 +15,5 @@ Disassembly of section .text:
 	...
 
 000080.. <[^>]*>:
-    80..:	b401      	push	{r0}
-    80..:	4802      	ldr	r0, \[pc, #8\]	; \(80.. <__dest_veneer\+0xc>\)
-    80..:	4684      	mov	ip, r0
-    80..:	bc01      	pop	{r0}
-    80..:	4760      	bx	ip
-    80..:	bf00      	nop
+    80..:	f85f f000 	ldr.w	pc, \[pc\]	; 800c <__dest_veneer\+0x4>
     80..:	00108005 	.word	0x00108005

Follow-Ups:
- Re: [PATCH, binutils/ARM] Add Thumb-2 long branch veneers
  - From: Nick Clifton

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