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Re: [PATCH] Allow setting CpuVRex bit in .arch directive
- From: Jakub Jelinek <jakub at redhat dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: Binutils <binutils at sourceware dot org>, Uros Bizjak <ubizjak at gmail dot com>, Kirill Yukhin <kirill dot yukhin at gmail dot com>
- Date: Wed, 25 May 2016 19:58:43 +0200
- Subject: Re: [PATCH] Allow setting CpuVRex bit in .arch directive
- Authentication-results: sourceware.org; auth=none
- References: <20160521165405 dot GQ28550 at tucnak dot redhat dot com> <20160521170615 dot GE1875 at tucnak dot redhat dot com> <CAMe9rOrSYftrqeWjZQYmWmn7x_h9vHfz9Fcy3=UVUDNr+O2aCA at mail dot gmail dot com> <20160524174933 dot GN28550 at tucnak dot redhat dot com> <CAMe9rOqQp54VXOvQPVwZDzSGDH1=_YB6Ghnekh=SRJQcsCVY3w at mail dot gmail dot com> <20160524190716 dot GQ28550 at tucnak dot redhat dot com> <CAMe9rOo0YZqENDbkVF_KVbCi9KP11PYXWGhG-_JNyR+wUwmOmg at mail dot gmail dot com> <CAMe9rOr5O8FhwFw1vFk2rRfcf8tfztvrHGSXhSTaMAeL5LLUgg at mail dot gmail dot com>
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
On Wed, May 25, 2016 at 10:53:51AM -0700, H.J. Lu wrote:
> I am checking in this patch to enable VREX for AVX512 directives.
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -200,13 +200,13 @@ static initializer cpu_flag_init[] =
> { "CPU_AVX2_FLAGS",
> "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" },
> { "CPU_AVX512F_FLAGS",
> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" },
> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" },
> { "CPU_AVX512CD_FLAGS",
> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" },
> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" },
> { "CPU_AVX512ER_FLAGS",
> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" },
> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" },
> { "CPU_AVX512PF_FLAGS",
> - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" },
> + "CpuVREX|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" },
> { "CPU_ANY_AVX_FLAGS",
> "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" },
> { "CPU_L1OM_FLAGS",
What about CPU_AVX512{DQ,BW,VL,IFMA,VBMI}_FLAGS ?
Jakub