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Re: [PATCH] Allow setting CpuVRex bit in .arch directive


On Sat, May 21, 2016 at 06:54:05PM +0200, Jakub Jelinek wrote:
> I've tried today to check for the various AVX512* ISA issues in GCC
> using assembly .arch support.  Seems by default all flags (but l10m/k10m)
> are set, but if I want to allow all insns but say AVX512DQ ISA instructions
> or something similar, there is no way to do it - there is no way except
> for explicit no* flags to remove ISA bits from the default, so one has to
> set some CPU and then add all the ISA flags one wants.  Seems most of them
> can be added, except for one very important one - the CpuVRex bit.
> Here is a patch to add support for .arch .vrex to set that, another option
> might be to set CpuVRex whenever CpuAVX512F is set in 64-bit mode.
> Any preferences?

BTW, to my surprise, I haven't found any issues in the compiler this way,
even the known ones that I've just fixed.
	.arch	corei7
	.arch	.avx512f
	.arch	.avx512vl
	vinserti32x4	$0x0, %xmm0, %ymm15, %ymm15
	vinserti32x4	$0x1, %xmm0, %ymm15, %ymm15
	vinserti64x2	$0x0, %xmm0, %ymm15, %ymm15
	vinserti64x2	$0x1, %xmm0, %ymm15, %ymm15
	vinsertf32x4	$0x0, %xmm0, %ymm15, %ymm15
	vinsertf32x4	$0x1, %xmm0, %ymm15, %ymm15
	vinsertf64x2	$0x0, %xmm0, %ymm15, %ymm15
	vinsertf64x2	$0x1, %xmm0, %ymm15, %ymm15
assembles fine, even when it IMHO should not - the 64x2 instructions
are all AVX512VL & AVX512DQ.


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