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[PATCH] [SPARC] opcodes,gas: fix mnemonic of faligndatai
- From: jose dot marchesi at oracle dot com (Jose E. Marchesi)
- To: binutils at sourceware dot org
- Date: Wed, 04 May 2016 20:14:33 +0200
- Subject: [PATCH] [SPARC] opcodes,gas: fix mnemonic of faligndatai
- Authentication-results: sourceware.org; auth=none
Hi people.
The patch below fixes the assembly mnemonic of the VIS4 instruction
faligndatai. Its assembly syntax uses "faligndata" (same than
faligndatag) and not "faligndatai".
Tests modified accordingly. No regressions in sparcv9-*-* nor in
sparc64-*-* targets.
Ok to commit?
Thanks.
opcodes/ChangeLog:
2016-05-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
gas/ChangeLog:
2016-05-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
* testsuite/gas/sparc/sparc5vis4.d: Likewise.
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.d b/gas/testsuite/gas/sparc/sparc5vis4.d
index 61a2de8..bf5c90b 100644
--- a/gas/testsuite/gas/sparc/sparc5vis4.d
+++ b/gas/testsuite/gas/sparc/sparc5vis4.d
@@ -35,4 +35,4 @@ Disassembly of section .text:
64: 95 b1 aa c8 fpsubs8 %f6, %f8, %f10
68: 9d b2 aa ec fpsubus8 %f10, %f12, %f14
6c: a5 b3 aa 70 fpsubus16 %f14, %f16, %f18
- 70: bf b0 09 3f faligndatai %f0, %f62, %f4, %f62
+ 70: bf b0 09 3f faligndata %f0, %f62, %f4, %f62
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.s b/gas/testsuite/gas/sparc/sparc5vis4.s
index 4bd7942..0a0155f 100644
--- a/gas/testsuite/gas/sparc/sparc5vis4.s
+++ b/gas/testsuite/gas/sparc/sparc5vis4.s
@@ -28,4 +28,4 @@
fpsubs8 %f6, %f8, %f10
fpsubus8 %f10, %f12, %f14
fpsubus16 %f14, %f16, %f18
- faligndatai %f0, %f62, %f4, %f62
+ faligndata %f0, %f62, %f4, %f62
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index e681a2f..e40ce37 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1834,7 +1834,8 @@ SLCBCC("cbnefr", 15),
{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a },
{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a },
-{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a },
+{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */
+{ "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b }, /* faligndatai */
{ "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a },
{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a },
@@ -2058,13 +2059,11 @@ SLCBCC("cbnefr", 15),
{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait r */
{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait imm */
-/* SPARC5 and VIS4.0 instructions. */
+/* Other SPARC5 and VIS4.0 instructions. */
{ "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
{ "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
-{ "faligndatai", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b },
-
{ "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
{ "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
{ "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },