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PowerPC64 ELFv2 entry code


This tightens the condition under which ld optimizes PIC entry code
to non-PIC, not that I expect anyone sane would write code that might
cause the existing optimization to fail.

bfd/
	* elf64-ppc.c (ppc64_elf_relocate_section): Further restrict
	ELFv2 entry optimization.
gold/
	* powerpc.cc (relocate): Further restrict ELFv2 entry optimization.

diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index f9c37b5..369eae5 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -13915,6 +13915,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	  if (!bfd_link_pic (info)
 	      && !info->traditional_format
 	      && !htab->opd_abi
+	      && rel->r_addend == 0
 	      && h != NULL && &h->elf == htab->elf.hgot
 	      && rel + 1 < relend
 	      && rel[1].r_info == ELF64_R_INFO (r_symndx, R_PPC64_REL16_LO)
diff --git a/gold/powerpc.cc b/gold/powerpc.cc
index e26a198..23288de 100644
--- a/gold/powerpc.cc
+++ b/gold/powerpc.cc
@@ -7727,6 +7727,7 @@ Target_powerpc<size, big_endian>::Relocate::relocate(
 	      && preloc != NULL
 	      && target->abiversion() >= 2
 	      && !parameters->options().output_is_position_independent()
+	      && rela.get_r_addend() == 4
 	      && gsym != NULL
 	      && strcmp(gsym->name(), ".TOC.") == 0)
 	    {

-- 
Alan Modra
Australia Development Lab, IBM


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