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[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.

The general form for these instructions is
  <OP> <Hd>, <Hs>, <Hm>

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
	instructions.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
	fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
	facgt to the scalar three same group.


>From 1954899becd32346d24300d39a1cbfdc6429e1a0 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 8 Sep 2015 19:13:04 +0100
Subject: [PATCH 03/14] [AArch64] Add FP16 Scalar three-same instructions (II).

---
 gas/testsuite/gas/aarch64/advsimd-fp16.d |   36 +
 gas/testsuite/gas/aarch64/advsimd-fp16.s |   19 +
 opcodes/aarch64-asm-2.c                  |  604 ++++++------
 opcodes/aarch64-dis-2.c                  | 1549 ++++++++++++++++--------------
 opcodes/aarch64-opc-2.c                  |  100 +-
 opcodes/aarch64-tbl.h                    |   18 +
 6 files changed, 1249 insertions(+), 1077 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 5b5e694..5814bec 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -167,3 +167,39 @@ Disassembly of section \.text:
  [0-9a-f]+:	0ec33c41 	frsqrts	v1.4h, v2.4h, v3.4h
  [0-9a-f]+:	4ec03c00 	frsqrts	v0.8h, v0.8h, v0.8h
  [0-9a-f]+:	4ec33c41 	frsqrts	v1.8h, v2.8h, v3.8h
+ [0-9a-f]+:	7ee2d420 	fabd	d0, d1, d2
+ [0-9a-f]+:	7ea2d420 	fabd	s0, s1, s2
+ [0-9a-f]+:	7ec21420 	fabd	h0, h1, h2
+ [0-9a-f]+:	7ec01400 	fabd	h0, h0, h0
+ [0-9a-f]+:	5e62dc20 	fmulx	d0, d1, d2
+ [0-9a-f]+:	5e22dc20 	fmulx	s0, s1, s2
+ [0-9a-f]+:	5e421c20 	fmulx	h0, h1, h2
+ [0-9a-f]+:	5e401c00 	fmulx	h0, h0, h0
+ [0-9a-f]+:	5e62e420 	fcmeq	d0, d1, d2
+ [0-9a-f]+:	5e22e420 	fcmeq	s0, s1, s2
+ [0-9a-f]+:	5e422420 	fcmeq	h0, h1, h2
+ [0-9a-f]+:	5e402400 	fcmeq	h0, h0, h0
+ [0-9a-f]+:	7ee2e420 	fcmgt	d0, d1, d2
+ [0-9a-f]+:	7ea2e420 	fcmgt	s0, s1, s2
+ [0-9a-f]+:	7ec22420 	fcmgt	h0, h1, h2
+ [0-9a-f]+:	7ec02400 	fcmgt	h0, h0, h0
+ [0-9a-f]+:	7e62e420 	fcmge	d0, d1, d2
+ [0-9a-f]+:	7e22e420 	fcmge	s0, s1, s2
+ [0-9a-f]+:	7e422420 	fcmge	h0, h1, h2
+ [0-9a-f]+:	7e402400 	fcmge	h0, h0, h0
+ [0-9a-f]+:	7e62ec20 	facge	d0, d1, d2
+ [0-9a-f]+:	7e22ec20 	facge	s0, s1, s2
+ [0-9a-f]+:	7e422c20 	facge	h0, h1, h2
+ [0-9a-f]+:	7e402c00 	facge	h0, h0, h0
+ [0-9a-f]+:	7ee2ec20 	facgt	d0, d1, d2
+ [0-9a-f]+:	7ea2ec20 	facgt	s0, s1, s2
+ [0-9a-f]+:	7ec22c20 	facgt	h0, h1, h2
+ [0-9a-f]+:	7ec02c00 	facgt	h0, h0, h0
+ [0-9a-f]+:	5e62fc20 	frecps	d0, d1, d2
+ [0-9a-f]+:	5e22fc20 	frecps	s0, s1, s2
+ [0-9a-f]+:	5e423c20 	frecps	h0, h1, h2
+ [0-9a-f]+:	5e403c00 	frecps	h0, h0, h0
+ [0-9a-f]+:	5ee2fc20 	frsqrts	d0, d1, d2
+ [0-9a-f]+:	5ea2fc20 	frsqrts	s0, s1, s2
+ [0-9a-f]+:	5ec23c20 	frsqrts	h0, h1, h2
+ [0-9a-f]+:	5ec03c00 	frsqrts	h0, h0, h0
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 3649ca2..99f27f2 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -38,3 +38,22 @@
 	three_same frecps
 	three_same fdiv
 	three_same frsqrts
+
+	/* Scalar three-same.  */
+
+	.macro sthree_same, op
+	\op	d0, d1, d2
+	\op	s0, s1, s2
+	\op	h0, h1, h2
+	\op	h0, h0, h0
+	.endm
+
+	sthree_same fabd
+	sthree_same fmulx
+	sthree_same fcmeq
+	sthree_same fcmgt
+	sthree_same fcmge
+	sthree_same facge
+	sthree_same facgt
+	sthree_same frecps
+	sthree_same frsqrts
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f2c7c7f..ba855ed 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1849,9 +1849,17 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
   {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
   {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
   {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
   {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
@@ -1864,10 +1872,20 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
   {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
   {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"facge", 0x7e402c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
+  {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
+   OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
   {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
   {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
   {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
-- 
2.1.4
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