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[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Wed, 9 Dec 2015 09:53:24 +0000
- Subject: [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
- Authentication-results: sourceware.org; auth=none
- References: <5667F9C3 dot 5070703 at foss dot arm dot com>
Hello,
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
gas/testsuite/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
include/opcode/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
opcodes/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
>From d4fcf40507d181b3f62504b30ef5e7325cdbbba8 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 12 Nov 2015 11:06:39 +0000
Subject: [PATCH 2/2] [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
Change-Id: I735e5a8eb0090d42f636ab97ac3f59f53e5b70f2
---
gas/config/tc-aarch64.c | 4 ++++
gas/testsuite/gas/aarch64/sysreg-2.d | 4 ++++
gas/testsuite/gas/aarch64/sysreg-2.s | 7 +++++++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-opc.c | 16 ++++++++++++++++
5 files changed, 34 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d306710..bb2f228 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3687,6 +3687,10 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
if (!o)
return NULL;
+ if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
+ as_bad (_("selected processor does not support system register "
+ "name '%s'"), buf);
+
*str = q;
return o;
}
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index f0fe533..5c9838f 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -9,3 +9,7 @@ Disassembly of section .text:
0000000000000000 <.*>:
[0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1
[0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
+ [0-9a-f]+: d50b7a20 dc cvac, x0
+ [0-9a-f]+: d50b7b21 dc cvau, x1
+ [0-9a-f]+: d50b7c22 dc cvap, x2
+
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index f519682..d45aaa0 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -13,3 +13,10 @@
rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
+
+ /* DC CVAP. */
+
+ dc cvac, x0
+ dc cvau, x1
+ dc cvap, x2
+
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 68a949f..069eee1 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -671,6 +671,9 @@ typedef struct
} aarch64_sys_ins_reg;
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
+ const aarch64_sys_ins_reg *);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 9fa7467..59303a0 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3213,6 +3213,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
+ { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
@@ -3278,6 +3279,21 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
return (sys_ins_reg->flags & F_HASXT) != 0;
}
+extern bfd_boolean
+aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_ins_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* DC CVAP. Values are from aarch64_sys_regs_dc. */
+ if (reg->value == CPENS (3, C7, C12, 1)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
+ return TRUE;
+}
+
#undef C0
#undef C1
#undef C2
--
2.1.4