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[AArch64][PATCH 2/2] Add ARMv8.2 instruction alias REV64.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Tue, 24 Nov 2015 11:19:25 +0000
- Subject: [AArch64][PATCH 2/2] Add ARMv8.2 instruction alias REV64.
- Authentication-results: sourceware.org; auth=none
- References: <56544752 dot 5050609 at foss dot arm dot com>
Hello,
This patch adds the alias REV64 <Rd>, <Rs> as an alias for REV <Rd>,
<Rs>. However, REV is still the preferred form for the instruction.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/alias-2.d: Add tests for REV.
* gas/aarch64/alias-2.s: Likewise.
opcodes/
2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
"rev64".
>From 476a132b565a15ac511e0a708afa7626e478788f Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 16 Sep 2015 10:59:58 +0100
Subject: [PATCH 2/2] [AArch64] Add ARMv8.2 instruction alias REV64.
---
gas/testsuite/gas/aarch64/alias-2.d | 13 +
gas/testsuite/gas/aarch64/alias-2.s | 12 +
opcodes/aarch64-asm-2.c | 514 +++++++++----------
opcodes/aarch64-dis-2.c | 990 ++++++++++++++++++------------------
opcodes/aarch64-opc-2.c | 36 +-
opcodes/aarch64-tbl.h | 5 +-
6 files changed, 802 insertions(+), 768 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d
index 92ed58f..a555547 100644
--- a/gas/testsuite/gas/aarch64/alias-2.d
+++ b/gas/testsuite/gas/aarch64/alias-2.d
@@ -96,3 +96,16 @@ Disassembly of section \.text:
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
+ [0-9a-f]+: dac00fe0 rev x0, xzr
+ [0-9a-f]+: dac00c20 rev x0, x1
+ [0-9a-f]+: dac00c3f rev xzr, x1
+ [0-9a-f]+: dac00fff rev xzr, xzr
+ [0-9a-f]+: dac007e0 rev16 x0, xzr
+ [0-9a-f]+: dac00420 rev16 x0, x1
+ [0-9a-f]+: dac0043f rev16 xzr, x1
+ [0-9a-f]+: dac007ff rev16 xzr, xzr
+ [0-9a-f]+: dac00fe0 rev x0, xzr
+ [0-9a-f]+: dac00c20 rev x0, x1
+ [0-9a-f]+: dac00c3f rev xzr, x1
+ [0-9a-f]+: dac00fff rev xzr, xzr
+
diff --git a/gas/testsuite/gas/aarch64/alias-2.s b/gas/testsuite/gas/aarch64/alias-2.s
index d952c97..86b561d 100644
--- a/gas/testsuite/gas/aarch64/alias-2.s
+++ b/gas/testsuite/gas/aarch64/alias-2.s
@@ -15,6 +15,14 @@
bfc xzr, #\imm, #\width
.endm
+ /* <rev> [Xd|xzr], [Xr|xzr] */
+ .macro rev_inst op
+ \op x0, xzr
+ \op x0, x1
+ \op xzr, x1
+ \op xzr, xzr
+ .endm
+
.text
.irp op, bfm, bfi
.irp imm, 1, 16, 31
@@ -29,3 +37,7 @@
bfc_inst \imm, \width
.endr
.endr
+
+ .irp op, rev, rev16, rev64
+ rev_inst \op
+ .endr
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 83f8a8e..51a8860 100644
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index f46f737..57630d5 100644
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 485a3f5..ca3f35b 100644
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ddfc577..6371193 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1848,7 +1848,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
- {"rev", 0xdac00c00, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
+ {"rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, CORE,
+ OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1},
+ {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2,
+ OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS},
{"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
{"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
--
2.1.4