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[Aarch64] Support an ARMv8.2 system register.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 24 Nov 2015 10:47:24 +0000
- Subject: [Aarch64] Support an ARMv8.2 system register.
- Authentication-results: sourceware.org; auth=none
Hello,
ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds
support for the register to binutils, making it available when
-march=armv8.2-a is selected.
Tested aarch64-none-linux-gnu with cross-compiled check-binutils and
check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: New.
* gas/aarch64/sysreg-2.s: New.
opcodes/
2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
(aarch64_sys_reg_supported_p): Add ARMv8.2 system register
feature test.
>From 5eae0863ad0ef77f326ed1024a958721b3bdb021 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 16 Sep 2015 10:45:56 +0100
Subject: [PATCH] [Aarch64] Support an ARMv8.2 system register.
Change-Id: If4c9d63489242566a74e84c468751fdfc3598346
---
gas/testsuite/gas/aarch64/sysreg-2.d | 11 +++++++++++
gas/testsuite/gas/aarch64/sysreg-2.s | 15 +++++++++++++++
opcodes/aarch64-opc.c | 5 +++++
3 files changed, 31 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sysreg-2.d
create mode 100644 gas/testsuite/gas/aarch64/sysreg-2.s
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
new file mode 100644
index 0000000..f0fe533
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -0,0 +1,11 @@
+#objdump: -dr
+#as: -march=armv8.2-a
+
+.*: file .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.*>:
+ [0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1
+ [0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
new file mode 100644
index 0000000..f519682
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -0,0 +1,15 @@
+/* sysreg-2.s Test file for ARMv8.2 system registers. */
+
+ .macro rw_sys_reg sys_reg xreg r w
+ .ifc \w, 1
+ msr \sys_reg, \xreg
+ .endif
+ .ifc \r, 1
+ mrs \xreg, \sys_reg
+ .endif
+ .endm
+
+ .text
+
+ rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
+ rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a19f36f..9323217 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2801,6 +2801,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), 0 }, /* RO */
{ "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), 0 }, /* RO */
{ "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), 0 }, /* RO */
+ { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */
{ "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), 0 }, /* RO */
{ "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), 0 }, /* RO */
{ "clidr_el1", CPENC(3,1,C0,C0,1), 0 }, /* RO */
@@ -3135,6 +3136,10 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
|| reg->value == CPENC (3, 5, C14, C3, 1)
|| reg->value == CPENC (3, 5, C14, C3, 2))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+
+ /* ARMv8.2 features. */
+ if (reg->value == CPENC (3, 0, C0, C7, 2)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
return TRUE;
--
2.1.4