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Re: [PATCH] PR binutils/18257: Properly decode x86/Intel mask instructions.
- From: Alexander Fomin <afomin dot mailbox at gmail dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: binutils at sourceware dot org
- Date: Wed, 19 Aug 2015 19:22:40 +0300
- Subject: Re: [PATCH] PR binutils/18257: Properly decode x86/Intel mask instructions.
- Authentication-results: sourceware.org; auth=none
- References: <20150819161316 dot GA15909 at msticlxl57 dot ims dot intel dot com> <CAMe9rOqQg-TUF-UBos3zDGRDv=yVaEgxcpU6=RqCCOXRMyCF3A at mail dot gmail dot com>
When appending new testcases, we need to insert a nop padding after
existing testcases.
Is it OK?
Alexander
On Wed, Aug 19, 2015 at 09:16:55AM -0700, H.J. Lu wrote:
> On Wed, Aug 19, 2015 at 9:13 AM, Alexander Fomin
> <afomin.mailbox@gmail.com> wrote:
> > For most of mask instructions, ModRM[7:6] must be 11b.
> > For some of them, ModRM[7:6] must be not 11b.
> > The patch makes disassembler satisfy these constraints.
> >
> > Any objections, comments?
> >
> > Alexander
> > ---
> > opcodes/
> >
> > PR binutils/18257
> > * i386-dis.c Use MOD_TABLE for most of mask instructions.
> > (MOD enum) Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1,
> > MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1,
> > MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1,
> > MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1,
> > MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1,
> > MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1,
> > MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1,
> > MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1,
> > MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1,
> > MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1,
> > MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1,
> > MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1,
> > MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1,
> > MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1,
> > MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1,
> > MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0,
> > MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0,
> > MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0,
> > MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0,
> > MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
> > MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0,
> > MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0,
> > MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0,
> > MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0,
> > MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0,
> > MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
> > MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
> > MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
> > MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
> > MOD_VEX_W_1_0F3A33_P_2_LEN_0.
> > (vex_w_table) Replace terminals with MOD_TABLE entries for
> > most of mask instructions.
> >
> > gas/testsuite
> >
> > PR binutils/18257
> > * gas/i386/disassem.s Add mask instructions with invalid ModR/M byte.
> > * gas/i386/x86-64-disassem.s Likewise.
> > * gas/i386/disassem.d Add mask instructions with invalid ModR/M byte disassembly.
> >
> > ---
> > gas/testsuite/gas/i386/disassem.d | 336 +++++++++++++++++++++-
> > gas/testsuite/gas/i386/disassem.s | 165 +++++++++++
> > gas/testsuite/gas/i386/x86-64-disassem.d | 336 +++++++++++++++++++++-
> > gas/testsuite/gas/i386/x86-64-disassem.s | 165 +++++++++++
> > opcodes/i386-dis.c | 472 +++++++++++++++++++++++++++----
> > 5 files changed, 1409 insertions(+), 65 deletions(-)
> >
>
> Please append the new testcases to i386/disassem.s, not
> insert them in the beginning. OK with that change.
>
> Thanks.
>
> --
> H.J.