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RE: [PATH] AMD MWAITX enablement
- From: "Pawar, Amit" <Amit dot Pawar at amd dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Wed, 10 Jun 2015 09:37:04 +0000
- Subject: RE: [PATH] AMD MWAITX enablement
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- References: <0428E25D138CAA4D819A6FED9429E51AF4A29C at SCYBEXDAG02 dot amd dot com> <556D83DE02000078000800CE at mail dot emea dot novell dot com> <0428E25D138CAA4D819A6FED9429E51AF4A96C at SCYBEXDAG02 dot amd dot com> <55755AD50200007800081CE1 at mail dot emea dot novell dot com>
64 bit version is provided for backward compatibility and upper 32 bits of RAX,RCX and RBX registers are not consumed by the
MWAITX instruction. Only lower 32 bits of RAX,RCX,RBX (I,e EAX,ECX and EBX) are consumed. Documentation is in progress
and on completion it will be released to the public.
-----Original Message-----
From: Jan Beulich [mailto:JBeulich@suse.com]
Sent: Monday, June 08, 2015 12:35 PM
To: Pawar, Amit
Cc: binutils@sourceware.org
Subject: RE: [PATH] AMD MWAITX enablement
>>> On 08.06.15 at 08:15, <Amit.Pawar@amd.com> wrote:
> Third operand has been added to MWAITX instruction.
Thanks. And just to double check - in 64-bit mode it is RBX that matters, not EBX (i.e. the upper 32 bits are not being ignored)?
(I suppose you realize that it's kind of difficult to review such a change without there being public documentation for these new
instructions.)
Jan