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Add Octeon3 support
- From: "Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at caviumnetworks dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "Pinski, Andrew" <Andrew dot Pinski at caviumnetworks dot com>
- Date: Tue, 7 Oct 2014 03:49:33 +0000
- Subject: Add Octeon3 support
- Authentication-results: sourceware.org; auth=none
- References: <1412588878522 dot 14605 at caviumnetworks dot com>
âHi,
This patch adds Cavium octeon3 support in mips.
âPlease review the patch and let us know if there should be any
modifications.
Submitting the patch on behalf of Andrew Pinski.
Thanks,
2014-10-06 ÂAndrew Pinski Â<apinski@cavium.com>
bfd/ChangeLog
ÂÂÂÂÂÂÂÂ* archures.c: Add octeon3 for mips target.
ÂÂÂÂÂÂÂÂ* bfd-in2.h: Regenerate.
ÂÂÂÂÂÂÂÂ* bfd/cpu-mips.c: Define I_mipsocteon3.
ÂÂÂÂÂÂÂÂ(arch_info_struct): Add octeon3 support.
   ÂÂ(_bfd_elf_mips_mach): Add support for octeon3.
   ÂÂ(mips_set_isa_flags): Add support for octeon3.
   ÂÂ(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
   ÂÂextension of bfd_mach_mips_octeon2.
gas/ChangeLog
   Â* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
   Â(CPU_IS_OCTEON3): New define.
   Â(mips_cpu_info_table): Octeon3 enables virt ase.
include/ChangeLog
   Â* elf/mips.h (INSN_OCTEON3, CPU_OCTEON3): Define.
opcodes/ChangeLog
   Â* mips-dis.c (mips_arch_choices): Add octeon3.
   Â* mips-opc.c (IOCT): Include INSN_OCTEON3.
   Â(IOCT2): Likewise.
   Â(IOCT3): New define.
   Â(IVIRT): New define.
   Â(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
   Âtlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
   ÂIVIRT instructions.
   ÂExtend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
   Âoperand for IOCT3.
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index dd59324..93594f6 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,14 @@
+2014-10-06 Andrew Pinski <apinski@cavium.com>
+
+ * archures.c: Add octeon3 for mips target.
+ * bfd-in2.h: Regenerate.
+ * bfd/cpu-mips.c: Define I_mipsocteon3.
+ (arch_info_struct): Add octeon3 support.
+ (_bfd_elf_mips_mach): Add support for octeon3.
+ (mips_set_isa_flags): Add support for octeon3.
+ (mips_mach_extensions): Make bfd_mach_mips_octeon3 an
+ extension of bfd_mach_mips_octeon2.
+
2014-10-04 Alan Modra <amodra@gmail.com>
PR 17447
diff --git a/bfd/archures.c b/bfd/archures.c
index c9fd6c8..5e069b2 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -179,6 +179,7 @@ DESCRIPTION
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_octeonp 6601
.#define bfd_mach_mips_octeon2 6502
+.#define bfd_mach_mips_octeon3 6503
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index a40a14a..724336d 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1966,6 +1966,7 @@ enum bfd_architecture
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_octeon2 6502
+#define bfd_mach_mips_octeon3 6503
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index b617aaa..a376944 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -102,6 +102,7 @@ enum
I_mipsocteon,
I_mipsocteonp,
I_mipsocteon2,
+ I_mipsocteon3,
I_xlr,
I_micromips
};
@@ -152,6 +153,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
+ N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", FALSE, NN(I_mipsocteon3)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
};
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 7343835..3218d2e 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -6588,6 +6588,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_LS3A:
return bfd_mach_mips_loongson_3a;
+ case E_MIPS_MACH_OCTEON3:
+ return bfd_mach_mips_octeon3;
+
case E_MIPS_MACH_OCTEON2:
return bfd_mach_mips_octeon2;
@@ -11859,6 +11862,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
+ case bfd_mach_mips_octeon3:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON3;
+ break;
+
case bfd_mach_mips_xlr:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
break;
@@ -14728,6 +14735,7 @@ struct mips_mach_extension
static const struct mips_mach_extension mips_mach_extensions[] =
{
/* MIPS64r2 extensions. */
+ { bfd_mach_mips_octeon3, bfd_mach_mips_octeon2 },
{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ff149d3..ba4595e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2014-10-06 Andrew Pinski <apinski@cavium.com>
+
+ * config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
+ (CPU_IS_OCTEON3): New define.
+ (mips_cpu_info_table): Octeon3 enables virt ase.
+
2014-09-29 Terry Guo <terry.guo@arm.com>
* as.c (create_obj_attrs_section): Move it and call it from ...
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 8d4a80b..f6feb80 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -510,7 +510,11 @@ static int mips_32bitmode = 0;
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
/* True if CPU is in the Octeon family */
-#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
+ || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
+
+/* True if CPU is Octeon3 or higher */
+#define CPU_IS_OCTEON3(CPU) ((CPU) == CPU_OCTEON3)
/* True if CPU has seq/sne and seqi/snei instructions. */
#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
@@ -18659,6 +18663,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
{ "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
{ "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
+ { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
/* RMI Xlr */
{ "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
diff --git a/include/ChangeLog b/include/ChangeLog
index f13af30..ff21e15 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2014-10-06 Andrew Pinski <apinski@cavium.com>
+
+ * elf/mips.h (INSN_OCTEON3, CPU_OCTEON3): Define.
+
2014-08-12 Alan Modra <amodra@gmail.com>
* bfdlink.h (struct bfd_link_callbacks <notice>): Remove "string"
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index ef26167..ab40c60 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1196,6 +1196,7 @@ static const unsigned int mips_isa_table[] = {
#define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
+#define INSN_OCTEON3 0x00000040
/* MIPS R5900 instruction */
#define INSN_5900 0x00004000
@@ -1323,6 +1324,7 @@ static const unsigned int mips_isa_table[] = {
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
+#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Return true if the given CPU is included in INSN_* mask MASK. */
@@ -1388,6 +1390,9 @@ cpu_is_member (int cpu, unsigned int mask)
case CPU_OCTEON2:
return (mask & INSN_OCTEON2) != 0;
+ case CPU_OCTEON3:
+ return (mask & INSN_OCTEON3) != 0;
+
case CPU_XLR:
return (mask & INSN_XLR) != 0;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e5bcb13..ca769f8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,16 @@
+2014-10-06 Andrew Pinski <apinski@cavium.com>
+
+ * mips-dis.c (mips_arch_choices): Add octeon3.
+ * mips-opc.c (IOCT): Include INSN_OCTEON3.
+ (IOCT2): Likewise.
+ (IOCT3): New define.
+ (IVIRT): New define.
+ (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+ tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
+ IVIRT instructions.
+ Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
+ operand for IOCT3.
+
2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOD_0F20): Removed.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1eb1d45..e710d04 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -649,6 +649,11 @@ const struct mips_arch_choice mips_arch_choices[] =
ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+ { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
+ ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
+ mips_cp0_names_numeric,
+ NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR, 0,
mips_cp0_names_xlr,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0e9f716..cdc5472 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -316,9 +316,10 @@ decode_mips_operand (const char *p)
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
-#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
-#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
-#define IOCT2 INSN_OCTEON2
+#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT3 INSN_OCTEON3
#define XLR INSN_XLR
#define IVIRT ASE_VIRT
#define IVIRT64 ASE_VIRT64
@@ -1496,11 +1497,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
+{"mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_2|RD_3, 0, IOCT3, 0, 0 },
{"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 },
{"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },
{"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 },