This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH 9/9] gas, opcodes: SPARC M7 support: sparc5/vis4.0 instructions.
- From: "Jose E. Marchesi" <jose dot marchesi at oracle dot com>
- To: binutils at sourceware dot org
- Cc: davem at davemloft dot net
- Date: Thu, 2 Oct 2014 18:19:42 +0200
- Subject: [PATCH 9/9] gas, opcodes: SPARC M7 support: sparc5/vis4.0 instructions.
- Authentication-results: sourceware.org; auth=none
- References: <1412266782-14873-1-git-send-email-jose dot marchesi at oracle dot com>
This patch adds support to GNU binutils for the following instructions
as documented in the OSA2015 specification and implemented in the M7
cpu:
- SPARC5 instructions:
subxc, subxcc
- SPARC5 and VIS4.0 instructions:
faligndatai, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32,
fpmax8, fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8,
fpmin16, fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8,
fpsubus8, fpsubus16
Tested on sparc64-unknown-linux-gnu.
gas/ChangeLog:
2014-10-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Handle } arguments as fdrd
floating point registers (double) that are the same than frs1.
gas/testsuite/ChangeLog:
2014-10-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/sparc.exp (sparc_elf_setup): Run the sparc5vis4 test.
* gas/sparc/sparc5vis4.d: New file.
* gas/sparc/sparc5vis4.s: Likewise.
include/opcode/ChangeLog:
2014-10-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc.h (sparc_opcode): Document the new operand kind }, which
represents frsd floating point registers (double precision) which
must be the same than frs1 in its containing instruction.
opcodes/ChangeLog:
2014-10-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (print_insn_sparc): Handle new operand type '}'.
* sparc-opc.c (sparc-opcodes): Add sparc5/vis4.0 instructions:
subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
fpsubus16, and faligndatai.
---
gas/ChangeLog | 5 +++++
gas/config/tc-sparc.c | 9 ++++++++
gas/testsuite/ChangeLog | 7 +++++++
gas/testsuite/gas/sparc/sparc.exp | 1 +
gas/testsuite/gas/sparc/sparc5vis4.d | 38 ++++++++++++++++++++++++++++++++++
gas/testsuite/gas/sparc/sparc5vis4.s | 31 +++++++++++++++++++++++++++
include/opcode/ChangeLog | 6 ++++++
include/opcode/sparc.h | 1 +
opcodes/ChangeLog | 10 +++++++++
opcodes/sparc-dis.c | 1 +
opcodes/sparc-opc.c | 34 ++++++++++++++++++++++++++++++
11 files changed, 143 insertions(+)
create mode 100644 gas/testsuite/gas/sparc/sparc5vis4.d
create mode 100644 gas/testsuite/gas/sparc/sparc5vis4.s
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index c808b45..f5c3de4 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -2360,6 +2360,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'g':
case 'H':
case 'J':
+ case '}':
{
char format;
@@ -2422,6 +2423,13 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
break;
} /* if not an 'f' register. */
+ if (*args == '}' && mask != RS2 (opcode))
+ {
+ error_message
+ = _(": Instruction requires frs2 and frsd must be the same register");
+ goto error;
+ }
+
switch (*args)
{
case 'v':
@@ -2444,6 +2452,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'g':
case 'H':
case 'J':
+ case '}':
opcode |= RD (mask);
continue;
} /* Pack it in. */
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index c8980cf..8178e0c 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -92,6 +92,7 @@ if [istarget sparc*-*-*] {
run_dump_test "flush"
run_dump_test "mwait"
run_dump_test "mcdper"
+ run_dump_test "sparc5vis4"
run_list_test "pr4587" ""
}
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.d b/gas/testsuite/gas/sparc/sparc5vis4.d
new file mode 100644
index 0000000..161236f
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.d
@@ -0,0 +1,38 @@
+#as: -Av9x
+#objdump: -dr
+#name: sparc SPARC5 and VIS4.0
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 87 b0 48 22 subxc %g1, %g2, %g3
+ 4: 87 b0 48 62 subxccc %g1, %g2, %g3
+ 8: 91 b0 a4 84 fpadd8 %f2, %f4, %f8
+ c: 99 b2 24 ca fpadds8 %f8, %f10, %f12
+ 10: a1 b3 24 ee fpaddus8 %f12, %f14, %f16
+ 14: a9 b4 24 72 fpaddus16 %f16, %f18, %f20
+ 18: 83 b0 86 84 fpcmple8 %f2, %f4, %g1
+ 1c: 85 b1 07 86 fpcmpgt8 %f4, %f6, %g2
+ 20: 87 b1 a5 c8 fpcmpule16 %f6, %f8, %g3
+ 24: 89 b2 25 6a fpcmpugt16 %f8, %f10, %g4
+ 28: 8b b2 a5 ec fpcmpule32 %f10, %f12, %g5
+ 2c: 8d b3 25 8e fpcmpugt32 %f12, %f14, %g6
+ 30: a5 b3 a3 b0 fpmax8 %f14, %f16, %f18
+ 34: ad b4 a3 d4 fpmax16 %f18, %f20, %f22
+ 38: b5 b5 a3 f8 fpmax32 %f22, %f24, %f26
+ 3c: bd b6 ab bc fpmaxu8 %f26, %f28, %f30
+ 40: 87 b7 ab c1 fpmaxu16 %f30, %f32, %f34
+ 44: 8f b0 eb e5 fpmaxu32 %f34, %f36, %f38
+ 48: 97 b1 e3 49 fpmin8 %f38, %f40, %f42
+ 4c: 9f b2 e3 6d fpmin16 %f42, %f44, %f46
+ 50: a7 b3 e3 91 fpmin32 %f46, %f48, %f50
+ 54: af b4 eb 55 fpminu8 %f50, %f52, %f54
+ 58: b7 b5 eb 79 fpminu16 %f54, %f56, %f58
+ 5c: bf b6 eb 9d fpminu32 %f58, %f60, %f62
+ 60: 8d b0 aa 84 fpsub8 %f2, %f4, %f6
+ 64: 95 b1 aa c8 fpsubs8 %f6, %f8, %f10
+ 68: 9d b2 aa ec fpsubus8 %f10, %f12, %f14
+ 6c: a5 b3 aa 70 fpsubus16 %f14, %f16, %f18
+ 70: bf b0 09 3f faligndatai %f0, %f62, %f4, %f62
diff --git a/gas/testsuite/gas/sparc/sparc5vis4.s b/gas/testsuite/gas/sparc/sparc5vis4.s
new file mode 100644
index 0000000..4bd7942
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc5vis4.s
@@ -0,0 +1,31 @@
+# Test SPARC5/VIS4 instructions
+ .text
+ subxc %g1, %g2, %g3
+ subxccc %g1, %g2, %g3
+ fpadd8 %f2, %f4, %f8
+ fpadds8 %f8, %f10, %f12
+ fpaddus8 %f12, %f14, %f16
+ fpaddus16 %f16, %f18, %f20
+ fpcmple8 %f2, %f4, %g1
+ fpcmpgt8 %f4, %f6, %g2
+ fpcmpule16 %f6, %f8, %g3
+ fpcmpugt16 %f8, %f10, %g4
+ fpcmpule32 %f10, %f12, %g5
+ fpcmpugt32 %f12, %f14, %g6
+ fpmax8 %f14, %f16, %f18
+ fpmax16 %f18, %f20, %f22
+ fpmax32 %f22, %f24, %f26
+ fpmaxu8 %f26, %f28, %f30
+ fpmaxu16 %f30, %f32, %f34
+ fpmaxu32 %f34, %f36, %f38
+ fpmin8 %f38, %f40, %f42
+ fpmin16 %f42, %f44, %f46
+ fpmin32 %f46, %f48, %f50
+ fpminu8 %f50, %f52, %f54
+ fpminu16 %f54, %f56, %f58
+ fpminu32 %f58, %f60, %f62
+ fpsub8 %f2, %f4, %f6
+ fpsubs8 %f6, %f8, %f10
+ fpsubus8 %f10, %f12, %f14
+ fpsubus16 %f14, %f16, %f18
+ faligndatai %f0, %f62, %f4, %f62
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 6849c23..13d1fe6 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -185,6 +185,7 @@ typedef struct sparc_opcode
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
+ } frsd floating point register (double/even) that is == frs2
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index e3389a6..9f0b96e 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -656,6 +656,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case 'H': /* Double/even. */
case 'J': /* Quad/multiple of 4. */
+ case '}': /* Double/even. */
fregx (X_RD (insn));
break;
#undef freg
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 75a8f75..1150b2f 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -2058,6 +2058,40 @@ SLCBCC("cbnefr", 15),
{ "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait r */
{ "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9b }, /* mwait imm */
+/* SPARC5 and VIS4.0 instructions. */
+
+{ "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9b },
+
+{ "faligndatai", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9b },
+
+{ "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+{ "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9b },
+
/* More v9 specific insns, these need to come last so they do not clash
with v9a instructions such as "edge8" which looks like impdep1. */
--
1.7.10.4