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[PATCH 14/14] or1k cgen changes
- From: Christian Svensson <blue at cmd dot nu>
- To: binutils at sourceware dot org
- Cc: openrisc at lists dot openrisc dot net,openrisc at lists dot opencores dot org
- Date: Sat, 8 Mar 2014 16:06:18 +0000
- Subject: [PATCH 14/14] or1k cgen changes
- Authentication-results: sourceware.org; auth=none
This patch adds CGEN files for or1k targets.
---
cpu/or1k.cpu | 131 +++++++
cpu/or1k.opc | 423 ++++++++++++++++++++
cpu/or1kcommon.cpu | 360 ++++++++++++++++++
cpu/or1korbis.cpu | 1080 ++++++++++++++++++++++++++++++++++++++++++++++++++++
cpu/or1korfpx.cpu | 222 +++++++++++
5 files changed, 2216 insertions(+)
create mode 100644 cpu/or1k.cpu
create mode 100644 cpu/or1k.opc
create mode 100644 cpu/or1kcommon.cpu
create mode 100644 cpu/or1korbis.cpu
create mode 100644 cpu/or1korfpx.cpu
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
new file mode 100644
index 0000000..5d337da
--- /dev/null
+++ b/cpu/or1k.cpu
@@ -0,0 +1,131 @@
+; OpenRISC 1000 architecture. -*- Scheme -*-
+; Copyright 2000-2001, 2011-2014 Free Software Foundation, Inc.
+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
+; Modified by Julius Baxter, juliusbaxter@gmail.com
+; Modified by Peter Gavin, pgavin@gmail.com
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <http://www.gnu.org/licenses/>
+
+(include "simplify.inc")
+
+; The OpenRISC family is a set of RISC microprocessor architectures with an
+; emphasis on scalability and is targetted at embedded use.
+; The CPU RTL development is a collaborative open source effort.
+; http://opencores.org/or1k
+; http://openrisc.net
+
+(define-arch
+ (name or1k)
+ (comment "OpenRISC 1000")
+ (default-alignment aligned)
+ (insn-lsb0? #t)
+ (machs or32 or32nd or64 or64nd)
+ (isas openrisc)
+)
+
+; Instruction set parameters.
+(define-isa
+ ; Name of the ISA.
+ (name openrisc)
+ ; Base insturction length. The insns are always 32 bits wide.
+ (base-insn-bitsize 32)
+ )
+
+(define-pmacro OR32-MACHS or32,or32nd)
+(define-pmacro OR64-MACHS or64,or64nd)
+(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX64-MACHS or64,or64nd)
+
+(define-attr
+ (for model)
+ (type boolean)
+ (name NO-DELAY-SLOT)
+ (comment "does not have delay slots")
+ )
+
+(if (keep-mach? (or32 or32nd))
+ (begin
+ (define-cpu
+ (name or1k32bf)
+ (comment "OpenRISC 1000 32-bit CPU family")
+ (insn-endian big)
+ (data-endian big)
+ (word-bitsize 32)
+ (file-transform "")
+ )
+
+ (define-mach
+ (name or32)
+ (comment "Generic OpenRISC 1000 32-bit CPU")
+ (cpu or1k32bf)
+ (bfd-name "or1k")
+ )
+
+ (define-mach
+ (name or32nd)
+ (comment "Generic OpenRISC 1000 32-bit CPU")
+ (cpu or1k32bf)
+ (bfd-name "or1knd")
+ )
+
+ ; OpenRISC 1200 - 32-bit or1k CPU implementation
+ (define-model
+ (name or1200) (comment "OpenRISC 1200 model")
+ (attrs)
+ (mach or32)
+ (unit u-exec "Execution Unit" () 1 1 () () () ())
+ )
+
+ ; OpenRISC 1200 - 32-bit or1k CPU implementation
+ (define-model
+ (name or1200nd) (comment "OpenRISC 1200 model")
+ (attrs NO-DELAY-SLOT)
+ (mach or32nd)
+ (unit u-exec "Execution Unit" () 1 1 () () () ())
+ )
+ )
+ )
+
+(if (keep-mach? (or64 or64nd))
+ (begin
+ (define-cpu
+ (name or1k64bf)
+ (comment "OpenRISC 1000 64-bit CPU family")
+ (insn-endian big)
+ (data-endian big)
+ (word-bitsize 64)
+ (file-transform "64")
+ )
+
+ (define-mach
+ (name or64)
+ (comment "Generic OpenRISC 1000 64-bit CPU")
+ (cpu or1k64bf)
+ (bfd-name "or1k64")
+ )
+
+ (define-mach
+ (name or64nd)
+ (comment "Generic OpenRISC 1000 ND 64-bit CPU")
+ (cpu or1k64bf)
+ (bfd-name "or1k64nd")
+ )
+ )
+ )
+
+(include "or1kcommon.cpu")
+(include "or1korbis.cpu")
+(include "or1korfpx.cpu")
diff --git a/cpu/or1k.opc b/cpu/or1k.opc
new file mode 100644
index 0000000..354105e
--- /dev/null
+++ b/cpu/or1k.opc
@@ -0,0 +1,423 @@
+/* OpenRISC 1000 opcode support. -*- C -*-
+ Copyright 2000-2001, 2003, 2005, 2011-2014
+ Free Software Foundation, Inc.
+
+ Originally ontributed for OR32 by Red Hat Inc;
+
+ This file is part of the GNU Binutils.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>. */
+
+/* This file is an addendum to or1k.cpu. Heavy use of C code isn't
+ appropriate in .cpu files, so it resides here. This especially applies
+ to assembly/disassembly where parsing/printing can be quite involved.
+ Such things aren't really part of the specification of the cpu, per se,
+ so .cpu files provide the general framework and .opc files handle the
+ nitty-gritty details as necessary.
+
+ Each section is delimited with start and end markers.
+
+ <arch>-opc.h additions use: "-- opc.h"
+ <arch>-opc.c additions use: "-- opc.c"
+ <arch>-asm.c additions use: "-- asm.c"
+ <arch>-dis.c additions use: "-- dis.c"
+ <arch>-ibd.h additions use: "-- ibd.h" */
+
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 256
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
+
+/* -- */
+
+/* -- opc.c */
+/* -- */
+
+/* -- asm.c */
+
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+static const char *
+parse_disp26 (CGEN_CPU_DESC cd,
+ const char ** strp,
+ int opindex,
+ int opinfo,
+ enum cgen_parse_operand_result * resultp,
+ bfd_vma * valuep)
+{
+ const char *errmsg = NULL;
+ enum cgen_parse_operand_result result_type;
+
+ if (strncasecmp (*strp, "plt(", 4) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 4;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_PLT26,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 2) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep);
+}
+
+static const char *
+parse_simm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
+{
+ const char *errmsg;
+ enum cgen_parse_operand_result result_type;
+ long ret;
+
+ if (**strp == '#')
+ ++*strp;
+
+ if (strncasecmp (*strp, "hi(", 3) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 3;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+ & result_type, & value);
+ if (**strp != ')')
+ errmsg = MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+
+ ret = value;
+
+ if (errmsg == NULL &&
+ result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) {
+ ret >>= 16;
+ ret &= 0xffff;
+ ret = (ret ^ 0x8000) - 0x8000;
+ }
+ }
+ else if (strncasecmp (*strp, "lo(", 3) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 3;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+
+ ret = value;
+
+ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) {
+ ret &= 0xffff;
+ ret = (ret ^ 0x8000) - 0x8000;
+ }
+
+ }
+ else if (strncasecmp (*strp, "got(", 4) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 4;
+ errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_OR1K_GOT16,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gotpchi(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_GOTPC_HI16,
+ & result_type, & value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gotpclo(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_GOTPC_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gotoffhi(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_GOTOFF_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gotofflo(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_GOTOFF_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tlsgdhi(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_GD_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tlsgdlo(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_GD_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tlsldmhi(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LDM_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tlsldmlo(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LDM_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "dtpoffhi(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LDO_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "dtpofflo(", 9) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 9;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LDO_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gottpoffhi(", 11) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 11;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_IE_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "gottpofflo(", 11) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 11;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_IE_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tpoffhi(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LE_HI16,
+ & result_type, & value);
+
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value = (value >> 16) & 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else if (strncasecmp (*strp, "tpofflo(", 8) == 0)
+ {
+ bfd_vma value;
+
+ *strp += 8;
+ errmsg = cgen_parse_address (cd, strp, opindex,
+ BFD_RELOC_OR1K_TLS_LE_LO16,
+ &result_type, &value);
+ if (**strp != ')')
+ return MISSING_CLOSING_PARENTHESIS;
+ ++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ value &= 0xffff;
+ *valuep = value;
+ return errmsg;
+ }
+ else
+ {
+ long value;
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
+ ret = value;
+ }
+
+ if (errmsg == NULL) {
+
+ *valuep = ret;
+
+ }
+
+ return errmsg;
+}
+
+static const char *
+parse_uimm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep)
+{
+ const char *errmsg = parse_simm16(cd, strp, opindex, (long *) valuep);
+ if (errmsg == NULL)
+ *valuep &= 0xffff;
+ return errmsg;
+}
+
+/* -- */
+
+/* -- ibd.h */
+
+/* -- */
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
new file mode 100644
index 0000000..599fe1b
--- /dev/null
+++ b/cpu/or1kcommon.cpu
@@ -0,0 +1,360 @@
+; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
+; Copyright 2000, 2001, 2011-2012 Free Software Foundation, Inc.
+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
+; Modified by Julius Baxter, juliusbaxter@gmail.com
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <http://www.gnu.org/licenses/>
+
+; Hardware pieces.
+; These entries list the elements of the raw hardware.
+; They're also used to provide tables and other elements of the assembly
+; language.
+
+(define-hardware
+ (name h-pc)
+ (comment "program counter")
+ (attrs PC (MACH ORBIS-MACHS))
+ (type pc UWI)
+ )
+
+(define-pmacro REG-INDICES
+ ((r0 0)
+ (r1 1)
+ (r2 2)
+ (r3 3)
+ (r4 4)
+ (r5 5)
+ (r6 6)
+ (r7 7)
+ (r8 8)
+ (r9 9)
+ (r10 10)
+ (r11 11)
+ (r12 12)
+ (r13 13)
+ (r14 14)
+ (r15 15)
+ (r16 16)
+ (r17 17)
+ (r18 18)
+ (r19 19)
+ (r20 20)
+ (r21 21)
+ (r22 22)
+ (r23 23)
+ (r24 24)
+ (r25 25)
+ (r26 26)
+ (r27 27)
+ (r28 28)
+ (r29 29)
+ (r30 30)
+ (r31 31)
+ (lr 9)
+ (sp 1)
+ (fp 2))
+ )
+
+(define-hardware
+ (name h-fsr)
+ (comment "floating point registers (single, virtual)")
+ (attrs VIRTUAL (MACH ORFPX32-MACHS))
+ (type register SF (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
+ (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
+ )
+
+(define-hardware
+ (name h-fdr) (comment "floating point registers (double, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64-MACHS))
+ (type register DF (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
+ (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
+ )
+
+(define-hardware
+ (name h-spr) (comment "special purpose registers")
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI (#x20000))
+ (get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
+ (set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
+)
+
+(define-pmacro spr-shift 11)
+(define-pmacro (spr-address spr-group spr-index)
+ (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
+ (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+
+(define-hardware
+ (name h-gpr) (comment "general registers")
+ (attrs (MACH ORBIS-MACHS))
+ (type register UWI (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
+ (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
+ )
+
+(define-normal-enum
+ except-number
+ "Exception numbers"
+ ()
+ EXCEPT-
+ (("NONE" #x00)
+ ("RESET" #x01)
+ ("BUSERR" #x02)
+ ("DPF" #x03)
+ ("IPF" #x04)
+ ("TICK" #x05)
+ ("ALIGN" #x06)
+ ("ILLEGAL" #x07)
+ ("INT" #x08)
+ ("DTLBMISS" #x09)
+ ("ITLBMISS" #x0a)
+ ("RANGE" #x0b)
+ ("SYSCALL" #x0c)
+ ("FPE" #x0d)
+ ("TRAP" #x0e)
+ )
+ )
+
+(define-pmacro (raise-exception exnum)
+ (c-call VOID "@cpu@_exception" pc exnum))
+
+(define-normal-enum
+ spr-groups
+ "special purpose register groups"
+ ()
+ SPR-GROUP-
+ (("SYS" #x0)
+ ("DMMU" #x1)
+ ("IMMU" #x2)
+ ("DCACHE" #x3)
+ ("ICACHE" #x4)
+ ("MAC" #x5)
+ ("DEBUG" #x6)
+ ("PERF" #x7)
+ ("POWER" #x8)
+ ("PIC" #x9)
+ ("TICK" #xa)
+ ("FPU" #xb)
+ )
+ )
+
+(define-pmacro (spr-reg-info)
+ (.splice
+ (SYS VR #x000 "version register")
+ (SYS UPR #x001 "unit present register")
+ (SYS CPUCFGR #x002 "cpu configuration register")
+ (SYS DMMUCFGR #x003 "Data MMU configuration register")
+ (SYS IMMUCFGR #x004 "Insn MMU configuration register")
+ (SYS DCCFGR #x005 "Data cache configuration register")
+ (SYS ICCFGR #x006 "Insn cache configuration register")
+ (SYS DCFGR #x007 "Debug configuration register")
+ (SYS PCCFGR #x008 "Performance counters configuration register")
+ (SYS NPC #x010 "Next program counter")
+ (SYS SR #x011 "Supervision Regsiter")
+ (SYS PPC #x012 "Previous program counter")
+ (SYS FPCSR #x014 "Floating point control status register")
+ (.unsplice
+ (.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n)))
+ (.iota #x10)))
+ (.unsplice
+ (.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n)))
+ (.iota #x10)))
+ (.unsplice
+ (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n)))
+ (.iota #x10)))
+ (.unsplice
+ (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n)))
+ (.iota #x200)))
+
+ (MAC MACLO #x001 "Multiply and accumulate result (low)")
+ (MAC MACHI #x002 "Multiply and accumulate result (high)")
+ (TICK TTMR #x000 "Tick timer mode register")
+ )
+ )
+
+(define-normal-enum
+ spr-reg-indices
+ "special purpose register indicies"
+ ()
+ SPR-INDEX-
+ (.map (.pmacro (args)
+ (.apply (.pmacro (group index n comment)
+ ((.sym group "-" index) n))
+ args)
+ )
+ (spr-reg-info)
+ )
+ )
+
+(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment)
+ (define-hardware
+ (name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index)))
+ (comment spr-comment)
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI)
+ (get () (reg UWI h-spr (spr-address spr-group spr-index)))
+ (set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval))
+ )
+ )
+(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info))))
+
+(define-pmacro (spr-field-info)
+ ((SYS VR REV 5 0 "revision field")
+ (SYS VR CFG 23 16 "configuration template field")
+ (SYS VR VER 31 24 "version field")
+ (SYS UPR UP 0 0 "UPR present bit")
+ (SYS UPR DCP 1 1 "data cache present bit")
+ (SYS UPR ICP 2 2 "insn cache present bit")
+ (SYS UPR DMP 3 3 "data MMU present bit")
+ (SYS UPR MP 4 4 "MAC unit present bit")
+ (SYS UPR IMP 5 5 "insn MMU present bit")
+ (SYS UPR DUP 6 6 "debug unit present bit")
+ (SYS UPR PCUP 7 7 "performance counters unit present bit")
+ (SYS UPR PICP 8 8 "programmable interrupt controller present bit")
+ (SYS UPR PMP 9 9 "power management present bit")
+ (SYS UPR TTP 10 10 "tick timer present bit")
+ (SYS UPR CUP 31 24 "custom units present field")
+ (SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field")
+ (SYS CPUCFGR CGF 4 4 "custom GPR file bit")
+ (SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit")
+ (SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit")
+ (SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit")
+ (SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit")
+ (SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit")
+ (SYS CPUCFGR ND 10 10 "no transfer delay bit")
+ (SYS SR SM 0 0 "supervisor mode bit")
+ (SYS SR TEE 1 1 "tick timer exception enabled bit")
+ (SYS SR IEE 2 2 "interrupt exception enabled bit")
+ (SYS SR DCE 3 3 "data cache enabled bit")
+ (SYS SR ICE 4 4 "insn cache enabled bit")
+ (SYS SR DME 5 5 "data MMU enabled bit")
+ (SYS SR IME 6 6 "insn MMU enabled bit")
+ (SYS SR LEE 7 7 "little endian enabled bit")
+ (SYS SR CE 8 8 "CID enable bit")
+ (SYS SR F 9 9 "flag bit")
+ (SYS SR CY 10 10 "carry bit")
+ (SYS SR OV 11 11 "overflow bit")
+ (SYS SR OVE 12 12 "overflow exception enabled bit")
+ (SYS SR DSX 13 13 "delay slot exception bit")
+ (SYS SR EPH 14 14 "exception prefix high bit")
+ (SYS SR FO 15 15 "fixed one bit")
+ (SYS SR SUMRA 16 16 "SPRs user mode read access bit")
+ (SYS SR CID 31 28 "context ID field")
+ (SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit")
+ (SYS FPCSR RM 2 1 "floating point rounding mode field")
+ (SYS FPCSR OVF 3 3 "floating point overflow flag bit")
+ (SYS FPCSR UNF 4 4 "floating point underflow bit")
+ (SYS FPCSR SNF 5 5 "floating point SNAN flag bit")
+ (SYS FPCSR QNF 6 6 "floating point QNAN flag bit")
+ (SYS FPCSR ZF 7 7 "floating point zero flag bit")
+ (SYS FPCSR IXF 8 8 "floating point inexact flag bit")
+ (SYS FPCSR IVF 9 9 "floating point invalid flag bit")
+ (SYS FPCSR INF 10 10 "floating point infinity flag bit")
+ (SYS FPCSR DZF 11 11 "floating point divide by zero flag bit")
+ )
+ )
+
+(define-normal-enum
+ spr-field-msbs
+ "SPR field msb positions"
+ ()
+ SPR-FIELD-MSB-
+ (.map (.pmacro (args)
+ (.apply (.pmacro (group index field msb lsb comment)
+ ((.sym group "-" index "-" field) msb)
+ )
+ args
+ )
+ )
+ (spr-field-info)
+ )
+ )
+
+(define-normal-enum
+ spr-field-lsbs
+ "SPR field lsb positions"
+ ()
+ SPR-FIELD-SIZE-
+ (.map (.pmacro (args)
+ (.apply (.pmacro (group index field msb lsb comment)
+ ((.sym group "-" index "-" field) lsb)
+ )
+ args
+ )
+ )
+ (spr-field-info)
+ )
+ )
+
+(define-normal-enum
+ spr-field-masks
+ "SPR field masks"
+ ()
+ SPR-FIELD-MASK-
+ (.map (.pmacro (args)
+ (.apply (.pmacro (group index field msb lsb comment)
+ (.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb))
+ )
+ args
+ )
+ )
+ (spr-field-info)
+ )
+ )
+
+(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment)
+ (.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field)))
+ )
+ (begin
+ (define-hardware
+ (name spr-field-name)
+ (comment spr-field-comment)
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI)
+ (get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb))
+ (set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value))
+ )
+ )
+ )
+ )
+(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info))))
+
+(define-attr
+ (type boolean)
+ (for insn)
+ (name DELAYED-CTI)
+ (comment "delayed control transfer instruction")
+ (values #f #t)
+ (default #f)
+ )
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name NOT-IN-DELAY-SLOT)
+ (comment "instruction cannot be in delay slot")
+ (values #f #t)
+ (default #f)
+ )
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name FORCED-CTI)
+ (comment "instruction may forcefully transfer control (e.g., rfe)")
+ )
diff --git a/cpu/or1korbis.cpu b/cpu/or1korbis.cpu
new file mode 100644
index 0000000..4561e97
--- /dev/null
+++ b/cpu/or1korbis.cpu
@@ -0,0 +1,1080 @@
+; OpenRISC Basic Instruction Set 32-bit (ORBIS) -*- Scheme -*-
+; Copyright 2000, 2001, 2011-2012 Free Software Foundation, Inc.
+; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
+; Modified by Julius Baxter, juliusbaxter@gmail.com
+; Modified by Peter Gavin, pgavin@gmail.com
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <http://www.gnu.org/licenses/>
+
+; Instruction fields.
+
+; Hardware for immediate operands
+(dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ())
+(dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ())
+(dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ())
+
+; Instruction classes.
+(dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6)
+
+; Register fields.
+(dnf f-r1 "r1" ((MACH ORBIS-MACHS)) 25 5)
+(dnf f-r2 "r2" ((MACH ORBIS-MACHS)) 20 5)
+(dnf f-r3 "r3" ((MACH ORBIS-MACHS)) 15 5)
+
+; Sub fields
+(dnf f-op-25-2 "op-25-2" ((MACH ORBIS-MACHS)) 25 2) ;; nop
+(dnf f-op-25-5 "op-25-5" ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf*
+(dnf f-op-16-1 "op-16-1" ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc
+(dnf f-op-7-4 "op-7-4" ((MACH ORBIS-MACHS)) 7 4)
+(dnf f-op-3-4 "op-3-4" ((MACH ORBIS-MACHS)) 3 4)
+(dnf f-op-9-2 "op-9-2" ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode
+(dnf f-op-9-4 "op-9-4" ((MACH ORBIS-MACHS)) 9 4) ;;
+(dnf f-op-7-8 "op-7-8" ((MACH ORBIS-MACHS)) 7 8)
+(dnf f-op-7-2 "op-7-2" ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti
+
+; Reserved fields
+(dnf f-resv-25-26 "resv-25-26" ((MACH ORBIS-MACHS) RESERVED) 25 26)
+(dnf f-resv-25-10 "resv-25-10" ((MACH ORBIS-MACHS) RESERVED) 25 10)
+(dnf f-resv-25-5 "resv-25-5" ((MACH ORBIS-MACHS) RESERVED) 25 5)
+(dnf f-resv-23-8 "resv-23-8" ((MACH ORBIS-MACHS) RESERVED) 23 8)
+(dnf f-resv-20-5 "resv-20-5" ((MACH ORBIS-MACHS) RESERVED) 20 5)
+(dnf f-resv-20-4 "resv-20-4" ((MACH ORBIS-MACHS) RESERVED) 20 4)
+(dnf f-resv-15-8 "resv-15-8" ((MACH ORBIS-MACHS) RESERVED) 15 8)
+(dnf f-resv-15-6 "resv-15-6" ((MACH ORBIS-MACHS) RESERVED) 15 6)
+(dnf f-resv-10-11 "resv-10-11" ((MACH ORBIS-MACHS) RESERVED) 10 11)
+(dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7)
+(dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3)
+(dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1)
+(dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4)
+(dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2)
+
+(dnf f-imm16-25-5 "imm16-25-5" ((MACH ORBIS-MACHS)) 25 5)
+(dnf f-imm16-10-11 "imm16-10-11" ((MACH ORBIS-MACHS)) 10 11)
+
+; PC relative, 26-bit (2 shifted to right)
+(df f-disp26
+ "disp26"
+ ((MACH ORBIS-MACHS) PCREL-ADDR)
+ 25
+ 26
+ INT
+ ((value pc) (sra SI (sub IAI value pc) (const 2)))
+ ((value pc) (add IAI (sll IAI value (const 2)) pc))
+ )
+
+; Immediates.
+(dnf f-uimm16 "uimm16" ((MACH ORBIS-MACHS)) 15 16)
+(df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f)
+(dnf f-uimm6 "uimm6" ((MACH ORBIS-MACHS)) 5 6) ;; shroti
+
+(define-multi-ifield
+ (name f-uimm16-split)
+ (comment "16-bit split unsigned immediate")
+ (attrs (MACH ORBIS-MACHS))
+ (mode UINT)
+ (subfields f-imm16-25-5 f-imm16-10-11)
+ (insert (sequence ()
+ (set (ifield f-imm16-25-5)
+ (and (srl (ifield f-uimm16-split)
+ (const 11))
+ (const #x1f)))
+ (set (ifield f-imm16-10-11)
+ (and (ifield f-uimm16-split)
+ (const #x7ff)))))
+ (extract
+ (set (ifield f-uimm16-split)
+ (trunc UHI
+ (or (sll (ifield f-imm16-25-5)
+ (const 11))
+ (ifield f-imm16-10-11)))))
+ )
+
+(define-multi-ifield
+ (name f-simm16-split)
+ (comment "16-bit split signed immediate")
+ (attrs (MACH ORBIS-MACHS) SIGN-OPT)
+ (mode INT)
+ (subfields f-imm16-25-5 f-imm16-10-11)
+ (insert (sequence ()
+ (set (ifield f-imm16-25-5)
+ (and (sra (ifield f-simm16-split)
+ (const 11))
+ (const #x1f)))
+ (set (ifield f-imm16-10-11)
+ (and (ifield f-simm16-split)
+ (const #x7ff)))))
+ (extract
+ (set (ifield f-simm16-split)
+ (trunc HI
+ (or (sll (ifield f-imm16-25-5)
+ (const 11))
+ (ifield f-imm16-10-11)))))
+ )
+
+; Enums.
+
+; insn-opcode: bits 31-26
+(define-normal-insn-enum
+ insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode
+ (("J" #x00)
+ ("JAL" #x01)
+ ("BNF" #x03)
+ ("BF" #x04)
+ ("NOP" #x05)
+ ("MOVHIMACRC" #x06)
+ ("SYSTRAPSYNCS" #x08)
+ ("RFE" #x09)
+ ("VECTOR" #x0a)
+ ("JR" #x11)
+ ("JALR" #x12)
+ ("MACI" #x13)
+ ("CUST1" #x1c)
+ ("CUST2" #x1d)
+ ("CUST3" #x1e)
+ ("CUST4" #x1f)
+ ("LD" #x20)
+ ("LWZ" #x21)
+ ("LWS" #x22)
+ ("LBZ" #x23)
+ ("LBS" #x24)
+ ("LHZ" #x25)
+ ("LHS" #x26)
+ ("ADDI" #x27)
+ ("ADDIC" #x28)
+ ("ANDI" #x29)
+ ("ORI" #x2a)
+ ("XORI" #x2b)
+ ("MULI" #x2c)
+ ("MFSPR" #x2d)
+ ("SHROTI" #x2e)
+ ("SFI" #x2f)
+ ("MTSPR" #x30)
+ ("MAC" #x31)
+ ("FLOAT" #x32)
+ ("SD" #x34)
+ ("SW" #x35)
+ ("SB" #x36)
+ ("SH" #x37)
+ ("ALU" #x38)
+ ("SF" #x39)
+ ("CUST5" #x3c)
+ ("CUST6" #x3d)
+ ("CUST7" #x3e)
+ ("CUST8" #x3f)
+ )
+)
+
+(define-normal-insn-enum insn-opcode-systrapsyncs
+ "systrapsync insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_SYSTRAPSYNCS_ f-op-25-5
+ (("SYSCALL" #x00 )
+ ("TRAP" #x08 )
+ ("MSYNC" #x10 )
+ ("PSYNC" #x14 )
+ ("CSYNC" #x18 )
+ )
+)
+
+(define-normal-insn-enum insn-opcode-movehimacrc
+ "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_MOVHIMACRC_ f-op-16-1
+ (("MOVHI" #x0)
+ ("MACRC" #x1)
+ )
+)
+
+(define-normal-insn-enum insn-opcode-mac
+ "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_MAC_ f-op-3-4
+ (("MAC" #x1)
+ ("MSB" #x2)
+ )
+ )
+
+(define-normal-insn-enum insn-opcode-shorts
+ "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_SHROTS_ f-op-7-2
+ (("SLL" #x0 )
+ ("SRL" #x1 )
+ ("SRA" #x2 )
+ ("ROR" #x3 )
+ )
+)
+
+(define-normal-insn-enum insn-opcode-extbhs
+ "extend byte/half opcode enums" ((MACH ORBIS-MACHS))
+ OPC_EXTBHS_ f-op-9-4
+ (("EXTHS" #x0)
+ ("EXTBS" #x1)
+ ("EXTHZ" #x2)
+ ("EXTBZ" #x3)
+ )
+)
+
+(define-normal-insn-enum insn-opcode-extws
+ "extend word opcode enums" ((MACH ORBIS-MACHS))
+ OPC_EXTWS_ f-op-9-4
+ (("EXTWS" #x0)
+ ("EXTWZ" #x1)
+ )
+)
+
+(define-normal-insn-enum insn-opcode-alu-regreg
+ "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_ALU_REGREG_ f-op-3-4
+ (("ADD" #x0)
+ ("ADDC" #x1)
+ ("SUB" #x2)
+ ("AND" #x3)
+ ("OR" #x4)
+ ("XOR" #x5)
+ ("MUL" #x6)
+ ("SHROT" #x8)
+ ("DIV" #x9)
+ ("DIVU" #xA)
+ ("MULU" #xB)
+ ("EXTBH" #xC)
+ ("EXTW" #xD)
+ ("CMOV" #xE)
+ ("FFL1" #xF)
+ )
+)
+
+(define-normal-insn-enum insn-opcode-setflag
+ "setflag insn opcode enums" ((MACH ORBIS-MACHS))
+ OPC_SF_ f-op-25-5
+ (("EQ" #x00)
+ ("NE" #x01)
+ ("GTU" #x02)
+ ("GEU" #x03)
+ ("LTU" #x04)
+ ("LEU" #x05)
+ ("GTS" #x0A)
+ ("GES" #x0B)
+ ("LTS" #x0C)
+ ("LES" #x0D)
+ )
+)
+
+
+; Instruction operands.
+
+(dnop sys-sr "supervision register" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr f-nil)
+(dnop sys-esr0 "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0 f-nil)
+(dnop sys-epcr0 "exception PC register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0 f-nil)
+
+(dnop sys-sr-lee "SR little endian enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee f-nil)
+(dnop sys-sr-f "SR flag bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f f-nil)
+(dnop sys-sr-cy "SR carry bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy f-nil)
+(dnop sys-sr-ov "SR overflow bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov f-nil)
+(dnop sys-sr-ove "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove f-nil)
+(dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil)
+(dnop sys-cpucfgr-nd "CPUCFGR no delay bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd f-nil)
+(dnop sys-fpcsr-rm "floating point round mode" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm f-nil)
+
+(dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil)
+(dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil)
+
+(dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6)
+
+(dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1)
+(dnop rA "source register A" ((MACH ORBIS-MACHS)) h-gpr f-r2)
+(dnop rB "source register B" ((MACH ORBIS-MACHS)) h-gpr f-r3)
+
+(define-operand
+ (name disp26)
+ (comment "pc-rel 26 bit")
+ (attrs (MACH ORBIS-MACHS))
+ (type h-iaddr)
+ (index f-disp26)
+ (handlers (parse "disp26"))
+ )
+
+(define-operand
+ (name simm16)
+ (comment "16-bit signed immediate")
+ (attrs (MACH ORBIS-MACHS) SIGN-OPT)
+ (type h-simm16)
+ (index f-simm16)
+ (handlers (parse "simm16"))
+ )
+
+(define-operand
+ (name uimm16)
+ (comment "16-bit unsigned immediate")
+ (attrs (MACH ORBIS-MACHS))
+ (type h-uimm16)
+ (index f-uimm16)
+ (handlers (parse "uimm16"))
+ )
+
+(define-operand
+ (name simm16-split)
+ (comment "split 16-bit signed immediate")
+ (attrs (MACH ORBIS-MACHS) SIGN-OPT)
+ (type h-simm16)
+ (index f-simm16-split)
+ (handlers (parse "simm16"))
+)
+
+(define-operand
+ (name uimm16-split)
+ (comment "split 16-bit unsigned immediate")
+ (attrs (MACH ORBIS-MACHS))
+ (type h-uimm16)
+ (index f-uimm16-split)
+ (handlers (parse "uimm16"))
+)
+
+; Instructions.
+
+; Branch releated instructions
+
+(define-pmacro (cti-link-return)
+ (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8)))
+ )
+(define-pmacro (cti-transfer-control condition target)
+ ;; this mess is necessary because we're
+ ;; skipping the delay slot, but it's
+ ;; actually the start of the next basic
+ ;; block
+ (sequence ()
+ (if condition
+ (delay 1 (set IAI pc target))
+ (if sys-cpucfgr-nd
+ (delay 1 (set IAI pc (add pc 4))))
+ )
+ (if sys-cpucfgr-nd
+ (skip 1)
+ )
+ )
+ )
+
+(define-pmacro
+ (define-cti
+ cti-name
+ cti-comment
+ cti-attrs
+ cti-syntax
+ cti-format
+ cti-semantics)
+ (begin
+ (dni
+ cti-name
+ cti-comment
+ (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs))
+ cti-syntax
+ cti-format
+ (cti-semantics)
+ ()
+ )
+ )
+ )
+
+(define-cti
+ l-j
+ "jump (pc-relative iaddr)"
+ (!COND-CTI UNCOND-CTI)
+ "l.j ${disp26}"
+ (+ OPC_J disp26)
+ (.pmacro ()
+ (cti-transfer-control 1 disp26)
+ )
+ )
+
+(define-cti
+ l-jal
+ "jump and link (pc-relative iaddr)"
+ (!COND-CTI UNCOND-CTI)
+ "l.jal ${disp26}"
+ (+ OPC_JAL disp26)
+ (.pmacro ()
+ (sequence ()
+ (cti-link-return)
+ (cti-transfer-control 1 disp26)
+ )
+ )
+ )
+
+(define-cti
+ l-jr
+ "jump register (absolute iaddr)"
+ (!COND-CTI UNCOND-CTI)
+ "l.jr $rB"
+ (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0))
+ (.pmacro ()
+ (cti-transfer-control 1 rB)
+ )
+ )
+
+(define-cti
+ l-jalr
+ "jump register and link (absolute iaddr)"
+ (!COND-CTI UNCOND-CTI)
+ "l.jalr $rB"
+ (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) )
+ (.pmacro ()
+ (sequence ()
+ (cti-link-return)
+ (cti-transfer-control 1 rB)
+ )
+ )
+ )
+
+(define-cti
+ l-bnf
+ "branch if condition bit not set (pc relative iaddr)"
+ (COND-CTI !UNCOND-CTI)
+ "l.bnf ${disp26}"
+ (+ OPC_BNF disp26)
+ (.pmacro ()
+ (cti-transfer-control (not sys-sr-f) disp26)
+ )
+ )
+
+(define-cti
+ l-bf
+ "branch if condition bit set (pc relative iaddr)"
+ (COND-CTI !UNCOND-CTI)
+ "l.bf ${disp26}"
+ (+ OPC_BF disp26)
+ (.pmacro ()
+ (cti-transfer-control sys-sr-f disp26)
+ )
+ )
+
+(dni l-trap "trap (exception)"
+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
+ "l.trap ${uimm16}"
+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16)
+ ; Do exception entry handling in C function, PC set based on SR state
+ (raise-exception EXCEPT-TRAP)
+ ()
+)
+
+
+(dni l-sys "syscall (exception)"
+ ; This function may not be in delay slot
+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
+
+ "l.sys ${uimm16}"
+ (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16)
+ ; Do exception entry handling in C function, PC set based on SR state
+ (raise-exception EXCEPT-SYSCALL)
+ ()
+)
+
+
+(dni l-rfe "return from exception"
+ ; This function may not be in delay slot
+ ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI)
+
+ "l.rfe"
+ (+ OPC_RFE (f-resv-25-26 0))
+ (c-call VOID "@cpu@_rfe")
+ ()
+)
+
+
+; Misc instructions
+
+; l.nop with immediate must be first so it handles all l.nops in sim
+(dni l-nop-imm "nop uimm16"
+ ((MACH ORBIS-MACHS))
+ "l.nop ${uimm16}"
+ (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
+ (c-call VOID "@cpu@_nop" (zext UWI uimm16))
+ ()
+ )
+
+(if (application-is? SIMULATOR)
+ (begin)
+ (begin
+ (dni l-nop "nop"
+ ((MACH ORBIS-MACHS))
+ "l.nop"
+ (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
+ (nop)
+ ()
+ )
+ )
+)
+
+(dni l-movhi "movhi reg/uimm16"
+ ((MACH ORBIS-MACHS))
+ "l.movhi $rD,$uimm16"
+ (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16)
+ (set UWI rD (sll UWI (zext UWI uimm16) (const 16)))
+ ()
+)
+
+(dni l-macrc "macrc reg"
+ ((MACH ORBIS-MACHS))
+ "l.macrc $rD"
+ (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0))
+ (sequence ()
+ (set UWI rD mac-maclo)
+ (set UWI mac-maclo 0)
+ (set UWI mac-machi 0)
+ )
+ ()
+ )
+
+
+; System releated instructions
+
+(dni l-mfspr "mfspr"
+ ((MACH ORBIS-MACHS))
+ "l.mfspr $rD,$rA,${uimm16}"
+ (+ OPC_MFSPR rD rA uimm16)
+ (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16))))
+ ()
+)
+
+(dni l-mtspr "mtspr"
+ ((MACH ORBIS-MACHS))
+ "l.mtspr $rA,$rB,${uimm16-split}"
+ (+ OPC_MTSPR rA rB uimm16-split )
+ (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB)
+ ()
+)
+
+
+; Load instructions
+(define-pmacro (load-store-addr base offset size)
+ (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size))
+
+(dni l-lwz "l.lwz reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lwz $rD,${simm16}($rA)"
+ (+ OPC_LWZ rD rA simm16)
+ (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
+ ()
+)
+
+
+(dni l-lws "l.lws reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lws $rD,${simm16}($rA)"
+ (+ OPC_LWS rD rA simm16)
+ (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4))))
+ ()
+)
+
+(dni l-lbz "l.lbz reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lbz $rD,${simm16}($rA)"
+ (+ OPC_LBZ rD rA simm16)
+ (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1))))
+ ()
+)
+
+(dni l-lbs "l.lbz reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lbs $rD,${simm16}($rA)"
+ (+ OPC_LBS rD rA simm16)
+ (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1))))
+ ()
+)
+
+(dni l-lhz "l.lhz reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lhz $rD,${simm16}($rA)"
+ (+ OPC_LHZ rD simm16 rA)
+ (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2))))
+ ()
+)
+
+(dni l-lhs "l.lhs reg/simm16(reg)"
+ ((MACH ORBIS-MACHS))
+ "l.lhs $rD,${simm16}($rA)"
+ (+ OPC_LHS rD rA simm16)
+ (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2))))
+ ()
+)
+
+
+; Store instructions
+
+(define-pmacro (store-insn mnemonic opc-op mode size)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " simm16(reg)/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " ${simm16-split}($rA),$rB")
+ (+ opc-op rB rD simm16-split)
+ (set mode (mem mode (load-store-addr rA simm16-split size)) (trunc mode rB))
+ ()
+ )
+ )
+)
+
+(store-insn sw OPC_SW USI 4)
+(store-insn sb OPC_SB UQI 1)
+(store-insn sh OPC_SH UHI 2)
+
+
+
+; Shift and rotate instructions
+
+(define-pmacro (shift-insn mnemonic)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " reg/reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0)
+ OPC_ALU_REGREG_SHROT )
+ (set UWI rD (mnemonic rA rB))
+ ()
+ )
+ (dni (.sym l- mnemonic "i")
+ (.str "l." mnemonic " reg/reg/uimm6")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic "i $rD,$rA,${uimm6}")
+ (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6)
+ (set rD (mnemonic rA uimm6))
+ ()
+ )
+ )
+)
+
+(shift-insn sll)
+(shift-insn srl)
+(shift-insn sra)
+(shift-insn ror)
+
+
+; Arithmetic insns
+
+; ALU op macro
+(define-pmacro (alu-insn mnemonic)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " reg/reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
+ (set rD (mnemonic rA rB))
+ ()
+ )
+ )
+)
+
+(alu-insn and)
+(alu-insn or)
+(alu-insn xor)
+
+(define-pmacro (alu-carry-insn mnemonic)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " reg/reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
+ (sequence ()
+ (sequence ()
+ (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0))
+ (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0))
+ (set rD (mnemonic WI rA rB))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+ )
+ )
+ )
+
+(alu-carry-insn add)
+(alu-carry-insn sub)
+
+(dni (l-addc) "l.addc reg/reg/reg"
+ ((MACH ORBIS-MACHS))
+ ("l.addc $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC)
+ (sequence ()
+ (sequence ((BI tmp-sys-sr-cy))
+ (set BI tmp-sys-sr-cy sys-sr-cy)
+ (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy))
+ (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy))
+ (set rD (addc WI rA rB tmp-sys-sr-cy))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni (l-mul) "l.mul reg/reg/reg"
+ ((MACH ORBIS-MACHS))
+ ("l.mul $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL)
+ (sequence ()
+ (sequence ()
+ ; 2's complement overflow
+ (set BI sys-sr-ov (mul-o2flag WI rA rB))
+ ; 1's complement overflow
+ (set BI sys-sr-cy (mul-o1flag WI rA rB))
+ (set rD (mul WI rA rB))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni (l-mulu) "l.mulu reg/reg/reg"
+ ((MACH ORBIS-MACHS))
+ ("l.mulu $rD,$rA,$rB")
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU)
+ (sequence ()
+ (sequence ()
+ ; 2's complement overflow
+ (set BI sys-sr-ov 0)
+ ; 1's complement overflow
+ (set BI sys-sr-cy (mul-o1flag UWI rA rB))
+ (set rD (mul UWI rA rB))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni l-div "divide (signed)"
+ ((MACH ORBIS-MACHS))
+ "l.div $rD,$rA,$rB"
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV)
+ (sequence ()
+ (if (ne rB 0)
+ (sequence ()
+ (set BI sys-sr-cy 0)
+ (set WI rD (div WI rA rB))
+ )
+ (set BI sys-sr-cy 1)
+ )
+ (set BI sys-sr-ov 0)
+ (if (andif sys-sr-cy sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni l-divu "divide (unsigned)"
+ ((MACH ORBIS-MACHS))
+ "l.divu $rD,$rA,$rB"
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU)
+ (sequence ()
+ (if (ne rB 0)
+ (sequence ()
+ (set BI sys-sr-cy 0)
+ (set rD (udiv UWI rA rB))
+ )
+ (set BI sys-sr-cy 1)
+ )
+ (set BI sys-sr-ov 0)
+ (if (andif sys-sr-cy sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni l-ff1 "find first '1'"
+ ((MACH ORBIS-MACHS))
+ "l.ff1 $rD,$rA"
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1)
+ (set rD (c-call UWI "@cpu@_ff1" rA))
+ ()
+)
+
+(dni l-fl1 "find last '1'"
+ ((MACH ORBIS-MACHS))
+ "l.fl1 $rD,$rA"
+ (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1)
+ (set rD (c-call UWI "@cpu@_fl1" rA))
+ ()
+)
+
+
+(define-pmacro (alu-insn-simm mnemonic)
+ (begin
+ (dni (.sym l- mnemonic "i")
+ (.str "l." mnemonic " reg/reg/simm16")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic "i $rD,$rA,$simm16")
+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
+ (set rD (mnemonic rA (ext WI simm16)))
+ ()
+ )
+ )
+)
+
+(define-pmacro (alu-insn-uimm mnemonic)
+ (begin
+ (dni (.sym l- mnemonic "i")
+ (.str "l." mnemonic " reg/reg/uimm16")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic "i $rD,$rA,$uimm16")
+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16)
+ (set rD (mnemonic rA (zext UWI uimm16)))
+ ()
+ )
+ )
+)
+
+(alu-insn-uimm and)
+(alu-insn-uimm or)
+(alu-insn-simm xor)
+
+(define-pmacro (alu-carry-insn-simm mnemonic)
+ (begin
+ (dni (.sym l- mnemonic "i")
+ (.str "l." mnemonic "i reg/reg/simm16")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic "i $rD,$rA,$simm16")
+ (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
+ (sequence ()
+ (sequence ()
+ (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0))
+ (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0))
+ (set rD (mnemonic WI rA (ext WI simm16)))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+ )
+ )
+ )
+
+(alu-carry-insn-simm add)
+
+(dni (l-addic)
+ ("l.addic reg/reg/simm16")
+ ((MACH ORBIS-MACHS))
+ ("l.addic $rD,$rA,$simm16")
+ (+ OPC_ADDIC rD rA simm16)
+ (sequence ()
+ (sequence ((BI tmp-sys-sr-cy))
+ (set BI tmp-sys-sr-cy sys-sr-cy)
+ (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy))
+ (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy))
+ (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+)
+
+(dni (l-muli)
+ "l.muli reg/reg/simm16"
+ ((MACH ORBIS-MACHS))
+ ("l.muli $rD,$rA,$simm16")
+ (+ OPC_MULI rD rA simm16)
+ (sequence ()
+ (sequence ()
+ ; 2's complement overflow
+ (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16)))
+ ; 1's complement overflow
+ (set sys-sr-cy (mul-o1flag UWI rA (ext UWI simm16)))
+ (set rD (mul WI rA (ext WI simm16)))
+ )
+ (if (andif sys-sr-ov sys-sr-ove)
+ (raise-exception EXCEPT-RANGE))
+ )
+ ()
+ )
+
+(define-pmacro (extbh-insn mnemonic extop extmode truncmode)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " $rD,$rA")
+ (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH)
+ (set rD (extop extmode (trunc truncmode rA)))
+ ()
+ )
+ )
+ )
+
+(extbh-insn exths ext WI HI)
+(extbh-insn extbs ext WI QI)
+(extbh-insn exthz zext UWI UHI)
+(extbh-insn extbz zext UWI UQI)
+
+(define-pmacro (extw-insn mnemonic extop extmode truncmode)
+ (begin
+ (dni (.sym l- mnemonic)
+ (.str "l." mnemonic " reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l." mnemonic " $rD,$rA")
+ (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW)
+ (set rD (extop extmode (trunc truncmode rA)))
+ ()
+ )
+ )
+ )
+
+(extw-insn extws ext WI SI)
+(extw-insn extwz zext USI USI)
+
+(dni l-cmov
+ "l.cmov reg/reg/reg"
+ ((MACH ORBIS-MACHS))
+ "l.cmov $rD,$rA,$rB"
+ (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV)
+ (if sys-sr-f
+ (set UWI rD rA)
+ (set UWI rD rB)
+ )
+ ()
+ )
+
+; Compare instructions
+
+; Ordering compare
+(define-pmacro (sf-insn op)
+ (begin
+ (dni (.sym l- "sf" op "s") ; l-sfgts
+ (.str "l.sf" op "s reg/reg") ; "l.sfgts reg/reg"
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op "s $rA,$rB") ; "l.sfgts $rA,$rB"
+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0))
+ (set sys-sr-f (op WI rA rB)) ; (set sys-sr-f (gt WI rA rB))
+ ()
+ )
+ (dni (.sym l- "sf" op "si") ; l-sfgtsi
+ (.str "l.sf" op "si reg/simm16") ; "l.sfgtsi reg/simm16"
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op "si $rA,$simm16") ; "l.sfgtsi $rA,$simm16"
+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16) ; (+ OPC_SFI OPC_SF_GTS rA simm16)
+ (set sys-sr-f (op WI rA (ext WI simm16))) ; (set sys-sr-f (gt WI rA (ext WI simm16)))
+ ()
+ )
+ (dni (.sym l- "sf" op "u") ; l-sfgtu
+ (.str "l.sf" op "u reg/reg") ; "l.sfgtu reg/reg"
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op "u $rA,$rB") ; "l.sfgtu $rA,$rB"
+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0))
+ (set sys-sr-f ((.sym op "u") WI rA rB)) ; (set sys-sr-f (gtu WI rA rB))
+ ()
+ )
+ ; immediate is sign extended even for unsigned compare
+ (dni (.sym l- "sf" op "ui") ; l-sfgtui
+ (.str "l.sf" op "ui reg/simm16") ; "l.sfgtui reg/uimm16"
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op "ui $rA,$simm16") ; "l.sfgtui $rA,$simm16"
+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16) ; (+ OPC_SFI OPC_SF_GTU rA simm16)
+ (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16))) ; (set sys-sr-f (gtu WI rA (ext WI simm16)))
+ ()
+ )
+ )
+ )
+
+(sf-insn gt)
+(sf-insn ge)
+(sf-insn lt)
+(sf-insn le)
+
+; Equality compare
+(define-pmacro (sf-insn-eq op)
+ (begin
+ (dni (.sym l- "sf" op)
+ (.str "l." op " reg/reg")
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op " $rA,$rB")
+ (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0))
+ (set sys-sr-f (op WI rA rB))
+ ()
+ )
+ (dni (.sym l- "sf" op "i")
+ (.str "l.sf" op "i reg/simm16")
+ ((MACH ORBIS-MACHS))
+ (.str "l.sf" op "i $rA,$simm16")
+ (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16)
+ (set sys-sr-f (op WI rA (ext WI simm16)))
+ ()
+ )
+ )
+)
+
+(sf-insn-eq eq)
+(sf-insn-eq ne)
+
+(dni l-mac
+ "l.mac reg/reg"
+ ((MACH ORBIS-MACHS))
+ "l.mac $rA,$rB"
+ (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC)
+ (sequence ((WI prod) (DI result))
+ (set WI prod (mul WI rA rB))
+ (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
+ (set SI mac-machi (subword SI result 0))
+ (set SI mac-maclo (subword SI result 1))
+ )
+ ()
+ )
+
+(dni l-msb
+ "l.msb reg/reg"
+ ((MACH ORBIS-MACHS))
+ "l.msb $rA,$rB"
+ (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB)
+ (sequence ((WI prod) (DI result))
+ (set WI prod (mul WI rA rB))
+ (set DI result (sub (join DI SI mac-machi mac-maclo) (ext DI prod)))
+ (set SI mac-machi (subword SI result 0))
+ (set SI mac-maclo (subword SI result 1))
+ )
+ ()
+ )
+
+(dni l-maci
+ "l.maci reg/simm16"
+ ((MACH ORBIS-MACHS))
+ "l.maci $rA,${simm16}"
+ (+ OPC_MACI (f-resv-25-5 0) rA simm16)
+ (sequence ((WI prod) (DI result))
+ (set WI prod (mul WI (ext WI simm16) rA))
+ (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
+ (set SI mac-machi (subword SI result 0))
+ (set SI mac-maclo (subword SI result 1))
+ )
+ ()
+ )
+
+(define-pmacro (cust-insn cust-num)
+ (begin
+ (dni (.sym l- "cust" cust-num)
+ (.str "l.cust" cust-num)
+ ((MACH ORBIS-MACHS))
+ (.str "l.cust" cust-num)
+ (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0))
+ (nop)
+ ()
+ )
+ )
+ )
+
+(cust-insn "1")
+(cust-insn "2")
+(cust-insn "3")
+(cust-insn "4")
+(cust-insn "5")
+(cust-insn "6")
+(cust-insn "7")
+(cust-insn "8")
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
new file mode 100644
index 0000000..b97f642
--- /dev/null
+++ b/cpu/or1korfpx.cpu
@@ -0,0 +1,222 @@
+; OpenRISC 1000 architecture. -*- Scheme -*-
+; Copyright 2000, 2001, 2011-2012 Free Software Foundation, Inc.
+; Contributed by Peter Gavin, pgavin@gmail.com
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <http://www.gnu.org/licenses/>
+
+; Initial ORFPX32 instruction set
+
+; I'm not sure how CGEN handles rounding in FP operations, except for
+; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and
+; lf.div do not round according to the FPCSR RM field.
+; NaN, overflow, and underflow are not yet handled either.
+
+(define-normal-insn-enum insn-opcode-float-regreg
+ "floating point reg/reg insn opcode enums" ()
+ OPC_FLOAT_REGREG_ f-op-7-8
+ (("ADD_S" #x00)
+ ("SUB_S" #x01)
+ ("MUL_S" #x02)
+ ("DIV_S" #x03)
+ ("ITOF_S" #x04)
+ ("FTOI_S" #x05)
+ ("REM_S" #x06)
+ ("MADD_S" #x07)
+ ("SFEQ_S" #x08)
+ ("SFNE_S" #x09)
+ ("SFGT_S" #x0a)
+ ("SFGE_S" #x0b)
+ ("SFLT_S" #x0c)
+ ("SFLE_S" #x0d)
+ ("ADD_D" #x10)
+ ("SUB_D" #x11)
+ ("MUL_D" #x12)
+ ("DIV_D" #x13)
+ ("ITOF_D" #x14)
+ ("FTOI_D" #x15)
+ ("REM_D" #x16)
+ ("MADD_D" #x17)
+ ("SFEQ_D" #x18)
+ ("SFNE_D" #x19)
+ ("SFGT_D" #x1a)
+ ("SFGE_D" #x1b)
+ ("SFLT_D" #x1c)
+ ("SFLE_D" #x1d)
+ ("CUST1_S" #xd0)
+ ("CUST1_D" #xe0)
+ )
+ )
+
+(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
+(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
+(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
+
+(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+
+(define-pmacro (float-regreg-insn mnemonic)
+ (begin
+ (dni (.sym lf- mnemonic -s)
+ (.str "lf." mnemonic ".s reg/reg/reg")
+ ((MACH ORFPX-MACHS))
+ (.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
+ (set SF rDSF (mnemonic SF rASF rBSF))
+ ()
+ )
+ (dni (.sym lf- mnemonic -d)
+ (.str "lf." mnemonic ".d reg/reg/reg")
+ ((MACH ORFPX64-MACHS))
+ (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
+ (set DF rDDF (mnemonic DF rADF rBDF))
+ ()
+ )
+ )
+ )
+
+(float-regreg-insn add)
+(float-regreg-insn sub)
+(float-regreg-insn mul)
+(float-regreg-insn div)
+
+(dni lf-rem-s
+ "lf.rem.s reg/reg/reg"
+ ((MACH ORFPX-MACHS))
+ "lf.rem.s $rDSF,$rASF,$rBSF"
+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
+ (set SF rDSF (rem SF rASF rBSF))
+ ()
+ )
+(dni lf-rem-d
+ "lf.rem.d reg/reg/reg"
+ ((MACH ORFPX64-MACHS))
+ "lf.rem.d $rDDF,$rADF,$rBDF"
+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
+ (set DF rDDF (mod DF rADF rBDF))
+ ()
+ )
+
+(define-pmacro (get-rounding-mode)
+ (case INT sys-fpcsr-rm
+ ((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
+ ((1) 3) ; TOWARD-ZERO
+ ((2) 4) ; TOWARD-POSITIVE
+ (else 5) ; TOWARD-NEGATIVE
+ )
+ )
+
+(dni lf-itof-s
+ "lf.itof.s reg/reg"
+ ((MACH ORFPX-MACHS))
+ "lf.itof.s $rDSF,$rA"
+ (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
+ (set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
+ ()
+ )
+(dni lf-itof-d
+ "lf.itof.d reg/reg"
+ ((MACH ORFPX64-MACHS))
+ "lf.itof.d $rDSF,$rA"
+ (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
+ (set DF rDDF (float DF (get-rounding-mode) rA))
+ ()
+ )
+
+(dni lf-ftoi-s
+ "lf.ftoi.s reg/reg"
+ ((MACH ORFPX-MACHS))
+ "lf.ftoi.s $rD,$rASF"
+ (+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
+ (set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
+ ()
+ )
+
+(dni lf-ftoi-d
+ "lf.ftoi.d reg/reg"
+ ((MACH ORFPX64-MACHS))
+ "lf.ftoi.d $rD,$rADF"
+ (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
+ (set DI rD (fix DI (get-rounding-mode) rADF))
+ ()
+ )
+
+(define-pmacro (float-setflag-insn mnemonic)
+ (begin
+ (dni (.sym lf- mnemonic -s)
+ (.str "lf.sf" mnemonic ".s reg/reg")
+ ((MACH ORFPX-MACHS))
+ (.str "lf.sf" mnemonic ".s $rASF,$rBSF")
+ (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
+ (set BI sys-sr-f (mnemonic SF rASF rBSF))
+ ()
+ )
+ (dni (.sym lf- mnemonic -d)
+ (.str "lf.sf" mnemonic ".d reg/reg")
+ ((MACH ORFPX64-MACHS))
+ (.str "lf.sf" mnemonic ".d $rASF,$rBSF")
+ (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+ (set BI sys-sr-f (mnemonic DF rADF rBDF))
+ ()
+ )
+ )
+ )
+
+(float-setflag-insn eq)
+(float-setflag-insn ne)
+(float-setflag-insn ge)
+(float-setflag-insn gt)
+(float-setflag-insn lt)
+(float-setflag-insn le)
+
+(dni lf-madd-s
+ "lf.madd.s reg/reg/reg"
+ ((MACH ORFPX-MACHS))
+ "lf.madd.s $rDSF,$rASF,$rBSF"
+ (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
+ (set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
+ ()
+ )
+(dni lf-madd-d
+ "lf.madd.d reg/reg/reg"
+ ((MACH ORFPX64-MACHS))
+ "lf.madd.d $rDDF,$rADF,$rBDF"
+ (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
+ (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
+ ()
+ )
+
+(define-pmacro (float-cust-insn cust-num)
+ (begin
+ (dni (.sym "lf-cust" cust-num "-s")
+ (.str "lf.cust" cust-num ".s")
+ ((MACH ORFPX-MACHS))
+ (.str "lf.cust" cust-num ".s $rASF,$rBSF")
+ (+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
+ (nop)
+ ()
+ )
+ (dni (.sym "lf-cust" cust-num "-d")
+ (.str "lf.cust" cust-num ".d")
+ ((MACH ORFPX64-MACHS))
+ (.str "lf.cust" cust-num ".d")
+ (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
+ (nop)
+ ()
+ )
+ )
+ )
+
+(float-cust-insn "1")
--
1.7.10.4