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RE: [PATCH] Add MIPS ufr macro instruction
- From: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: "Maciej W. Rozycki" <macro at codesourcery dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Sat, 14 Dec 2013 18:51:02 +0000
- Subject: RE: [PATCH] Add MIPS ufr macro instruction
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- References: <0DA23CC379F5F945ACB41CF394B982774C835E at LEMAIL01 dot le dot imgtec dot org> <87vc01erxi dot fsf at talisman dot default> <87siuzcpp4 dot fsf at talisman dot default> <0DA23CC379F5F945ACB41CF394B982774CB15B at LEMAIL01 dot le dot imgtec dot org> <0DA23CC379F5F945ACB41CF394B982774CE268 at LEMAIL01 dot le dot imgtec dot org> <8738mm3pgb dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1311241820110 dot 21686 at tp dot orcam dot me dot uk> <0DA23CC379F5F945ACB41CF394B982774DAC1A at LEMAIL01 dot le dot imgtec dot org> <87fvq07ufx dot fsf at talisman dot default> <0DA23CC379F5F945ACB41CF394B982774DE91E at LEMAIL01 dot le dot imgtec dot org>,<87vbysiu3a dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com>
> Hi Andrew,
>
> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
> for all MIPS32 and MIPS64 targets? I realise some of them don't have an FPU,
> but if we see (presumably emulated) FPU instructions anyway, then I think we
> might as well follow the architecture names for the registers.
>
> E.g.:
>
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>> @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
>> { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
>> ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
>> mips_cp0_names_sb1,
>> mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
>> - mips_hwr_names_numeric },
>> + mips_cp1_names_numeric, mips_hwr_names_numeric },
>
>SB1 did have an FPU.
>
>If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
>entry having mips_cp1_names_mips3264. If not then let me know :-)
Yes that is fine.
Regards,
Andrew