Re: [PATCH/AArch64 3/3] * opcodes/aarch64-tbl.h (aarch64_opcode_table): Add back the "lost" instruction aliases for scalar compare and vector compare.

[James Greenhalgh <james dot greenhalgh at arm dot com>]

On Wed, Dec 11, 2013 at 03:50:01AM +0000, Dr. Philipp Tomsich wrote:
> GCC 4.8.x and (the current top-of-trunk for) 4.9 will generate at least some of
> these instructions. Hereâs one relevant snippet from aarch64-simd.md:
> > ;; fcm(eq|ge|gt|le|lt)
> > 
> > (define_insn "aarch64_cm<optab><mode>"
> >   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
> >         (neg:<V_cmp_result>
> >           (COMPARISONS:<V_cmp_result>
> >             (match_operand:VALLF 1 "register_operand" "w,w")
> >             (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
> >           )))]
> >   "TARGET_SIMD"
> >   "@
> >   fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
> >   fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
> >   [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
> > )
> 

Hi Philipp,

This pattern, through the <n_optab> code attribute, will only
generate instructions from the following set:

lt
  fcmgt %0, %2, %1
  fcmlt %0, %1, 0

le
  fcmge %0, %2, %1
  fcmle %0, %1, 0

eq
  fcmeq %0, %1, %2
  fcmeq %0, %1, 0

ge
  fcmge %0, %1, %1
  fcmge %0, %1, 0
  
gt
  fcmgt %0, %1, %2
  fcmgt %0, %1, 0

Each of these instructions appear in my copy of the ARMv8 ARMARM.

In fact, we have this explicit comment in aarch64/iterators.md calling
out the absence of the FCMLE and FCMLT 3 register variants and
describing the workaround.

;; For comparison operators we use the FCM* and CM* instructions.
;; As there are no CMLE or CMLT instructions which act on 3 vector
;; operands, we must use CMGE or CMGT and swap the order of the
;; source operands.

If you are seeing other instructions generated it is either a bug,
or some other pattern.

Thanks,
James