Re: [PATCH/AArch64 3/3] * opcodes/aarch64-tbl.h (aarch64_opcode_table): Add back the "lost" instruction aliases for scalar compare and vector compare.

["Dr. Philipp Tomsich" <philipp dot tomsich at theobroma-systems dot com>]

Marcus,

> In the meantime binutils 2.23 and now the recently released 2.24 do
> not support these mnemonics therefore gcc must not generate them and
> will need fixing to emit the appropriate architecture instruction
> instead.

GCC 4.8.x and (the current top-of-trunk for) 4.9 will generate at least some of
these instructions. Here’s one relevant snippet from aarch64-simd.md:
> ;; fcm(eq|ge|gt|le|lt)
> 
> (define_insn "aarch64_cm<optab><mode>"
>   [(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
>         (neg:<V_cmp_result>
>           (COMPARISONS:<V_cmp_result>
>             (match_operand:VALLF 1 "register_operand" "w,w")
>             (match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
>           )))]
>   "TARGET_SIMD"
>   "@
>   fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
>   fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
>   [(set_attr "type" "neon_fp_compare_<Vetype><q>")]
> )

Given that this is the behaviour for all release 4.8.x versions of the AArch64 
backend, I do believe that extending the assembler at least to the extent 
necessary to support the existing GCC versions would be advisable.

As this would require only the addition of all variants of the ‘fcm’-instruction,
I would be happy to revise the patch to limit the change to these instructions.

Thanks,
Philipp.