[PATCH/AArch64 3/3] * opcodes/aarch64-tbl.h (aarch64_opcode_table): Add back the "lost" instruction aliases for scalar compare and vector compare.

[Philipp Tomsich <philipp dot tomsich at theobroma-systems dot com>]

In v27 of the ARMv8 ISA various compare instructions were moved to new 
"Vector Compare" and "Scalar Compare" sections. However, some instructions
were lost in this move. 

GCC still generates some of these instructions at -O3 when compiling SPECfp.
This patch adds these aliases back to the assembler for consistency.

Tested on aarch64-apm-linux-gnu.

Thanks,
Philipp.


    * opcodes/aarch64-tbl.h (aarch64_opcode_table): Add back the "lost"
      instruction aliases for scalar compare and vector compare.

---
 opcodes/aarch64-tbl.h |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7c77768..5718821 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2112,6 +2112,24 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
   {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
   {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
+  /* Aliases for "Vector Compare" instructions. */
+  {"fcmlt", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAMESD, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"fcmle", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAMESD, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"fcmlt", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_FP3, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"fcmle", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_FP3, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"facle", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAMESD, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"faclt", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAMESD, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"facle", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_FP3, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"faclt", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_FP3, F_ALIAS | F_PSEUDO | F_SSIZE},
+  /* Aliases for "Scalar Compare" instructions. */
+  {"cmls", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAME, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"cmls", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_S_3SAMED, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"cmle", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAME, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"cmle", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_S_3SAMED, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"cmlo", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAME, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"cmlo", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_S_3SAMED, F_ALIAS | F_PSEUDO | F_SSIZE},
+  {"cmlt", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vm, Vn), QL_V3SAME, F_ALIAS | F_PSEUDO | F_SIZEQ},
+  {"cmlt", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sm, Sn), QL_S_3SAMED, F_ALIAS | F_PSEUDO | F_SSIZE},
 
   {0, 0, 0, 0, 0, 0, {}, {}, 0},
 };
-- 
1.7.2.5