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Re: [PATCH 5/6] x86/MPX: fix operand size handling

From: "Jan Beulich" <JBeulich at suse dot com>
To: "H.J. Lu" <hjl dot tools at gmail dot com>
Cc: <kirill dot yukhin at intel dot com>,"Binutils" <binutils at sourceware dot org>
Date: Thu, 10 Oct 2013 14:14:03 +0100
Subject: Re: [PATCH 5/6] x86/MPX: fix operand size handling
Authentication-results: sourceware.org; auth=none
References: <5254349502000078000F9A3D at nat28 dot tlf dot novell dot com> <5254364802000078000F9A5D at nat28 dot tlf dot novell dot com> <CAMe9rOpB9=0rgvE0nOZ8o-C1R_EMamgGm8-BRB5DtOGYgs7V0Q at mail dot gmail dot com> <5255239602000078000F9DE5 at nat28 dot tlf dot novell dot com> <CAMe9rOqOWD_j1B9Qb+FkogoqL3pAn=ZwT6J1ugZeVjoFas5K0Q at mail dot gmail dot com>

>>> On 09.10.13 at 17:51, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Wed, Oct 9, 2013 at 12:36 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 08.10.13 at 17:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>>> On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> All MPX instructions in 64-bit mode ignore REX.W, which means we neither
>>>> need to encode this bit nor should disassemble with 32-bit register
>>>> operands.
>>>>
>>>> No MPX instructions would ever take a 16-bit register operand.
>>>>
>>>> gas/
>>>> 2013-10-08  Jan Beulich <jbeulich@suse.com>
>>>>
>>>>         * tc-i386.c (process_suffix): Warn about 32-bit register operands
>>>>         to MPX instructions in 64-bit mode.
>>>
>>> I think it should be an error.
>>
>> I can certainly change that - a warning just seemed a better match
>> to hardware ignoring operand size here.
> 
> We can use separate entries with Reg32 for CpuNo64 and Reg64 for Cpu64,
> similar to mov with debug registers.  Let's do that instead.

Here's  the updated patch.

Jan

General purpose register operands of MPX instructions can only ever be
native size ones.

opcodes/
2013-10-08  Jan Beulich <jbeulich@suse.com>

	* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
	default case.
	(OP_E_register): Move v_bnd_mode alongside m_mode.
	* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
	Drop Reg16 and Disp16. Add NoRex64.
	(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
	* i386-tbl.h: Re-generate.

--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
 	}
       /* FALLTHRU */
     case v_mode:
-    case v_bnd_mode:
     case v_swap_mode:
     case dq_mode:
       USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
 	abort ();
       oappend ("WORD PTR ");
       break;
+    case v_bnd_mode:
     default:
       break;
     }
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
       names = names64;
       break;
     case m_mode:
+    case v_bnd_mode:
       names = address_mode == mode_64bit ? names64 : names32;
       break;
     case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
       bytemode = v_mode;
       /* FALLTHRU */
     case v_mode:
-    case v_bnd_mode:
     case v_swap_mode:
     case dq_mode:
     case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3061,14 +3061,17 @@ stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSu
 bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
 
 // MPX instructions.
-bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
-bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND, RegBND }
+bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
+bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp32|Disp32S }
+bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
 
 // SHA instructions.
 sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }

Attachment: binutils-mainline-x86-MPX-operand-size.patch
Description: Text document

Follow-Ups:
- Re: [PATCH 5/6] x86/MPX: fix operand size handling
  - From: H.J. Lu

References:
- [PATCH 0/6] x86: various MPX fixes
  - From: Jan Beulich
- [PATCH 5/6] x86/MPX: fix operand size handling
  - From: Jan Beulich
- Re: [PATCH 5/6] x86/MPX: fix operand size handling
  - From: H.J. Lu
- Re: [PATCH 5/6] x86/MPX: fix operand size handling
  - From: Jan Beulich
- Re: [PATCH 5/6] x86/MPX: fix operand size handling
  - From: H.J. Lu

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