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RE: [PATCH] MIPS SIMD Architecture (MSA) patch
- From: Chao-Ying Fu <Chao-Ying dot Fu at imgtec dot com>
- To: 'Richard Sandiford' <rdsandiford at googlemail dot com>
- Cc: "'Maciej W. Rozycki'" <macro at codesourcery dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Thu, 10 Oct 2013 00:24:44 +0000
- Subject: RE: [PATCH] MIPS SIMD Architecture (MSA) patch
- Authentication-results: sourceware.org; auth=none
- References: <81D57523CB07B24881D63DE650C6ED82019034B4 at BADAG02 dot ba dot imgtec dot org> <87siwbr2os dot fsf at talisman dot default> <81D57523CB07B24881D63DE650C6ED82019039DC at BADAG02 dot ba dot imgtec dot org> <874n8rq66j dot fsf at talisman dot default>
Richard Sandiford wrote:
>
> The flow is that mips_parse_arguments is first called to parse all
> the arguments in one go. It converts them to an array of
> mips_operand_tokens. This array is then used instead of string
> parsing when matching the operands. (The parsing only happens
> once per .s instruction regardless of how many opcode alternatives
> we have to match against. Nothing other than mips_parse_arguments
> calls mips_parse_argument_token.)
>
> At the moment "xx[yy]" is one token, but my patch split it into two,
> a normal OT_REG for the "xx" followed by an OT_INTEGER_INDEX or
> OT_REG_INDEX for the "[yy]". So the array will contain two tokens
> that can be individually matched as two operands.
>
> "xx[yy]" could then be represented as "+a+b" in the opcode/*.c table
> (pretending that "a" and "b" are free). "+a" would be a
> normal OP_REG.
> "+b" would be a new OP_*. And the match_operand routine for that new
> OP_* would just check whether the next token in the array is a
> OT_INTEGER_INDEX or OT_REG_INDEX.
Thanks a lot! I got the assembler working from your patch and your descriptions.
Here is the revised patch based on your and Maciej's reviews.
Changes from last time include:
1. Add abi_msa_bfd.
2. Support MSA branch relaxation and its tests.
3. Use OT_IMM_INDEX or OT_REG_INDEX for MSA vector elements.
4. Remove the bug fix in mips-dis.c.
No new regressions are found for mips-sde-elf targets.
Any feedback? Thanks!
Regards,
Chao-ying
bfd/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* elfxx-mips.c (mips_elf_obj_tdata): Add abi_msa_bfd.
(mips_elf_merge_obj_attributes): Set abi_msa_bfd to the first object
file that has a Tag_GNU_MIPS_ABI_MSA attribute.
Merge Tag_GNU_MIPS_ABI_MSA attributes.
binutils/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* readelf.c (display_mips_gnu_attribute): Support Tag_GNU_MIPS_ABI_MSA.
* doc/binutils.texi: Document -Mmsa disassembler option.
gas/ChangeLog
2013-10-09 Richard Sandiford <rdsandiford@googlemail.com>
Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* config/tc-mips.c (options): Add OPTION_MSA and OPTION_NO_MSA.
(md_longopts): Add mmsa and mno-msa.
(mips_ases): Add msa.
(RTYPE_MASK): Update.
(RTYPE_MSA): New define.
(MSA_REGISTER_NAMES): New define.
(reg_names): Add MSA_REGISTER_NAMES.
(OT_REG_ELEMENT): Replace with...
(OT_INTEGER_INDEX, OT_REG_INDEX): ...these new operand types.
(mips_operand_token): Replace reg_element with index.
(mips_parse_argument_token): Treat vector indices as separate tokens.
Handle register indices.
(operand_reg_mask): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
(convert_reg_type): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
(match_mdmx_imm_reg_operand): Update accordingly.
(match_imm_index_operand): New function.
(match_reg_index_operand): New function.
(match_operand): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
(md_convert_frag): Convert bz.b/h/w/d, bnz.b/h/w/d, bz.v bnz.v.
(md_show_usage): Print -mmsa and -mno-msa.
* doc/c-mips.texi: Document -mmsa and -mno-msa.
Document .set msa and .set nomsa.
gas/testsuite/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* gas/mips/micromips@msa-relax.d, gas/mips/micromips@msa.d,
gas/mips/micromips@msa.s, gas/mips/micromips@msa64.d,
gas/mips/msa-relax.d, gas/mips/msa-relax.l, gas/mips/msa-relax.s,
gas/mips/msa.d, gas/mips/msa.s, gas/mips/msa64.d,
gas/mips/msa64.s: New.
* gas/mips/mips.exp: Run msa and msa64 tests.
include/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* elf/mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA.
(enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128.
* opcode/mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
(mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
For MIPS, update extension character sequences after +.
(ASE_MSA): New define.
(ASE_MSA64): New define.
For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
For microMIPS, update extension character sequences after +.
ld/testsuite/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* ld-mips-elf/attr-gnu-8-0.s, ld-mips-elf/attr-gnu-8-1.s,
ld-mips-elf/attr-gnu-8-2.s,
ld-mips-elf/attr-gnu-8-00.d, ld-mips-elf/attr-gnu-8-01.d,
ld-mips-elf/attr-gnu-8-02.d, ld-mips-elf/attr-gnu-8-10.d,
ld-mips-elf/attr-gnu-8-11.d, ld-mips-elf/attr-gnu-8-12.d,
ld-mips-elf/attr-gnu-8-20.d, ld-mips-elf/attr-gnu-8-21.d,
ld-mips-elf/attr-gnu-8-22.d: New.
* ld-mips-elf/mips-elf.exp: Run new tests.
opcodes/ChangeLog
2013-10-09 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
+d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
+~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
(MSA): New define.
(MSA64): New define.
(micromips_opcodes): Add MSA instructions.
* mips-dis.c (msa_control_names): New array.
(mips_abi_choice): Add ASE_MSA to mips32r2.
Add ASE_MSA and ASE_MSA64 to mips64r2.
(parse_mips_dis_option): When disassembling for MSA, disable ASE_MDMX.
(print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
(print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
(print_mips_disassembler_options): Print -Mmsa.
* mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
+l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
(MSA): New define.
(MSA64): New define.
(mips_builtin_op): Add MSA instructions.
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.360
diff -u -p -r1.360 elfxx-mips.c
--- bfd/elfxx-mips.c 24 Sep 2013 22:15:37 -0000 1.360
+++ bfd/elfxx-mips.c 9 Oct 2013 23:42:52 -0000
@@ -542,6 +542,9 @@ struct mips_elf_obj_tdata
/* Input BFD providing Tag_GNU_MIPS_ABI_FP attribute for output. */
bfd *abi_fp_bfd;
+ /* Input BFD providing Tag_GNU_MIPS_ABI_MSA attribute for output. */
+ bfd *abi_msa_bfd;
+
/* The GOT requirements of input bfds. */
struct mips_got_info *got;
@@ -14314,12 +14317,18 @@ mips_elf_merge_obj_attributes (bfd *ibfd
obj_attribute *in_attr;
obj_attribute *out_attr;
bfd *abi_fp_bfd;
+ bfd *abi_msa_bfd;
abi_fp_bfd = mips_elf_tdata (obfd)->abi_fp_bfd;
in_attr = elf_known_obj_attributes (ibfd)[OBJ_ATTR_GNU];
if (!abi_fp_bfd && in_attr[Tag_GNU_MIPS_ABI_FP].i != Val_GNU_MIPS_ABI_FP_ANY)
mips_elf_tdata (obfd)->abi_fp_bfd = ibfd;
+ abi_msa_bfd = mips_elf_tdata (obfd)->abi_msa_bfd;
+ if (!abi_msa_bfd
+ && in_attr[Tag_GNU_MIPS_ABI_MSA].i != Val_GNU_MIPS_ABI_MSA_ANY)
+ mips_elf_tdata (obfd)->abi_msa_bfd = ibfd;
+
if (!elf_known_obj_attributes_proc (obfd)[0].i)
{
/* This is the first object. Copy the attributes. */
@@ -14509,6 +14518,47 @@ mips_elf_merge_obj_attributes (bfd *ibfd
}
}
+ /* Check for conflicting Tag_GNU_MIPS_ABI_MSA attributes and merge
+ non-conflicting ones. */
+ if (in_attr[Tag_GNU_MIPS_ABI_MSA].i != out_attr[Tag_GNU_MIPS_ABI_MSA].i)
+ {
+ out_attr[Tag_GNU_MIPS_ABI_MSA].type = 1;
+ if (out_attr[Tag_GNU_MIPS_ABI_MSA].i == Val_GNU_MIPS_ABI_MSA_ANY)
+ out_attr[Tag_GNU_MIPS_ABI_MSA].i = in_attr[Tag_GNU_MIPS_ABI_MSA].i;
+ else if (in_attr[Tag_GNU_MIPS_ABI_MSA].i != Val_GNU_MIPS_ABI_MSA_ANY)
+ switch (out_attr[Tag_GNU_MIPS_ABI_MSA].i)
+ {
+ case Val_GNU_MIPS_ABI_MSA_128:
+ _bfd_error_handler
+ (_("Warning: %B uses %s (set by %B), "
+ "%B uses unknown MSA ABI %d"),
+ obfd, abi_msa_bfd, ibfd,
+ "-mmsa", in_attr[Tag_GNU_MIPS_ABI_MSA].i);
+ break;
+
+ default:
+ switch (in_attr[Tag_GNU_MIPS_ABI_MSA].i)
+ {
+ case Val_GNU_MIPS_ABI_MSA_128:
+ _bfd_error_handler
+ (_("Warning: %B uses unknown MSA ABI %d "
+ "(set by %B), %B uses %s"),
+ obfd, abi_msa_bfd, ibfd,
+ out_attr[Tag_GNU_MIPS_ABI_MSA].i, "-mmsa");
+ break;
+
+ default:
+ _bfd_error_handler
+ (_("Warning: %B uses unknown MSA ABI %d "
+ "(set by %B), %B uses unknown MSA ABI %d"),
+ obfd, abi_msa_bfd, ibfd,
+ out_attr[Tag_GNU_MIPS_ABI_MSA].i,
+ in_attr[Tag_GNU_MIPS_ABI_MSA].i);
+ break;
+ }
+ }
+ }
+
/* Merge Tag_compatibility attributes and any common GNU ones. */
_bfd_elf_merge_object_attributes (ibfd, obfd);
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.608
diff -u -p -r1.608 readelf.c
--- binutils/readelf.c 17 Sep 2013 21:09:27 -0000 1.608
+++ binutils/readelf.c 9 Oct 2013 23:42:52 -0000
@@ -11767,6 +11767,30 @@ display_mips_gnu_attribute (unsigned cha
return p;
}
+ if (tag == Tag_GNU_MIPS_ABI_MSA)
+ {
+ unsigned int len;
+ int val;
+
+ val = read_uleb128 (p, &len, end);
+ p += len;
+ printf (" Tag_GNU_MIPS_ABI_MSA: ");
+
+ switch (val)
+ {
+ case Val_GNU_MIPS_ABI_MSA_ANY:
+ printf (_("Any MSA or not\n"));
+ break;
+ case Val_GNU_MIPS_ABI_MSA_128:
+ printf (_("128-bit MSA\n"));
+ break;
+ default:
+ printf ("??? (%d)\n", val);
+ break;
+ }
+ return p;
+ }
+
return display_tag_value (tag & 1, p, end);
}
Index: binutils/doc/binutils.texi
===================================================================
RCS file: /cvs/src/src/binutils/doc/binutils.texi,v
retrieving revision 1.206
diff -u -p -r1.206 binutils.texi
--- binutils/doc/binutils.texi 23 Aug 2013 17:06:44 -0000 1.206
+++ binutils/doc/binutils.texi 9 Oct 2013 23:42:52 -0000
@@ -2114,6 +2114,9 @@ Print the 'raw' instruction mnemonic ins
instruction mnemonic. I.e., print 'daddu' or 'or' instead of 'move',
'sll' instead of 'nop', etc.
+@item msa
+Disassemble MSA instructions.
+
@item virt
Disassemble the virtualization ASE instructions.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.593
diff -u -p -r1.593 tc-mips.c
--- gas/config/tc-mips.c 17 Sep 2013 21:08:30 -0000 1.593
+++ gas/config/tc-mips.c 9 Oct 2013 23:42:53 -0000
@@ -1329,6 +1329,8 @@ enum options
OPTION_NO_MT,
OPTION_VIRT,
OPTION_NO_VIRT,
+ OPTION_MSA,
+ OPTION_NO_MSA,
OPTION_SMARTMIPS,
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
@@ -1440,6 +1442,8 @@ struct option md_longopts[] =
{"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
{"mvirt", no_argument, NULL, OPTION_VIRT},
{"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
+ {"mmsa", no_argument, NULL, OPTION_MSA},
+ {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
@@ -1586,6 +1590,10 @@ static const struct mips_ase mips_ases[]
{ "virt", ASE_VIRT, ASE_VIRT64,
OPTION_VIRT, OPTION_NO_VIRT,
+ 2, 2, 2, 2 },
+
+ { "msa", ASE_MSA, ASE_MSA64,
+ OPTION_MSA, OPTION_NO_MSA,
2, 2, 2, 2 }
};
@@ -2347,7 +2355,7 @@ struct regname {
};
#define RNUM_MASK 0x00000ff
-#define RTYPE_MASK 0x0efff00
+#define RTYPE_MASK 0x0ffff00
#define RTYPE_NUM 0x0000100
#define RTYPE_FPU 0x0000200
#define RTYPE_FCC 0x0000400
@@ -2363,6 +2371,7 @@ struct regname {
#define RTYPE_R5900_Q 0x0100000
#define RTYPE_R5900_R 0x0200000
#define RTYPE_R5900_ACC 0x0400000
+#define RTYPE_MSA 0x0800000
#define RWARN 0x8000000
#define GENERIC_REGISTER_NUMBERS \
@@ -2567,6 +2576,40 @@ struct regname {
{"$ac2", RTYPE_ACC | 2}, \
{"$ac3", RTYPE_ACC | 3}
+#define MSA_REGISTER_NAMES \
+ {"$w0", RTYPE_MSA | 0}, \
+ {"$w1", RTYPE_MSA | 1}, \
+ {"$w2", RTYPE_MSA | 2}, \
+ {"$w3", RTYPE_MSA | 3}, \
+ {"$w4", RTYPE_MSA | 4}, \
+ {"$w5", RTYPE_MSA | 5}, \
+ {"$w6", RTYPE_MSA | 6}, \
+ {"$w7", RTYPE_MSA | 7}, \
+ {"$w8", RTYPE_MSA | 8}, \
+ {"$w9", RTYPE_MSA | 9}, \
+ {"$w10", RTYPE_MSA | 10}, \
+ {"$w11", RTYPE_MSA | 11}, \
+ {"$w12", RTYPE_MSA | 12}, \
+ {"$w13", RTYPE_MSA | 13}, \
+ {"$w14", RTYPE_MSA | 14}, \
+ {"$w15", RTYPE_MSA | 15}, \
+ {"$w16", RTYPE_MSA | 16}, \
+ {"$w17", RTYPE_MSA | 17}, \
+ {"$w18", RTYPE_MSA | 18}, \
+ {"$w19", RTYPE_MSA | 19}, \
+ {"$w20", RTYPE_MSA | 20}, \
+ {"$w21", RTYPE_MSA | 21}, \
+ {"$w22", RTYPE_MSA | 22}, \
+ {"$w23", RTYPE_MSA | 23}, \
+ {"$w24", RTYPE_MSA | 24}, \
+ {"$w25", RTYPE_MSA | 25}, \
+ {"$w26", RTYPE_MSA | 26}, \
+ {"$w27", RTYPE_MSA | 27}, \
+ {"$w28", RTYPE_MSA | 28}, \
+ {"$w29", RTYPE_MSA | 29}, \
+ {"$w30", RTYPE_MSA | 30}, \
+ {"$w31", RTYPE_MSA | 31}
+
static const struct regname reg_names[] = {
GENERIC_REGISTER_NUMBERS,
FPU_REGISTER_NAMES,
@@ -2586,6 +2629,7 @@ static const struct regname reg_names[]
R5900_R_NAMES,
R5900_ACC_NAMES,
MIPS_DSP_ACCUMULATOR_NAMES,
+ MSA_REGISTER_NAMES,
{0, 0}
};
@@ -2747,8 +2791,11 @@ enum mips_operand_token_type {
/* A 4-bit XYZW channel mask. */
OT_CHANNELS,
- /* An element of a vector, e.g. $v0[1]. */
- OT_REG_ELEMENT,
+ /* A constant vector index, e.g. [1]. */
+ OT_INTEGER_INDEX,
+
+ /* A register vector index, e.g. [$2]. */
+ OT_REG_INDEX,
/* A continuous range of registers, e.g. $s0-$s4. */
OT_REG_RANGE,
@@ -2777,17 +2824,14 @@ struct mips_operand_token
enum mips_operand_token_type type;
union
{
- /* The register symbol value for an OT_REG. */
+ /* The register symbol value for an OT_REG or OT_REG_INDEX. */
unsigned int regno;
/* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
unsigned int channels;
- /* The register symbol value and index for an OT_REG_ELEMENT. */
- struct {
- unsigned int regno;
- addressT index;
- } reg_element;
+ /* The integer value of an OT_INTEGER_INDEX. */
+ addressT index;
/* The two register symbol values involved in an OT_REG_RANGE. */
struct {
@@ -2948,20 +2992,32 @@ mips_parse_argument_token (char *s, char
mips_add_token (&token, OT_REG_RANGE);
return s;
}
- else if (*s == '[')
- {
- /* A vector element. */
- expressionS element;
+ /* Add the register itself. */
+ token.u.regno = regno1;
+ mips_add_token (&token, OT_REG);
+
+ /* Check for a vector index. */
+ if (*s == '[')
+ {
++s;
SKIP_SPACE_TABS (s);
- my_getExpression (&element, s);
- if (element.X_op != O_constant)
+ if (mips_parse_register (&s, &token.u.regno, NULL))
+ mips_add_token (&token, OT_REG_INDEX);
+ else
{
- set_insn_error (0, _("vector element must be constant"));
- return 0;
+ expressionS element;
+
+ my_getExpression (&element, s);
+ if (element.X_op != O_constant)
+ {
+ set_insn_error (0, _("vector element must be constant"));
+ return 0;
+ }
+ s = expr_end;
+ token.u.index = element.X_add_number;
+ mips_add_token (&token, OT_INTEGER_INDEX);
}
- s = expr_end;
SKIP_SPACE_TABS (s);
if (*s != ']')
{
@@ -2969,16 +3025,7 @@ mips_parse_argument_token (char *s, char
return 0;
}
++s;
-
- token.u.reg_element.regno = regno1;
- token.u.reg_element.index = element.X_add_number;
- mips_add_token (&token, OT_REG_ELEMENT);
- return s;
}
-
- /* Looks like just a plain register. */
- token.u.regno = regno1;
- mips_add_token (&token, OT_REG);
return s;
}
@@ -4005,6 +4052,7 @@ operand_reg_mask (const struct mips_cl_i
case OP_PC:
case OP_VU0_SUFFIX:
case OP_VU0_MATCH_SUFFIX:
+ case OP_IMM_INDEX:
abort ();
case OP_REG:
@@ -4050,6 +4098,11 @@ operand_reg_mask (const struct mips_cl_i
if ((vsel & 0x18) == 0x18)
return 0;
return 1 << (uval & 31);
+
+ case OP_REG_INDEX:
+ if (!(type_mask & (1 << OP_REG_GP)))
+ return 0;
+ return 1 << insn_extract_operand (insn, operand);
}
abort ();
}
@@ -4408,6 +4461,12 @@ convert_reg_type (const struct mips_opco
case OP_REG_R5900_ACC:
return RTYPE_R5900_ACC;
+
+ case OP_REG_MSA:
+ return RTYPE_MSA;
+
+ case OP_REG_MSA_CTRL:
+ return RTYPE_NUM;
}
abort ();
}
@@ -5078,7 +5137,7 @@ match_mdmx_imm_reg_operand (struct mips_
uval = mips_extract_operand (operand, opcode->match);
is_qh = (uval != 0);
- if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
+ if (arg->token->type == OT_REG)
{
if ((opcode->membership & INSN_5400)
&& strcmp (opcode->name, "rzu.ob") == 0)
@@ -5088,20 +5147,21 @@ match_mdmx_imm_reg_operand (struct mips_
return FALSE;
}
+ if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
+ return FALSE;
+ ++arg->token;
+
/* Check whether this is a vector register or a broadcast of
a single element. */
- if (arg->token->type == OT_REG_ELEMENT)
+ if (arg->token->type == OT_INTEGER_INDEX)
{
- if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
- ®no))
- return FALSE;
- if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
+ if (arg->token->u.index > (is_qh ? 3 : 7))
{
set_insn_error (arg->argnum, _("invalid element selector"));
return FALSE;
}
- else
- uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
+ uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
+ ++arg->token;
}
else
{
@@ -5115,15 +5175,12 @@ match_mdmx_imm_reg_operand (struct mips_
return FALSE;
}
- if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
- return FALSE;
if (is_qh)
uval |= MDMX_FMTSEL_VEC_QH << 5;
else
uval |= MDMX_FMTSEL_VEC_OB << 5;
}
uval |= regno;
- ++arg->token;
}
else
{
@@ -5146,6 +5203,48 @@ match_mdmx_imm_reg_operand (struct mips_
return TRUE;
}
+/* OP_IMM_INDEX matcher. */
+
+static bfd_boolean
+match_imm_index_operand (struct mips_arg_info *arg,
+ const struct mips_operand *operand)
+{
+ int min_val, max_val;
+ if (arg->token->type != OT_INTEGER_INDEX)
+ return FALSE;
+
+ min_val = 0;
+ max_val = (1 << operand->size) - 1;
+
+ if ((int) arg->token->u.index < min_val
+ || (int) arg->token->u.index > max_val)
+ {
+ match_out_of_range (arg);
+ return FALSE;
+ }
+ insn_insert_operand (arg->insn, operand, arg->token->u.index);
+ ++arg->token;
+ return TRUE;
+}
+
+/* OP_REG_INDEX matcher. */
+
+static bfd_boolean
+match_reg_index_operand (struct mips_arg_info *arg,
+ const struct mips_operand *operand)
+{
+ unsigned int regno;
+ if (arg->token->type != OT_REG_INDEX)
+ return FALSE;
+
+ if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
+ return FALSE;
+
+ insn_insert_operand (arg->insn, operand, regno);
+ ++arg->token;
+ return TRUE;
+}
+
/* OP_PC matcher. */
static bfd_boolean
@@ -5426,6 +5525,12 @@ match_operand (struct mips_arg_info *arg
case OP_VU0_MATCH_SUFFIX:
return match_vu0_suffix_operand (arg, operand, TRUE);
+
+ case OP_IMM_INDEX:
+ return match_imm_index_operand (arg, operand);
+
+ case OP_REG_INDEX:
+ return match_reg_index_operand (arg, operand);
}
abort ();
}
@@ -16539,11 +16644,21 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU
switch ((insn >> 28) & 0xf)
{
case 4:
- /* bc[0-3][tf]l? instructions can have the condition
- reversed by tweaking a single TF bit, and their
- opcodes all have 0x4???????. */
- gas_assert ((insn & 0xf3e00000) == 0x41000000);
- insn ^= 0x00010000;
+ if ((insn & 0xff000000) == 0x47000000
+ || (insn & 0xff600000) == 0x45600000)
+ {
+ /* bz.df/bnz.df, bz.v/bnz.v can have the condition
+ reversed by tweaking bit 23. */
+ insn ^= 0x00800000;
+ }
+ else
+ {
+ /* bc[0-3][tf]l? instructions can have the condition
+ reversed by tweaking a single TF bit, and their
+ opcodes all have 0x4???????. */
+ gas_assert ((insn & 0xf3e00000) == 0x41000000);
+ insn ^= 0x00010000;
+ }
break;
case 0:
@@ -16810,6 +16925,11 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNU
|| (insn & 0xffe30000) == 0x42800000 /* bc2f */
|| (insn & 0xffe30000) == 0x42a00000) /* bc2t */
insn ^= 0x00200000;
+ else if ((insn & 0xff000000) == 0x83000000 /* bz.df
+ bnz.df */
+ || (insn & 0xff600000) == 0x81600000) /* bz.v
+ bnz.v */
+ insn ^= 0x00800000;
else
abort ();
@@ -18021,6 +18141,9 @@ MIPS options:\n\
-mmcu generate MCU instructions\n\
-mno-mcu do not generate MCU instructions\n"));
fprintf (stream, _("\
+-mmsa generate MSA instructions\n\
+-mno-msa do not generate MSA instructions\n"));
+ fprintf (stream, _("\
-mvirt generate Virtualization instructions\n\
-mno-virt do not generate Virtualization instructions\n"));
fprintf (stream, _("\
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.80
diff -u -p -r1.80 c-mips.texi
--- gas/doc/c-mips.texi 12 Jul 2013 15:58:14 -0000 1.80
+++ gas/doc/c-mips.texi 9 Oct 2013 23:42:53 -0000
@@ -179,6 +179,12 @@ Generate code for the MCU Application Sp
This tells the assembler to accept MCU instructions.
@samp{-mno-mcu} turns off this option.
+@item -mmsa
+@itemx -mno-msa
+Generate code for the MIPS SIMD Architecture Extension.
+This tells the assembler to accept MSA instructions.
+@samp{-mno-msa} turns off this option.
+
@item -mvirt
@itemx -mno-virt
Generate code for the Virtualization Application Specific Extension.
@@ -853,6 +859,14 @@ from the MCU Application Specific Extens
in the assembly. The @code{.set nomcu} directive prevents MCU
instructions from being accepted.
+@cindex MIPS SIMD Architecture instruction generation override
+@kindex @code{.set msa}
+@kindex @code{.set nomsa}
+The directive @code{.set msa} makes the assembler accept instructions
+from the MIPS SIMD Architecture Extension from that point on
+in the assembly. The @code{.set nomsa} directive prevents MSA
+instructions from being accepted.
+
@cindex Virtualization instruction generation override
@kindex @code{.set virt}
@kindex @code{.set novirt}
Index: gas/testsuite/gas/mips/micromips@msa-relax.d
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@msa-relax.d
diff -N gas/testsuite/gas/mips/micromips@msa-relax.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@msa-relax.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,131 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA relax
+#as: -32 -mmsa -relax-branch
+#stderr: msa-relax.l
+#source: msa-relax.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83e3 fffe bnz\.d \$w3,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8304 fffe bz\.b \$w4,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8325 fffe bz\.h \$w5,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8346 fffe bz\.w \$w6,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8367 fffe bz\.d \$w7,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 81e8 fffe bnz\.v \$w8,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8169 fffe bz\.v \$w9,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 838a fffe bnz\.b \$w10,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83ab fffe bnz\.h \$w11,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83cc fffe bnz\.w \$w12,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83ed fffe bnz\.d \$w13,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 830e fffe bz\.b \$w14,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 832f fffe bz\.h \$w15,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8350 fffe bz\.w \$w16,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8371 fffe bz\.d \$w17,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 81f2 fffe bnz\.v \$w18,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8173 fffe bz\.v \$w19,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
Index: gas/testsuite/gas/mips/micromips@msa.d
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@msa.d
diff -N gas/testsuite/gas/mips/micromips@msa.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@msa.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,787 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA instructions
+#as: -32 -mmsa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5802 081a sll\.b \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5825 20da sll\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 5848 399a sll\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 586b 525a sll\.d \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 5870 6b12 slli\.b \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 5877 7b92 slli\.b \$w14,\$w15,0x7
+[0-9a-f]+ <[^>]*> 5860 8c12 slli\.h \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 586f 9c92 slli\.h \$w18,\$w19,0xf
+[0-9a-f]+ <[^>]*> 5840 ad12 slli\.w \$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 585f bd92 slli\.w \$w22,\$w23,0x1f
+[0-9a-f]+ <[^>]*> 5800 ce12 slli\.d \$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 583f de92 slli\.d \$w26,\$w27,0x3f
+[0-9a-f]+ <[^>]*> 589e ef1a sra\.b \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 58a1 07da sra\.h \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 58c4 189a sra\.w \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 58e7 315a sra\.d \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 58f0 4a12 srai\.b \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 58f7 5a92 srai\.b \$w10,\$w11,0x7
+[0-9a-f]+ <[^>]*> 58e0 6b12 srai\.h \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 58ef 7b92 srai\.h \$w14,\$w15,0xf
+[0-9a-f]+ <[^>]*> 58c0 8c12 srai\.w \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 58df 9c92 srai\.w \$w18,\$w19,0x1f
+[0-9a-f]+ <[^>]*> 5880 ad12 srai\.d \$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 58bf bd92 srai\.d \$w22,\$w23,0x3f
+[0-9a-f]+ <[^>]*> 591a ce1a srl\.b \$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 593d e6da srl\.h \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 5940 ff9a srl\.w \$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 5963 105a srl\.d \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 5970 2912 srli\.b \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 5977 3992 srli\.b \$w6,\$w7,0x7
+[0-9a-f]+ <[^>]*> 5960 4a12 srli\.h \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 596f 5a92 srli\.h \$w10,\$w11,0xf
+[0-9a-f]+ <[^>]*> 5940 6b12 srli\.w \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 595f 7b92 srli\.w \$w14,\$w15,0x1f
+[0-9a-f]+ <[^>]*> 5900 8c12 srli\.d \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 593f 9c92 srli\.d \$w18,\$w19,0x3f
+[0-9a-f]+ <[^>]*> 5996 ad1a bclr\.b \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 59b9 c5da bclr\.h \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 59dc de9a bclr\.w \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 59ff f75a bclr\.d \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 59f0 0812 bclri\.b \$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 59f7 1892 bclri\.b \$w2,\$w3,0x7
+[0-9a-f]+ <[^>]*> 59e0 2912 bclri\.h \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 59ef 3992 bclri\.h \$w6,\$w7,0xf
+[0-9a-f]+ <[^>]*> 59c0 4a12 bclri\.w \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 59df 5a92 bclri\.w \$w10,\$w11,0x1f
+[0-9a-f]+ <[^>]*> 5980 6b12 bclri\.d \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 59bf 7b92 bclri\.d \$w14,\$w15,0x3f
+[0-9a-f]+ <[^>]*> 5a12 8c1a bset\.b \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 5a35 a4da bset\.h \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 5a58 bd9a bset\.w \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 5a7b d65a bset\.d \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 5a70 ef12 bseti\.b \$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 5a77 ff92 bseti\.b \$w30,\$w31,0x7
+[0-9a-f]+ <[^>]*> 5a60 0812 bseti\.h \$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 5a6f 1892 bseti\.h \$w2,\$w3,0xf
+[0-9a-f]+ <[^>]*> 5a40 2912 bseti\.w \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 5a5f 3992 bseti\.w \$w6,\$w7,0x1f
+[0-9a-f]+ <[^>]*> 5a00 4a12 bseti\.d \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 5a3f 5a92 bseti\.d \$w10,\$w11,0x3f
+[0-9a-f]+ <[^>]*> 5a8e 6b1a bneg\.b \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 5ab1 83da bneg\.h \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 5ad4 9c9a bneg\.w \$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 5af7 b55a bneg\.d \$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 5af0 ce12 bnegi\.b \$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 5af7 de92 bnegi\.b \$w26,\$w27,0x7
+[0-9a-f]+ <[^>]*> 5ae0 ef12 bnegi\.h \$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 5aef ff92 bnegi\.h \$w30,\$w31,0xf
+[0-9a-f]+ <[^>]*> 5ac0 0812 bnegi\.w \$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 5adf 1892 bnegi\.w \$w2,\$w3,0x1f
+[0-9a-f]+ <[^>]*> 5a80 2912 bnegi\.d \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 5abf 3992 bnegi\.d \$w6,\$w7,0x3f
+[0-9a-f]+ <[^>]*> 5b0a 4a1a binsl\.b \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 5b2d 62da binsl\.h \$w11,\$w12,\$w13
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
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+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
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+[0-9a-f]+ <[^>]*> 5b0b 106e nloc\.d \$w1,\$w2
+[0-9a-f]+ <[^>]*> 5b0c 20ee nlzc\.b \$w3,\$w4
+[0-9a-f]+ <[^>]*> 5b0d 316e nlzc\.h \$w5,\$w6
+[0-9a-f]+ <[^>]*> 5b0e 41ee nlzc\.w \$w7,\$w8
+[0-9a-f]+ <[^>]*> 5b0f 526e nlzc\.d \$w9,\$w10
+[0-9a-f]+ <[^>]*> 5880 62d6 copy_s\.b t3,\$w12\[0\]
+[0-9a-f]+ <[^>]*> 589f 7356 copy_s\.b t5,\$w14\[31\]
+[0-9a-f]+ <[^>]*> 58a0 83d6 copy_s\.h t7,\$w16\[0\]
+[0-9a-f]+ <[^>]*> 58af 9456 copy_s\.h s1,\$w18\[15\]
+[0-9a-f]+ <[^>]*> 58b0 a4d6 copy_s\.w s3,\$w20\[0\]
+[0-9a-f]+ <[^>]*> 58b7 b556 copy_s\.w s5,\$w22\[7\]
+[0-9a-f]+ <[^>]*> 58c0 e6d6 copy_u\.b k1,\$w28\[0\]
+[0-9a-f]+ <[^>]*> 58df f756 copy_u\.b sp,\$w30\[31\]
+[0-9a-f]+ <[^>]*> 58e0 07d6 copy_u\.h ra,\$w0\[0\]
+[0-9a-f]+ <[^>]*> 58ef 1056 copy_u\.h at,\$w2\[15\]
+[0-9a-f]+ <[^>]*> 58f0 20d6 copy_u\.w v1,\$w4\[0\]
+[0-9a-f]+ <[^>]*> 58f7 3156 copy_u\.w a1,\$w6\[7\]
+[0-9a-f]+ <[^>]*> 5900 62d6 insert\.b \$w11\[0\],t4
+[0-9a-f]+ <[^>]*> 591f 7356 insert\.b \$w13\[31\],t6
+[0-9a-f]+ <[^>]*> 5920 83d6 insert\.h \$w15\[0\],s0
+[0-9a-f]+ <[^>]*> 592f 9456 insert\.h \$w17\[15\],s2
+[0-9a-f]+ <[^>]*> 5930 a4d6 insert\.w \$w19\[0\],s4
+[0-9a-f]+ <[^>]*> 5937 b556 insert\.w \$w21\[7\],s6
+[0-9a-f]+ <[^>]*> 5940 e6d6 insve\.b \$w27\[0\],\$w28\[0\]
+[0-9a-f]+ <[^>]*> 595f f756 insve\.b \$w29\[31\],\$w30\[0\]
+[0-9a-f]+ <[^>]*> 5960 07d6 insve\.h \$w31\[0\],\$w0\[0\]
+[0-9a-f]+ <[^>]*> 596f 1056 insve\.h \$w1\[15\],\$w2\[0\]
+[0-9a-f]+ <[^>]*> 5970 20d6 insve\.w \$w3\[0\],\$w4\[0\]
+[0-9a-f]+ <[^>]*> 5977 3156 insve\.w \$w5\[7\],\$w6\[0\]
+[0-9a-f]+ <[^>]*> 5978 41d6 insve\.d \$w7\[0\],\$w8\[0\]
+[0-9a-f]+ <[^>]*> 597b 5256 insve\.d \$w9\[3\],\$w10\[0\]
+[0-9a-f]+ <[^>]*> 838b 8000 bnz\.b \$w11,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 838c 7fff bnz\.b \$w12,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 838d fffe bnz\.b \$w13,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 838e fffe bnz\.b \$w14,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83af 8000 bnz\.h \$w15,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83b0 7fff bnz\.h \$w16,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83b1 fffe bnz\.h \$w17,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83b2 fffe bnz\.h \$w18,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83d3 8000 bnz\.w \$w19,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83d4 7fff bnz\.w \$w20,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83d5 fffe bnz\.w \$w21,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83d6 fffe bnz\.w \$w22,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83f7 8000 bnz\.d \$w23,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83f8 7fff bnz\.d \$w24,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83f9 fffe bnz\.d \$w25,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83fa fffe bnz\.d \$w26,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 831b 8000 bz\.b \$w27,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 831c 7fff bz\.b \$w28,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 831d fffe bz\.b \$w29,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 831e fffe bz\.b \$w30,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 833f 8000 bz\.h \$w31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8320 7fff bz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8343 8000 bz\.w \$w3,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8344 7fff bz\.w \$w4,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8345 fffe bz\.w \$w5,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8346 fffe bz\.w \$w6,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8367 8000 bz\.d \$w7,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8368 7fff bz\.d \$w8,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8369 fffe bz\.d \$w9,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 836a fffe bz\.d \$w10,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5b10 02f9 ldi\.b \$w11,-512
+[0-9a-f]+ <[^>]*> 5b0f fb39 ldi\.b \$w12,511
+[0-9a-f]+ <[^>]*> 5b30 0379 ldi\.h \$w13,-512
+[0-9a-f]+ <[^>]*> 5b2f fbb9 ldi\.h \$w14,511
+[0-9a-f]+ <[^>]*> 5b50 03f9 ldi\.w \$w15,-512
+[0-9a-f]+ <[^>]*> 5b4f fc39 ldi\.w \$w16,511
+[0-9a-f]+ <[^>]*> 5b70 0479 ldi\.d \$w17,-512
+[0-9a-f]+ <[^>]*> 5b6f fcb9 ldi\.d \$w18,511
+[0-9a-f]+ <[^>]*> 5815 a4e6 fcaf\.w \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 5838 bda6 fcaf\.d \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 585b d666 fcun\.w \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 587e ef26 fcun\.d \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 5881 07e6 fceq\.w \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 58a4 18a6 fceq\.d \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 58c7 3166 fcueq\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 58ea 4a26 fcueq\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 590d 62e6 fclt\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 5930 7ba6 fclt\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 5953 9466 fcult\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 5976 ad26 fcult\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 5999 c5e6 fcle\.w \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 59bc dea6 fcle\.d \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 59df f766 fcule\.w \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 59e2 0826 fcule\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5a05 20e6 fsaf\.w \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 5a28 39a6 fsaf\.d \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 5a4b 5266 fsun\.w \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 5a6e 6b26 fsun\.d \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 5a91 83e6 fseq\.w \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 5ab4 9ca6 fseq\.d \$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 5ad7 b566 fsueq\.w \$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 5afa ce26 fsueq\.d \$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 5b1d e6e6 fslt\.w \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 5b20 ffa6 fslt\.d \$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 5b43 1066 fsult\.w \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 5b66 2926 fsult\.d \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 5b89 41e6 fsle\.w \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 5bac 5aa6 fsle\.d \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 5bcf 7366 fsule\.w \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 5bf2 8c26 fsule\.d \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 5815 a4f6 fadd\.w \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 5838 bdb6 fadd\.d \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 585b d676 fsub\.w \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 587e ef36 fsub\.d \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 5881 07f6 fmul\.w \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 58a4 18b6 fmul\.d \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 58c7 3176 fdiv\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 58ea 4a36 fdiv\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 590d 62f6 fmadd\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 5930 7bb6 fmadd\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 5953 9476 fmsub\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 5976 ad36 fmsub\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 59d9 c5f6 fexp2\.w \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 59fc deb6 fexp2\.d \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 5a1f f776 fexdo\.h \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 5a22 0836 fexdo\.w \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5a85 20f6 ftq\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 5aa8 39b6 ftq\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 5b0b 5276 fmin\.w \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 5b2e 6b36 fmin\.d \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 5b51 83f6 fmin_a\.w \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 5b74 9cb6 fmin_a\.d \$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 5b97 b576 fmax\.w \$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 5bba ce36 fmax\.d \$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 5bdd e6f6 fmax_a\.w \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 5be0 ffb6 fmax_a\.d \$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 5843 104e fcor\.w \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 5866 290e fcor\.d \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 5889 41ce fcune\.w \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 58ac 5a8e fcune\.d \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 58cf 734e fcne\.w \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 58f2 8c0e fcne\.d \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 5915 a4ce mul_q\.h \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 5938 bd8e mul_q\.w \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 595b d64e madd_q\.h \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 597e ef0e madd_q\.w \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 5981 07ce msub_q\.h \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 59a4 188e msub_q\.w \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 5a47 314e fsor\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 5a6a 4a0e fsor\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 5a8d 62ce fsune\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 5ab0 7b8e fsune\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 5ad3 944e fsne\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 5af6 ad0e fsne\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 5b19 c5ce mulr_q\.h \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 5b3c de8e mulr_q\.w \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 5b5f f74e maddr_q\.h \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 5b62 080e maddr_q\.w \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5b85 20ce msubr_q\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 5ba8 398e msubr_q\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 5b20 526e fclass\.w \$w9,\$w10
+[0-9a-f]+ <[^>]*> 5b21 62ee fclass\.d \$w11,\$w12
+[0-9a-f]+ <[^>]*> 5b22 736e ftrunc_s\.w \$w13,\$w14
+[0-9a-f]+ <[^>]*> 5b23 83ee ftrunc_s\.d \$w15,\$w16
+[0-9a-f]+ <[^>]*> 5b24 946e ftrunc_u\.w \$w17,\$w18
+[0-9a-f]+ <[^>]*> 5b25 a4ee ftrunc_u\.d \$w19,\$w20
+[0-9a-f]+ <[^>]*> 5b26 b56e fsqrt\.w \$w21,\$w22
+[0-9a-f]+ <[^>]*> 5b27 c5ee fsqrt\.d \$w23,\$w24
+[0-9a-f]+ <[^>]*> 5b28 d66e frsqrt\.w \$w25,\$w26
+[0-9a-f]+ <[^>]*> 5b29 e6ee frsqrt\.d \$w27,\$w28
+[0-9a-f]+ <[^>]*> 5b2a f76e frcp\.w \$w29,\$w30
+[0-9a-f]+ <[^>]*> 5b2b 07ee frcp\.d \$w31,\$w0
+[0-9a-f]+ <[^>]*> 5b2c 106e frint\.w \$w1,\$w2
+[0-9a-f]+ <[^>]*> 5b2d 20ee frint\.d \$w3,\$w4
+[0-9a-f]+ <[^>]*> 5b2e 316e flog2\.w \$w5,\$w6
+[0-9a-f]+ <[^>]*> 5b2f 41ee flog2\.d \$w7,\$w8
+[0-9a-f]+ <[^>]*> 5b30 526e fexupl\.w \$w9,\$w10
+[0-9a-f]+ <[^>]*> 5b31 62ee fexupl\.d \$w11,\$w12
+[0-9a-f]+ <[^>]*> 5b32 736e fexupr\.w \$w13,\$w14
+[0-9a-f]+ <[^>]*> 5b33 83ee fexupr\.d \$w15,\$w16
+[0-9a-f]+ <[^>]*> 5b34 946e ffql\.w \$w17,\$w18
+[0-9a-f]+ <[^>]*> 5b35 a4ee ffql\.d \$w19,\$w20
+[0-9a-f]+ <[^>]*> 5b36 b56e ffqr\.w \$w21,\$w22
+[0-9a-f]+ <[^>]*> 5b37 c5ee ffqr\.d \$w23,\$w24
+[0-9a-f]+ <[^>]*> 5b38 d66e ftint_s\.w \$w25,\$w26
+[0-9a-f]+ <[^>]*> 5b39 e6ee ftint_s\.d \$w27,\$w28
+[0-9a-f]+ <[^>]*> 5b3a f76e ftint_u\.w \$w29,\$w30
+[0-9a-f]+ <[^>]*> 5b3b 07ee ftint_u\.d \$w31,\$w0
+[0-9a-f]+ <[^>]*> 5b3c 106e ffint_s\.w \$w1,\$w2
+[0-9a-f]+ <[^>]*> 5b3d 20ee ffint_s\.d \$w3,\$w4
+[0-9a-f]+ <[^>]*> 5b3e 316e ffint_u\.w \$w5,\$w6
+[0-9a-f]+ <[^>]*> 5b3f 41ee ffint_u\.d \$w7,\$w8
+[0-9a-f]+ <[^>]*> 583e 4816 ctcmsa msa_ir,t1
+[0-9a-f]+ <[^>]*> 583e 5056 ctcmsa msa_csr,t2
+[0-9a-f]+ <[^>]*> 583e 5896 ctcmsa msa_access,t3
+[0-9a-f]+ <[^>]*> 583e 60d6 ctcmsa msa_save,t4
+[0-9a-f]+ <[^>]*> 587e 0356 cfcmsa t5,msa_ir
+[0-9a-f]+ <[^>]*> 587e 0b96 cfcmsa t6,msa_csr
+[0-9a-f]+ <[^>]*> 587e 13d6 cfcmsa t7,msa_access
+[0-9a-f]+ <[^>]*> 587e 1c16 cfcmsa s0,msa_save
+[0-9a-f]+ <[^>]*> 58be 9456 move\.v \$w17,\$w18
+[0-9a-f]+ <[^>]*> 02b4 9820 lsa s3,s4,s5,0x1
+[0-9a-f]+ <[^>]*> 0317 b0e0 lsa s6,s7,t8,0x4
+ \.\.\.
Index: gas/testsuite/gas/mips/micromips@msa.s
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@msa.s
diff -N gas/testsuite/gas/mips/micromips@msa.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@msa.s 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,758 @@
+ .text
+ .set noat
+ .set noreorder
+ .set nomacro
+test_msa:
+ sll.b $w0,$w1,$w2
+ sll.h $w3,$w4,$w5
+ sll.w $w6,$w7,$w8
+ sll.d $w9,$w10,$w11
+ slli.b $w12,$w13,0
+ slli.b $w14,$w15,7
+ slli.h $w16,$w17,0
+ slli.h $w18,$w19,15
+ slli.w $w20,$w21,0
+ slli.w $w22,$w23,31
+ slli.d $w24,$w25,0
+ slli.d $w26,$w27,63
+ sra.b $w28,$w29,$w30
+ sra.h $w31,$w0,$w1
+ sra.w $w2,$w3,$w4
+ sra.d $w5,$w6,$w7
+ srai.b $w8,$w9,0
+ srai.b $w10,$w11,7
+ srai.h $w12,$w13,0
+ srai.h $w14,$w15,15
+ srai.w $w16,$w17,0
+ srai.w $w18,$w19,31
+ srai.d $w20,$w21,0
+ srai.d $w22,$w23,63
+ srl.b $w24,$w25,$w26
+ srl.h $w27,$w28,$w29
+ srl.w $w30,$w31,$w0
+ srl.d $w1,$w2,$w3
+ srli.b $w4,$w5,0
+ srli.b $w6,$w7,7
+ srli.h $w8,$w9,0
+ srli.h $w10,$w11,15
+ srli.w $w12,$w13,0
+ srli.w $w14,$w15,31
+ srli.d $w16,$w17,0
+ srli.d $w18,$w19,63
+ bclr.b $w20,$w21,$w22
+ bclr.h $w23,$w24,$w25
+ bclr.w $w26,$w27,$w28
+ bclr.d $w29,$w30,$w31
+ bclri.b $w0,$w1,0
+ bclri.b $w2,$w3,7
+ bclri.h $w4,$w5,0
+ bclri.h $w6,$w7,15
+ bclri.w $w8,$w9,0
+ bclri.w $w10,$w11,31
+ bclri.d $w12,$w13,0
+ bclri.d $w14,$w15,63
+ bset.b $w16,$w17,$w18
+ bset.h $w19,$w20,$w21
+ bset.w $w22,$w23,$w24
+ bset.d $w25,$w26,$w27
+ bseti.b $w28,$w29,0
+ bseti.b $w30,$w31,7
+ bseti.h $w0,$w1,0
+ bseti.h $w2,$w3,15
+ bseti.w $w4,$w5,0
+ bseti.w $w6,$w7,31
+ bseti.d $w8,$w9,0
+ bseti.d $w10,$w11,63
+ bneg.b $w12,$w13,$w14
+ bneg.h $w15,$w16,$w17
+ bneg.w $w18,$w19,$w20
+ bneg.d $w21,$w22,$w23
+ bnegi.b $w24,$w25,0
+ bnegi.b $w26,$w27,7
+ bnegi.h $w28,$w29,0
+ bnegi.h $w30,$w31,15
+ bnegi.w $w0,$w1,0
+ bnegi.w $w2,$w3,31
+ bnegi.d $w4,$w5,0
+ bnegi.d $w6,$w7,63
+ binsl.b $w8,$w9,$w10
+ binsl.h $w11,$w12,$w13
+ binsl.w $w14,$w15,$w16
+ binsl.d $w17,$w18,$w19
+ binsli.b $w20,$w21,0
+ binsli.b $w22,$w23,7
+ binsli.h $w24,$w25,0
+ binsli.h $w26,$w27,15
+ binsli.w $w28,$w29,0
+ binsli.w $w30,$w31,31
+ binsli.d $w0,$w1,0
+ binsli.d $w2,$w3,63
+ binsr.b $w4,$w5,$w6
+ binsr.h $w7,$w8,$w9
+ binsr.w $w10,$w11,$w12
+ binsr.d $w13,$w14,$w15
+ binsri.b $w16,$w17,0
+ binsri.b $w18,$w19,7
+ binsri.h $w20,$w21,0
+ binsri.h $w22,$w23,15
+ binsri.w $w24,$w25,0
+ binsri.w $w26,$w27,31
+ binsri.d $w28,$w29,0
+ binsri.d $w30,$w31,63
+ addv.b $w0,$w1,$w2
+ addv.h $w3,$w4,$w5
+ addv.w $w6,$w7,$w8
+ addv.d $w9,$w10,$w11
+ addvi.b $w12,$w13,0
+ addvi.b $w14,$w15,31
+ addvi.h $w16,$w17,0
+ addvi.h $w18,$w19,31
+ addvi.w $w20,$w21,0
+ addvi.w $w22,$w23,31
+ addvi.d $w24,$w25,0
+ addvi.d $w26,$w27,31
+ subv.b $w28,$w29,$w30
+ subv.h $w31,$w0,$w1
+ subv.w $w2,$w3,$w4
+ subv.d $w5,$w6,$w7
+ subvi.b $w8,$w9,0
+ subvi.b $w10,$w11,31
+ subvi.h $w12,$w13,0
+ subvi.h $w14,$w15,31
+ subvi.w $w16,$w17,0
+ subvi.w $w18,$w19,31
+ subvi.d $w20,$w21,0
+ subvi.d $w22,$w23,31
+ max_s.b $w24,$w25,$w26
+ max_s.h $w27,$w28,$w29
+ max_s.w $w30,$w31,$w0
+ max_s.d $w1,$w2,$w3
+ maxi_s.b $w4,$w5,-16
+ maxi_s.b $w6,$w7,15
+ maxi_s.h $w8,$w9,-16
+ maxi_s.h $w10,$w11,15
+ maxi_s.w $w12,$w13,-16
+ maxi_s.w $w14,$w15,15
+ maxi_s.d $w16,$w17,-16
+ maxi_s.d $w18,$w19,15
+ max_u.b $w20,$w21,$w22
+ max_u.h $w23,$w24,$w25
+ max_u.w $w26,$w27,$w28
+ max_u.d $w29,$w30,$w31
+ maxi_u.b $w0,$w1,0
+ maxi_u.b $w2,$w3,31
+ maxi_u.h $w4,$w5,0
+ maxi_u.h $w6,$w7,31
+ maxi_u.w $w8,$w9,0
+ maxi_u.w $w10,$w11,31
+ maxi_u.d $w12,$w13,0
+ maxi_u.d $w14,$w15,31
+ min_s.b $w16,$w17,$w18
+ min_s.h $w19,$w20,$w21
+ min_s.w $w22,$w23,$w24
+ min_s.d $w25,$w26,$w27
+ mini_s.b $w28,$w29,-16
+ mini_s.b $w30,$w31,15
+ mini_s.h $w0,$w1,-16
+ mini_s.h $w2,$w3,15
+ mini_s.w $w4,$w5,-16
+ mini_s.w $w6,$w7,15
+ mini_s.d $w8,$w9,-16
+ mini_s.d $w10,$w11,15
+ min_u.b $w12,$w13,$w14
+ min_u.h $w15,$w16,$w17
+ min_u.w $w18,$w19,$w20
+ min_u.d $w21,$w22,$w23
+ mini_u.b $w24,$w25,0
+ mini_u.b $w26,$w27,31
+ mini_u.h $w28,$w29,0
+ mini_u.h $w30,$w31,31
+ mini_u.w $w0,$w1,0
+ mini_u.w $w2,$w3,31
+ mini_u.d $w4,$w5,0
+ mini_u.d $w6,$w7,31
+ max_a.b $w8,$w9,$w10
+ max_a.h $w11,$w12,$w13
+ max_a.w $w14,$w15,$w16
+ max_a.d $w17,$w18,$w19
+ min_a.b $w20,$w21,$w22
+ min_a.h $w23,$w24,$w25
+ min_a.w $w26,$w27,$w28
+ min_a.d $w29,$w30,$w31
+ ceq.b $w0,$w1,$w2
+ ceq.h $w3,$w4,$w5
+ ceq.w $w6,$w7,$w8
+ ceq.d $w9,$w10,$w11
+ ceqi.b $w12,$w13,-16
+ ceqi.b $w14,$w15,15
+ ceqi.h $w16,$w17,-16
+ ceqi.h $w18,$w19,15
+ ceqi.w $w20,$w21,-16
+ ceqi.w $w22,$w23,15
+ ceqi.d $w24,$w25,-16
+ ceqi.d $w26,$w27,15
+ clt_s.b $w28,$w29,$w30
+ clt_s.h $w31,$w0,$w1
+ clt_s.w $w2,$w3,$w4
+ clt_s.d $w5,$w6,$w7
+ clti_s.b $w8,$w9,-16
+ clti_s.b $w10,$w11,15
+ clti_s.h $w12,$w13,-16
+ clti_s.h $w14,$w15,15
+ clti_s.w $w16,$w17,-16
+ clti_s.w $w18,$w19,15
+ clti_s.d $w20,$w21,-16
+ clti_s.d $w22,$w23,15
+ clt_u.b $w24,$w25,$w26
+ clt_u.h $w27,$w28,$w29
+ clt_u.w $w30,$w31,$w0
+ clt_u.d $w1,$w2,$w3
+ clti_u.b $w4,$w5,0
+ clti_u.b $w6,$w7,31
+ clti_u.h $w8,$w9,0
+ clti_u.h $w10,$w11,31
+ clti_u.w $w12,$w13,0
+ clti_u.w $w14,$w15,31
+ clti_u.d $w16,$w17,0
+ clti_u.d $w18,$w19,31
+ cle_s.b $w20,$w21,$w22
+ cle_s.h $w23,$w24,$w25
+ cle_s.w $w26,$w27,$w28
+ cle_s.d $w29,$w30,$w31
+ clei_s.b $w0,$w1,-16
+ clei_s.b $w2,$w3,15
+ clei_s.h $w4,$w5,-16
+ clei_s.h $w6,$w7,15
+ clei_s.w $w8,$w9,-16
+ clei_s.w $w10,$w11,15
+ clei_s.d $w12,$w13,-16
+ clei_s.d $w14,$w15,15
+ cle_u.b $w16,$w17,$w18
+ cle_u.h $w19,$w20,$w21
+ cle_u.w $w22,$w23,$w24
+ cle_u.d $w25,$w26,$w27
+ clei_u.b $w28,$w29,0
+ clei_u.b $w30,$w31,31
+ clei_u.h $w0,$w1,0
+ clei_u.h $w2,$w3,31
+ clei_u.w $w4,$w5,0
+ clei_u.w $w6,$w7,31
+ clei_u.d $w8,$w9,0
+ clei_u.d $w10,$w11,31
+ ld.b $w12,-512($13)
+ ld.b $w14,511($15)
+ ld.h $w16,-1024($17)
+ ld.h $w18,1022($19)
+ ld.w $w20,-2048($21)
+ ld.w $w22,2044($23)
+ ld.d $w24,-4096($25)
+ ld.d $w26,4088($27)
+ st.b $w28,-512($29)
+ st.b $w30,511($31)
+ st.h $w0,-1024($1)
+ st.h $w2,1022($3)
+ st.w $w4,-2048($5)
+ st.w $w6,2044($7)
+ st.d $w8,-4096($9)
+ st.d $w10,4088($11)
+ sat_s.b $w12,$w13,0
+ sat_s.b $w14,$w15,7
+ sat_s.h $w16,$w17,0
+ sat_s.h $w18,$w19,15
+ sat_s.w $w20,$w21,0
+ sat_s.w $w22,$w23,31
+ sat_s.d $w24,$w25,0
+ sat_s.d $w26,$w27,63
+ sat_u.b $w28,$w29,0
+ sat_u.b $w30,$w31,7
+ sat_u.h $w0,$w1,0
+ sat_u.h $w2,$w3,15
+ sat_u.w $w4,$w5,0
+ sat_u.w $w6,$w7,31
+ sat_u.d $w8,$w9,0
+ sat_u.d $w10,$w11,63
+ add_a.b $w12,$w13,$w14
+ add_a.h $w15,$w16,$w17
+ add_a.w $w18,$w19,$w20
+ add_a.d $w21,$w22,$w23
+ adds_a.b $w24,$w25,$w26
+ adds_a.h $w27,$w28,$w29
+ adds_a.w $w30,$w31,$w0
+ adds_a.d $w1,$w2,$w3
+ adds_s.b $w4,$w5,$w6
+ adds_s.h $w7,$w8,$w9
+ adds_s.w $w10,$w11,$w12
+ adds_s.d $w13,$w14,$w15
+ adds_u.b $w16,$w17,$w18
+ adds_u.h $w19,$w20,$w21
+ adds_u.w $w22,$w23,$w24
+ adds_u.d $w25,$w26,$w27
+ ave_s.b $w28,$w29,$w30
+ ave_s.h $w31,$w0,$w1
+ ave_s.w $w2,$w3,$w4
+ ave_s.d $w5,$w6,$w7
+ ave_u.b $w8,$w9,$w10
+ ave_u.h $w11,$w12,$w13
+ ave_u.w $w14,$w15,$w16
+ ave_u.d $w17,$w18,$w19
+ aver_s.b $w20,$w21,$w22
+ aver_s.h $w23,$w24,$w25
+ aver_s.w $w26,$w27,$w28
+ aver_s.d $w29,$w30,$w31
+ aver_u.b $w0,$w1,$w2
+ aver_u.h $w3,$w4,$w5
+ aver_u.w $w6,$w7,$w8
+ aver_u.d $w9,$w10,$w11
+ subs_s.b $w12,$w13,$w14
+ subs_s.h $w15,$w16,$w17
+ subs_s.w $w18,$w19,$w20
+ subs_s.d $w21,$w22,$w23
+ subs_u.b $w24,$w25,$w26
+ subs_u.h $w27,$w28,$w29
+ subs_u.w $w30,$w31,$w0
+ subs_u.d $w1,$w2,$w3
+ subsus_u.b $w4,$w5,$w6
+ subsus_u.h $w7,$w8,$w9
+ subsus_u.w $w10,$w11,$w12
+ subsus_u.d $w13,$w14,$w15
+ subsuu_s.b $w16,$w17,$w18
+ subsuu_s.h $w19,$w20,$w21
+ subsuu_s.w $w22,$w23,$w24
+ subsuu_s.d $w25,$w26,$w27
+ asub_s.b $w28,$w29,$w30
+ asub_s.h $w31,$w0,$w1
+ asub_s.w $w2,$w3,$w4
+ asub_s.d $w5,$w6,$w7
+ asub_u.b $w8,$w9,$w10
+ asub_u.h $w11,$w12,$w13
+ asub_u.w $w14,$w15,$w16
+ asub_u.d $w17,$w18,$w19
+ mulv.b $w20,$w21,$w22
+ mulv.h $w23,$w24,$w25
+ mulv.w $w26,$w27,$w28
+ mulv.d $w29,$w30,$w31
+ maddv.b $w0,$w1,$w2
+ maddv.h $w3,$w4,$w5
+ maddv.w $w6,$w7,$w8
+ maddv.d $w9,$w10,$w11
+ msubv.b $w12,$w13,$w14
+ msubv.h $w15,$w16,$w17
+ msubv.w $w18,$w19,$w20
+ msubv.d $w21,$w22,$w23
+ div_s.b $w24,$w25,$w26
+ div_s.h $w27,$w28,$w29
+ div_s.w $w30,$w31,$w0
+ div_s.d $w1,$w2,$w3
+ div_u.b $w4,$w5,$w6
+ div_u.h $w7,$w8,$w9
+ div_u.w $w10,$w11,$w12
+ div_u.d $w13,$w14,$w15
+ mod_s.b $w16,$w17,$w18
+ mod_s.h $w19,$w20,$w21
+ mod_s.w $w22,$w23,$w24
+ mod_s.d $w25,$w26,$w27
+ mod_u.b $w28,$w29,$w30
+ mod_u.h $w31,$w0,$w1
+ mod_u.w $w2,$w3,$w4
+ mod_u.d $w5,$w6,$w7
+ dotp_s.h $w8,$w9,$w10
+ dotp_s.w $w11,$w12,$w13
+ dotp_s.d $w14,$w15,$w16
+ dotp_u.h $w17,$w18,$w19
+ dotp_u.w $w20,$w21,$w22
+ dotp_u.d $w23,$w24,$w25
+ dpadd_s.h $w26,$w27,$w28
+ dpadd_s.w $w29,$w30,$w31
+ dpadd_s.d $w0,$w1,$w2
+ dpadd_u.h $w3,$w4,$w5
+ dpadd_u.w $w6,$w7,$w8
+ dpadd_u.d $w9,$w10,$w11
+ dpsub_s.h $w12,$w13,$w14
+ dpsub_s.w $w15,$w16,$w17
+ dpsub_s.d $w18,$w19,$w20
+ dpsub_u.h $w21,$w22,$w23
+ dpsub_u.w $w24,$w25,$w26
+ dpsub_u.d $w27,$w28,$w29
+ sld.b $w30,$w31[$0]
+ sld.h $w1,$w2[$3]
+ sld.w $w4,$w5[$6]
+ sld.d $w7,$w8[$9]
+ sldi.b $w10,$w11[0]
+ sldi.b $w12,$w13[31]
+ sldi.h $w14,$w15[0]
+ sldi.h $w16,$w17[15]
+ sldi.w $w18,$w19[0]
+ sldi.w $w20,$w21[7]
+ sldi.d $w22,$w23[0]
+ sldi.d $w24,$w25[3]
+ splat.b $w26,$w27[$28]
+ splat.h $w29,$w30[$31]
+ splat.w $w0,$w1[$2]
+ splat.d $w3,$w4[$5]
+ splati.b $w6,$w7[0]
+ splati.b $w8,$w9[31]
+ splati.h $w10,$w11[0]
+ splati.h $w12,$w13[15]
+ splati.w $w14,$w15[0]
+ splati.w $w16,$w17[7]
+ splati.d $w18,$w19[0]
+ splati.d $w20,$w21[3]
+ pckev.b $w22,$w23,$w24
+ pckev.h $w25,$w26,$w27
+ pckev.w $w28,$w29,$w30
+ pckev.d $w31,$w0,$w1
+ pckod.b $w2,$w3,$w4
+ pckod.h $w5,$w6,$w7
+ pckod.w $w8,$w9,$w10
+ pckod.d $w11,$w12,$w13
+ ilvl.b $w14,$w15,$w16
+ ilvl.h $w17,$w18,$w19
+ ilvl.w $w20,$w21,$w22
+ ilvl.d $w23,$w24,$w25
+ ilvr.b $w26,$w27,$w28
+ ilvr.h $w29,$w30,$w31
+ ilvr.w $w0,$w1,$w2
+ ilvr.d $w3,$w4,$w5
+ ilvev.b $w6,$w7,$w8
+ ilvev.h $w9,$w10,$w11
+ ilvev.w $w12,$w13,$w14
+ ilvev.d $w15,$w16,$w17
+ ilvod.b $w18,$w19,$w20
+ ilvod.h $w21,$w22,$w23
+ ilvod.w $w24,$w25,$w26
+ ilvod.d $w27,$w28,$w29
+ vshf.b $w30,$w31,$w0
+ vshf.h $w1,$w2,$w3
+ vshf.w $w4,$w5,$w6
+ vshf.d $w7,$w8,$w9
+ srar.b $w10,$w11,$w12
+ srar.h $w13,$w14,$w15
+ srar.w $w16,$w17,$w18
+ srar.d $w19,$w20,$w21
+ srari.b $w22,$w23,0
+ srari.b $w24,$w25,7
+ srari.h $w26,$w27,0
+ srari.h $w28,$w29,15
+ srari.w $w30,$w31,0
+ srari.w $w0,$w1,31
+ srari.d $w2,$w3,0
+ srari.d $w4,$w5,63
+ srlr.b $w6,$w7,$w8
+ srlr.h $w9,$w10,$w11
+ srlr.w $w12,$w13,$w14
+ srlr.d $w15,$w16,$w17
+ srlri.b $w18,$w19,0
+ srlri.b $w20,$w21,7
+ srlri.h $w22,$w23,0
+ srlri.h $w24,$w25,15
+ srlri.w $w26,$w27,0
+ srlri.w $w28,$w29,31
+ srlri.d $w30,$w31,0
+ srlri.d $w0,$w1,63
+ hadd_s.h $w2,$w3,$w4
+ hadd_s.w $w5,$w6,$w7
+ hadd_s.d $w8,$w9,$w10
+ hadd_u.h $w11,$w12,$w13
+ hadd_u.w $w14,$w15,$w16
+ hadd_u.d $w17,$w18,$w19
+ hsub_s.h $w20,$w21,$w22
+ hsub_s.w $w23,$w24,$w25
+ hsub_s.d $w26,$w27,$w28
+ hsub_u.h $w29,$w30,$w31
+ hsub_u.w $w0,$w1,$w2
+ hsub_u.d $w3,$w4,$w5
+ and.v $w6,$w7,$w8
+ andi.b $w9,$w10,0
+ andi.b $w11,$w12,255
+ or.v $w13,$w14,$w15
+ ori.b $w16,$w17,0
+ ori.b $w18,$w19,255
+ nor.v $w20,$w21,$w22
+ nori.b $w23,$w24,0
+ nori.b $w25,$w26,255
+ xor.v $w27,$w28,$w29
+ xori.b $w30,$w31,0
+ xori.b $w0,$w1,255
+ bmnz.v $w2,$w3,$w4
+ bmnzi.b $w5,$w6,0
+ bmnzi.b $w7,$w8,255
+ bmz.v $w9,$w10,$w11
+ bmzi.b $w12,$w13,0
+ bmzi.b $w14,$w15,255
+ bsel.v $w16,$w17,$w18
+ bseli.b $w19,$w20,0
+ bseli.b $w21,$w22,255
+ shf.b $w23,$w24,0
+ shf.b $w25,$w26,255
+ shf.h $w27,$w28,0
+ shf.h $w29,$w30,255
+ shf.w $w31,$w0,0
+ shf.w $w1,$w2,255
+1:
+ bnz.v $w3,. + 4 + (-32768 << 1)
+ nop
+ bnz.v $w4,. + 4 + (32767 << 1)
+ nop
+ bnz.v $w5,1b
+ nop
+ bnz.v $w6,external_label
+ nop
+1:
+ bz.v $w7,. + 4 + (-32768 << 1)
+ nop
+ bz.v $w8,. + 4 + (32767 << 1)
+ nop
+ bz.v $w9,1b
+ nop
+ bz.v $w10,external_label
+ nop
+ fill.b $w11,$12
+ fill.h $w13,$14
+ fill.w $w15,$16
+ pcnt.b $w19,$w20
+ pcnt.h $w21,$w22
+ pcnt.w $w23,$w24
+ pcnt.d $w25,$w26
+ nloc.b $w27,$w28
+ nloc.h $w29,$w30
+ nloc.w $w31,$w0
+ nloc.d $w1,$w2
+ nlzc.b $w3,$w4
+ nlzc.h $w5,$w6
+ nlzc.w $w7,$w8
+ nlzc.d $w9,$w10
+ copy_s.b $11,$w12[0]
+ copy_s.b $13,$w14[31]
+ copy_s.h $15,$w16[0]
+ copy_s.h $17,$w18[15]
+ copy_s.w $19,$w20[0]
+ copy_s.w $21,$w22[7]
+ copy_u.b $27,$w28[0]
+ copy_u.b $29,$w30[31]
+ copy_u.h $31,$w0[0]
+ copy_u.h $1,$w2[15]
+ copy_u.w $3,$w4[0]
+ copy_u.w $5,$w6[7]
+ insert.b $w11[0],$12
+ insert.b $w13[31],$14
+ insert.h $w15[0],$16
+ insert.h $w17[15],$18
+ insert.w $w19[0],$20
+ insert.w $w21[7],$22
+ insve.b $w27[0],$w28[0]
+ insve.b $w29[31],$w30[0]
+ insve.h $w31[0],$w0[0]
+ insve.h $w1[15],$w2[0]
+ insve.w $w3[0],$w4[0]
+ insve.w $w5[7],$w6[0]
+ insve.d $w7[0],$w8[0]
+ insve.d $w9[3],$w10[0]
+1:
+ bnz.b $w11,. + 4 + (-32768 << 1)
+ nop
+ bnz.b $w12,. + 4 + (32767 << 1)
+ nop
+ bnz.b $w13,1b
+ nop
+ bnz.b $w14,external_label
+ nop
+1:
+ bnz.h $w15,. + 4 + (-32768 << 1)
+ nop
+ bnz.h $w16,. + 4 + (32767 << 1)
+ nop
+ bnz.h $w17,1b
+ nop
+ bnz.h $w18,external_label
+ nop
+1:
+ bnz.w $w19,. + 4 + (-32768 << 1)
+ nop
+ bnz.w $w20,. + 4 + (32767 << 1)
+ nop
+ bnz.w $w21,1b
+ nop
+ bnz.w $w22,external_label
+ nop
+1:
+ bnz.d $w23,. + 4 + (-32768 << 1)
+ nop
+ bnz.d $w24,. + 4 + (32767 << 1)
+ nop
+ bnz.d $w25,1b
+ nop
+ bnz.d $w26,external_label
+ nop
+1:
+ bz.b $w27,. + 4 + (-32768 << 1)
+ nop
+ bz.b $w28,. + 4 + (32767 << 1)
+ nop
+ bz.b $w29,1b
+ nop
+ bz.b $w30,external_label
+ nop
+1:
+ bz.h $w31,. + 4 + (-32768 << 1)
+ nop
+ bz.h $w0,. + 4 + (32767 << 1)
+ nop
+ bz.h $w1,1b
+ nop
+ bz.h $w2,external_label
+ nop
+1:
+ bz.w $w3,. + 4 + (-32768 << 1)
+ nop
+ bz.w $w4,. + 4 + (32767 << 1)
+ nop
+ bz.w $w5,1b
+ nop
+ bz.w $w6,external_label
+ nop
+1:
+ bz.d $w7,. + 4 + (-32768 << 1)
+ nop
+ bz.d $w8,. + 4 + (32767 << 1)
+ nop
+ bz.d $w9,1b
+ nop
+ bz.d $w10,external_label
+ nop
+ ldi.b $w11,-512
+ ldi.b $w12,511
+ ldi.h $w13,-512
+ ldi.h $w14,511
+ ldi.w $w15,-512
+ ldi.w $w16,511
+ ldi.d $w17,-512
+ ldi.d $w18,511
+ fcaf.w $w19,$w20,$w21
+ fcaf.d $w22,$w23,$w24
+ fcun.w $w25,$w26,$w27
+ fcun.d $w28,$w29,$w30
+ fceq.w $w31,$w0,$w1
+ fceq.d $w2,$w3,$w4
+ fcueq.w $w5,$w6,$w7
+ fcueq.d $w8,$w9,$w10
+ fclt.w $w11,$w12,$w13
+ fclt.d $w14,$w15,$w16
+ fcult.w $w17,$w18,$w19
+ fcult.d $w20,$w21,$w22
+ fcle.w $w23,$w24,$w25
+ fcle.d $w26,$w27,$w28
+ fcule.w $w29,$w30,$w31
+ fcule.d $w0,$w1,$w2
+ fsaf.w $w3,$w4,$w5
+ fsaf.d $w6,$w7,$w8
+ fsun.w $w9,$w10,$w11
+ fsun.d $w12,$w13,$w14
+ fseq.w $w15,$w16,$w17
+ fseq.d $w18,$w19,$w20
+ fsueq.w $w21,$w22,$w23
+ fsueq.d $w24,$w25,$w26
+ fslt.w $w27,$w28,$w29
+ fslt.d $w30,$w31,$w0
+ fsult.w $w1,$w2,$w3
+ fsult.d $w4,$w5,$w6
+ fsle.w $w7,$w8,$w9
+ fsle.d $w10,$w11,$w12
+ fsule.w $w13,$w14,$w15
+ fsule.d $w16,$w17,$w18
+ fadd.w $w19,$w20,$w21
+ fadd.d $w22,$w23,$w24
+ fsub.w $w25,$w26,$w27
+ fsub.d $w28,$w29,$w30
+ fmul.w $w31,$w0,$w1
+ fmul.d $w2,$w3,$w4
+ fdiv.w $w5,$w6,$w7
+ fdiv.d $w8,$w9,$w10
+ fmadd.w $w11,$w12,$w13
+ fmadd.d $w14,$w15,$w16
+ fmsub.w $w17,$w18,$w19
+ fmsub.d $w20,$w21,$w22
+ fexp2.w $w23,$w24,$w25
+ fexp2.d $w26,$w27,$w28
+ fexdo.h $w29,$w30,$w31
+ fexdo.w $w0,$w1,$w2
+ ftq.h $w3,$w4,$w5
+ ftq.w $w6,$w7,$w8
+ fmin.w $w9,$w10,$w11
+ fmin.d $w12,$w13,$w14
+ fmin_a.w $w15,$w16,$w17
+ fmin_a.d $w18,$w19,$w20
+ fmax.w $w21,$w22,$w23
+ fmax.d $w24,$w25,$w26
+ fmax_a.w $w27,$w28,$w29
+ fmax_a.d $w30,$w31,$w0
+ fcor.w $w1,$w2,$w3
+ fcor.d $w4,$w5,$w6
+ fcune.w $w7,$w8,$w9
+ fcune.d $w10,$w11,$w12
+ fcne.w $w13,$w14,$w15
+ fcne.d $w16,$w17,$w18
+ mul_q.h $w19,$w20,$w21
+ mul_q.w $w22,$w23,$w24
+ madd_q.h $w25,$w26,$w27
+ madd_q.w $w28,$w29,$w30
+ msub_q.h $w31,$w0,$w1
+ msub_q.w $w2,$w3,$w4
+ fsor.w $w5,$w6,$w7
+ fsor.d $w8,$w9,$w10
+ fsune.w $w11,$w12,$w13
+ fsune.d $w14,$w15,$w16
+ fsne.w $w17,$w18,$w19
+ fsne.d $w20,$w21,$w22
+ mulr_q.h $w23,$w24,$w25
+ mulr_q.w $w26,$w27,$w28
+ maddr_q.h $w29,$w30,$w31
+ maddr_q.w $w0,$w1,$w2
+ msubr_q.h $w3,$w4,$w5
+ msubr_q.w $w6,$w7,$w8
+ fclass.w $w9,$w10
+ fclass.d $w11,$w12
+ ftrunc_s.w $w13,$w14
+ ftrunc_s.d $w15,$w16
+ ftrunc_u.w $w17,$w18
+ ftrunc_u.d $w19,$w20
+ fsqrt.w $w21,$w22
+ fsqrt.d $w23,$w24
+ frsqrt.w $w25,$w26
+ frsqrt.d $w27,$w28
+ frcp.w $w29,$w30
+ frcp.d $w31,$w0
+ frint.w $w1,$w2
+ frint.d $w3,$w4
+ flog2.w $w5,$w6
+ flog2.d $w7,$w8
+ fexupl.w $w9,$w10
+ fexupl.d $w11,$w12
+ fexupr.w $w13,$w14
+ fexupr.d $w15,$w16
+ ffql.w $w17,$w18
+ ffql.d $w19,$w20
+ ffqr.w $w21,$w22
+ ffqr.d $w23,$w24
+ ftint_s.w $w25,$w26
+ ftint_s.d $w27,$w28
+ ftint_u.w $w29,$w30
+ ftint_u.d $w31,$w0
+ ffint_s.w $w1,$w2
+ ffint_s.d $w3,$w4
+ ffint_u.w $w5,$w6
+ ffint_u.d $w7,$w8
+ ctcmsa $0,$9
+ ctcmsa $1,$10
+ ctcmsa $2,$11
+ ctcmsa $3,$12
+ cfcmsa $13,$0
+ cfcmsa $14,$1
+ cfcmsa $15,$2
+ cfcmsa $16,$3
+ move.v $w17,$w18
+ lsa $19,$20,$21,1
+ lsa $22,$23,$24,4
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
Index: gas/testsuite/gas/mips/micromips@msa64.d
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@msa64.d
diff -N gas/testsuite/gas/mips/micromips@msa64.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@msa64.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,18 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA64 instructions
+#source: msa64.s
+#as: -64 -mmsa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5b03 946e fill\.d \$w17,s2
+[0-9a-f]+ <[^>]*> 58b8 c5d6 copy_s\.d s7,\$w24\[0\]
+[0-9a-f]+ <[^>]*> 58bb d656 copy_s\.d t9,\$w26\[3\]
+[0-9a-f]+ <[^>]*> 58f8 41d6 copy_u\.d a3,\$w8\[0\]
+[0-9a-f]+ <[^>]*> 58fb 5256 copy_u\.d a5,\$w10\[3\]
+[0-9a-f]+ <[^>]*> 5938 c5d6 insert\.d \$w23\[0\],t8
+[0-9a-f]+ <[^>]*> 593b d656 insert\.d \$w25\[3\],k0
+[0-9a-f]+ <[^>]*> 5b7a c820 dlsa t9,k0,k1,0x1
+[0-9a-f]+ <[^>]*> 5bdd e0e0 dlsa gp,sp,s8,0x4
+ \.\.\.
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.234
diff -u -p -r1.234 mips.exp
--- gas/testsuite/gas/mips/mips.exp 12 Sep 2013 21:45:04 -0000 1.234
+++ gas/testsuite/gas/mips/mips.exp 9 Oct 2013 23:42:54 -0000
@@ -1147,4 +1147,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "l_d-reloc"
run_list_test "bltzal"
+
+ run_dump_test_arches "msa" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2]
+ run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2]
}
Index: gas/testsuite/gas/mips/msa-relax.d
===================================================================
RCS file: gas/testsuite/gas/mips/msa-relax.d
diff -N gas/testsuite/gas/mips/msa-relax.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa-relax.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,110 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA relax
+#as: -32 -mmsa -relax-branch
+#stderr: msa-relax.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 47800002 bnz\.b \$w0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47a10002 bnz\.h \$w1,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47c20002 bnz\.w \$w2,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47e30002 bnz\.d \$w3,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47040002 bz\.b \$w4,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47250002 bz\.h \$w5,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47460002 bz\.w \$w6,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47670002 bz\.d \$w7,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e80002 bnz\.v \$w8,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45690002 bz\.v \$w9,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 478a0002 bnz\.b \$w10,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47ab0002 bnz\.h \$w11,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47cc0002 bnz\.w \$w12,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47ed0002 bnz\.d \$w13,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 470e0002 bz\.b \$w14,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 472f0002 bz\.h \$w15,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47500002 bz\.w \$w16,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47710002 bz\.d \$w17,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45f20002 bnz\.v \$w18,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45730002 bz\.v \$w19,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_26 \.text
+[0-9a-f]+ <[^>]*> 00000000 nop
+ \.\.\.
Index: gas/testsuite/gas/mips/msa-relax.l
===================================================================
RCS file: gas/testsuite/gas/mips/msa-relax.l
diff -N gas/testsuite/gas/mips/msa-relax.l
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa-relax.l 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*:3: Warning: relaxed out-of-range branch into a jump
+.*:4: Warning: relaxed out-of-range branch into a jump
+.*:5: Warning: relaxed out-of-range branch into a jump
+.*:6: Warning: relaxed out-of-range branch into a jump
+.*:7: Warning: relaxed out-of-range branch into a jump
+.*:8: Warning: relaxed out-of-range branch into a jump
+.*:9: Warning: relaxed out-of-range branch into a jump
+.*:10: Warning: relaxed out-of-range branch into a jump
+.*:11: Warning: relaxed out-of-range branch into a jump
+.*:12: Warning: relaxed out-of-range branch into a jump
+.*:16: Warning: relaxed out-of-range branch into a jump
+.*:17: Warning: relaxed out-of-range branch into a jump
+.*:18: Warning: relaxed out-of-range branch into a jump
+.*:19: Warning: relaxed out-of-range branch into a jump
+.*:20: Warning: relaxed out-of-range branch into a jump
+.*:21: Warning: relaxed out-of-range branch into a jump
+.*:22: Warning: relaxed out-of-range branch into a jump
+.*:23: Warning: relaxed out-of-range branch into a jump
+.*:24: Warning: relaxed out-of-range branch into a jump
+.*:25: Warning: relaxed out-of-range branch into a jump
Index: gas/testsuite/gas/mips/msa-relax.s
===================================================================
RCS file: gas/testsuite/gas/mips/msa-relax.s
diff -N gas/testsuite/gas/mips/msa-relax.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa-relax.s 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,29 @@
+ .text
+foo:
+ bz.b $w0, bar
+ bz.h $w1, bar
+ bz.w $w2, bar
+ bz.d $w3, bar
+ bnz.b $w4, bar
+ bnz.h $w5, bar
+ bnz.w $w6, bar
+ bnz.d $w7, bar
+ bz.v $w8, bar
+ bnz.v $w9, bar
+
+ .space 0x20000 # to make a 128kb loop body
+bar:
+ bz.b $w10, foo
+ bz.h $w11, foo
+ bz.w $w12, foo
+ bz.d $w13, foo
+ bnz.b $w14, foo
+ bnz.h $w15, foo
+ bnz.w $w16, foo
+ bnz.d $w17, foo
+ bz.v $w18, foo
+ bnz.v $w19, foo
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
Index: gas/testsuite/gas/mips/msa.d
===================================================================
RCS file: gas/testsuite/gas/mips/msa.d
diff -N gas/testsuite/gas/mips/msa.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,757 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA instructions
+#as: -32 -mmsa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7802080d sll\.b \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 782520cd sll\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7848398d sll\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 786b524d sll\.d \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 78706b09 slli\.b \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 78777b89 slli\.b \$w14,\$w15,0x7
+[0-9a-f]+ <[^>]*> 78608c09 slli\.h \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 786f9c89 slli\.h \$w18,\$w19,0xf
+[0-9a-f]+ <[^>]*> 7840ad09 slli\.w \$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 785fbd89 slli\.w \$w22,\$w23,0x1f
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+[0-9a-f]+ <[^>]*> 783fde89 slli\.d \$w26,\$w27,0x3f
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+[0-9a-f]+ <[^>]*> 78a107cd sra\.h \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78c4188d sra\.w \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78e7314d sra\.d \$w5,\$w6,\$w7
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+[0-9a-f]+ <[^>]*> 78c08c09 srai\.w \$w16,\$w17,0x0
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+[0-9a-f]+ <[^>]*> 7880ad09 srai\.d \$w20,\$w21,0x0
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+[0-9a-f]+ <[^>]*> 793de6cd srl\.h \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7940ff8d srl\.w \$w30,\$w31,\$w0
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+[0-9a-f]+ <[^>]*> 79702909 srli\.b \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 79773989 srli\.b \$w6,\$w7,0x7
+[0-9a-f]+ <[^>]*> 79604a09 srli\.h \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 796f5a89 srli\.h \$w10,\$w11,0xf
+[0-9a-f]+ <[^>]*> 79406b09 srli\.w \$w12,\$w13,0x0
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+[0-9a-f]+ <[^>]*> 793f9c89 srli\.d \$w18,\$w19,0x3f
+[0-9a-f]+ <[^>]*> 7996ad0d bclr\.b \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 79b9c5cd bclr\.h \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79dcde8d bclr\.w \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 79fff74d bclr\.d \$w29,\$w30,\$w31
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+[0-9a-f]+ <[^>]*> 79e02909 bclri\.h \$w4,\$w5,0x0
+[0-9a-f]+ <[^>]*> 79ef3989 bclri\.h \$w6,\$w7,0xf
+[0-9a-f]+ <[^>]*> 79c04a09 bclri\.w \$w8,\$w9,0x0
+[0-9a-f]+ <[^>]*> 79df5a89 bclri\.w \$w10,\$w11,0x1f
+[0-9a-f]+ <[^>]*> 79806b09 bclri\.d \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 79bf7b89 bclri\.d \$w14,\$w15,0x3f
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+[0-9a-f]+ <[^>]*> 7a6f1889 bseti\.h \$w2,\$w3,0xf
+[0-9a-f]+ <[^>]*> 7a402909 bseti\.w \$w4,\$w5,0x0
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+[0-9a-f]+ <[^>]*> 7a004a09 bseti\.d \$w8,\$w9,0x0
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+[0-9a-f]+ <[^>]*> 7ad49c8d bneg\.w \$w18,\$w19,\$w20
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+[0-9a-f]+ <[^>]*> 7ae0ef09 bnegi\.h \$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7aefff89 bnegi\.h \$w30,\$w31,0xf
+[0-9a-f]+ <[^>]*> 7ac00809 bnegi\.w \$w0,\$w1,0x0
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+[0-9a-f]+ <[^>]*> 7b0a4a0d binsl\.b \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b2d62cd binsl\.h \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7b507b8d binsl\.w \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b73944d binsl\.d \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b70ad09 binsli\.b \$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 7b77bd89 binsli\.b \$w22,\$w23,0x7
+[0-9a-f]+ <[^>]*> 7b60ce09 binsli\.h \$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 7b6fde89 binsli\.h \$w26,\$w27,0xf
+[0-9a-f]+ <[^>]*> 7b40ef09 binsli\.w \$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7b5fff89 binsli\.w \$w30,\$w31,0x1f
+[0-9a-f]+ <[^>]*> 7b000809 binsli\.d \$w0,\$w1,0x0
+[0-9a-f]+ <[^>]*> 7b3f1889 binsli\.d \$w2,\$w3,0x3f
+[0-9a-f]+ <[^>]*> 7b86290d binsr\.b \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7ba941cd binsr\.h \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 7bcc5a8d binsr\.w \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7bef734d binsr\.d \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 7bf08c09 binsri\.b \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 7bf79c89 binsri\.b \$w18,\$w19,0x7
+[0-9a-f]+ <[^>]*> 7be0ad09 binsri\.h \$w20,\$w21,0x0
+[0-9a-f]+ <[^>]*> 7befbd89 binsri\.h \$w22,\$w23,0xf
+[0-9a-f]+ <[^>]*> 7bc0ce09 binsri\.w \$w24,\$w25,0x0
+[0-9a-f]+ <[^>]*> 7bdfde89 binsri\.w \$w26,\$w27,0x1f
+[0-9a-f]+ <[^>]*> 7b80ef09 binsri\.d \$w28,\$w29,0x0
+[0-9a-f]+ <[^>]*> 7bbfff89 binsri\.d \$w30,\$w31,0x3f
+[0-9a-f]+ <[^>]*> 7802080e addv\.b \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 782520ce addv\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7848398e addv\.w \$w6,\$w7,\$w8
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+[0-9a-f]+ <[^>]*> 78006b06 addvi\.b \$w12,\$w13,0
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+[0-9a-f]+ <[^>]*> 78208c06 addvi\.h \$w16,\$w17,0
+[0-9a-f]+ <[^>]*> 783f9c86 addvi\.h \$w18,\$w19,31
+[0-9a-f]+ <[^>]*> 7840ad06 addvi\.w \$w20,\$w21,0
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+[0-9a-f]+ <[^>]*> 787fde86 addvi\.d \$w26,\$w27,31
+[0-9a-f]+ <[^>]*> 789eef0e subv\.b \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 78a107ce subv\.h \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78c4188e subv\.w \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78e7314e subv\.d \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78804a06 subvi\.b \$w8,\$w9,0
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+[0-9a-f]+ <[^>]*> 78a06b06 subvi\.h \$w12,\$w13,0
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+[0-9a-f]+ <[^>]*> 78c08c06 subvi\.w \$w16,\$w17,0
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+[0-9a-f]+ <[^>]*> 78e0ad06 subvi\.d \$w20,\$w21,0
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+[0-9a-f]+ <[^>]*> 7940ff8e max_s\.w \$w30,\$w31,\$w0
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+[0-9a-f]+ <[^>]*> 79304a06 maxi_s\.h \$w8,\$w9,-16
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+[0-9a-f]+ <[^>]*> 7b96ad0e min_a\.b \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7bb9c5ce min_a\.h \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7bdcde8e min_a\.w \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7bfff74e min_a\.d \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7802080f ceq\.b \$w0,\$w1,\$w2
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+[0-9a-f]+ <[^>]*> 791eef0f clt_s\.b \$w28,\$w29,\$w30
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+[0-9a-f]+ <[^>]*> 79508c07 clti_s\.w \$w16,\$w17,-16
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+[0-9a-f]+ <[^>]*> 7b128c12 mod_s\.b \$w16,\$w17,\$w18
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+[0-9a-f]+ <[^>]*> 78231055 vshf\.h \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 78462915 vshf\.w \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 786941d5 vshf\.d \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 788c5a95 srar\.b \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 78af7355 srar\.h \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 78d28c15 srar\.w \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 78f5a4d5 srar\.d \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7970bd8a srari\.b \$w22,\$w23,0x0
+[0-9a-f]+ <[^>]*> 7977ce0a srari\.b \$w24,\$w25,0x7
+[0-9a-f]+ <[^>]*> 7960de8a srari\.h \$w26,\$w27,0x0
+[0-9a-f]+ <[^>]*> 796fef0a srari\.h \$w28,\$w29,0xf
+[0-9a-f]+ <[^>]*> 7940ff8a srari\.w \$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 795f080a srari\.w \$w0,\$w1,0x1f
+[0-9a-f]+ <[^>]*> 7900188a srari\.d \$w2,\$w3,0x0
+[0-9a-f]+ <[^>]*> 793f290a srari\.d \$w4,\$w5,0x3f
+[0-9a-f]+ <[^>]*> 79083995 srlr\.b \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 792b5255 srlr\.h \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 794e6b15 srlr\.w \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 797183d5 srlr\.d \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 79f09c8a srlri\.b \$w18,\$w19,0x0
+[0-9a-f]+ <[^>]*> 79f7ad0a srlri\.b \$w20,\$w21,0x7
+[0-9a-f]+ <[^>]*> 79e0bd8a srlri\.h \$w22,\$w23,0x0
+[0-9a-f]+ <[^>]*> 79efce0a srlri\.h \$w24,\$w25,0xf
+[0-9a-f]+ <[^>]*> 79c0de8a srlri\.w \$w26,\$w27,0x0
+[0-9a-f]+ <[^>]*> 79dfef0a srlri\.w \$w28,\$w29,0x1f
+[0-9a-f]+ <[^>]*> 7980ff8a srlri\.d \$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 79bf080a srlri\.d \$w0,\$w1,0x3f
+[0-9a-f]+ <[^>]*> 7a241895 hadd_s\.h \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a473155 hadd_s\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a6a4a15 hadd_s\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7aad62d5 hadd_u\.h \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ad07b95 hadd_u\.w \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7af39455 hadd_u\.d \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7b36ad15 hsub_s\.h \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b59c5d5 hsub_s\.w \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7b7cde95 hsub_s\.d \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7bbff755 hsub_u\.h \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7bc20815 hsub_u\.w \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7be520d5 hsub_u\.d \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7808399e and\.v \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 78005240 andi\.b \$w9,\$w10,0x0
+[0-9a-f]+ <[^>]*> 78ff62c0 andi\.b \$w11,\$w12,0xff
+[0-9a-f]+ <[^>]*> 782f735e or\.v \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 79008c00 ori\.b \$w16,\$w17,0x0
+[0-9a-f]+ <[^>]*> 79ff9c80 ori\.b \$w18,\$w19,0xff
+[0-9a-f]+ <[^>]*> 7856ad1e nor\.v \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7a00c5c0 nori\.b \$w23,\$w24,0x0
+[0-9a-f]+ <[^>]*> 7affd640 nori\.b \$w25,\$w26,0xff
+[0-9a-f]+ <[^>]*> 787de6de xor\.v \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7b00ff80 xori\.b \$w30,\$w31,0x0
+[0-9a-f]+ <[^>]*> 7bff0800 xori\.b \$w0,\$w1,0xff
+[0-9a-f]+ <[^>]*> 7884189e bmnz\.v \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78003141 bmnzi\.b \$w5,\$w6,0x0
+[0-9a-f]+ <[^>]*> 78ff41c1 bmnzi\.b \$w7,\$w8,0xff
+[0-9a-f]+ <[^>]*> 78ab525e bmz\.v \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 79006b01 bmzi\.b \$w12,\$w13,0x0
+[0-9a-f]+ <[^>]*> 79ff7b81 bmzi\.b \$w14,\$w15,0xff
+[0-9a-f]+ <[^>]*> 78d28c1e bsel\.v \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7a00a4c1 bseli\.b \$w19,\$w20,0x0
+[0-9a-f]+ <[^>]*> 7affb541 bseli\.b \$w21,\$w22,0xff
+[0-9a-f]+ <[^>]*> 7800c5c2 shf\.b \$w23,\$w24,0x0
+[0-9a-f]+ <[^>]*> 78ffd642 shf\.b \$w25,\$w26,0xff
+[0-9a-f]+ <[^>]*> 7900e6c2 shf\.h \$w27,\$w28,0x0
+[0-9a-f]+ <[^>]*> 79fff742 shf\.h \$w29,\$w30,0xff
+[0-9a-f]+ <[^>]*> 7a0007c2 shf\.w \$w31,\$w0,0x0
+[0-9a-f]+ <[^>]*> 7aff1042 shf\.w \$w1,\$w2,0xff
+[0-9a-f]+ <[^>]*> 45e38000 bnz\.v \$w3,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e47fff bnz\.v \$w4,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e5fffb bnz\.v \$w5,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e6ffff bnz\.v \$w6,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45678000 bz\.v \$w7,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45687fff bz\.v \$w8,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4569fffb bz\.v \$w9,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 456affff bz\.v \$w10,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 7b0062de fill\.b \$w11,t4
+[0-9a-f]+ <[^>]*> 7b01735e fill\.h \$w13,t6
+[0-9a-f]+ <[^>]*> 7b0283de fill\.w \$w15,s0
+[0-9a-f]+ <[^>]*> 7b04a4de pcnt\.b \$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b05b55e pcnt\.h \$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b06c5de pcnt\.w \$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b07d65e pcnt\.d \$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b08e6de nloc\.b \$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b09f75e nloc\.h \$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b0a07de nloc\.w \$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b0b105e nloc\.d \$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b0c20de nlzc\.b \$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b0d315e nlzc\.h \$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b0e41de nlzc\.w \$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b0f525e nlzc\.d \$w9,\$w10
+[0-9a-f]+ <[^>]*> 788062d9 copy_s\.b t3,\$w12\[0\]
+[0-9a-f]+ <[^>]*> 789f7359 copy_s\.b t5,\$w14\[31\]
+[0-9a-f]+ <[^>]*> 78a083d9 copy_s\.h t7,\$w16\[0\]
+[0-9a-f]+ <[^>]*> 78af9459 copy_s\.h s1,\$w18\[15\]
+[0-9a-f]+ <[^>]*> 78b0a4d9 copy_s\.w s3,\$w20\[0\]
+[0-9a-f]+ <[^>]*> 78b7b559 copy_s\.w s5,\$w22\[7\]
+[0-9a-f]+ <[^>]*> 78c0e6d9 copy_u\.b k1,\$w28\[0\]
+[0-9a-f]+ <[^>]*> 78dff759 copy_u\.b sp,\$w30\[31\]
+[0-9a-f]+ <[^>]*> 78e007d9 copy_u\.h ra,\$w0\[0\]
+[0-9a-f]+ <[^>]*> 78ef1059 copy_u\.h at,\$w2\[15\]
+[0-9a-f]+ <[^>]*> 78f020d9 copy_u\.w v1,\$w4\[0\]
+[0-9a-f]+ <[^>]*> 78f73159 copy_u\.w a1,\$w6\[7\]
+[0-9a-f]+ <[^>]*> 790062d9 insert\.b \$w11\[0\],t4
+[0-9a-f]+ <[^>]*> 791f7359 insert\.b \$w13\[31\],t6
+[0-9a-f]+ <[^>]*> 792083d9 insert\.h \$w15\[0\],s0
+[0-9a-f]+ <[^>]*> 792f9459 insert\.h \$w17\[15\],s2
+[0-9a-f]+ <[^>]*> 7930a4d9 insert\.w \$w19\[0\],s4
+[0-9a-f]+ <[^>]*> 7937b559 insert\.w \$w21\[7\],s6
+[0-9a-f]+ <[^>]*> 7940e6d9 insve\.b \$w27\[0\],\$w28\[0\]
+[0-9a-f]+ <[^>]*> 795ff759 insve\.b \$w29\[31\],\$w30\[0\]
+[0-9a-f]+ <[^>]*> 796007d9 insve\.h \$w31\[0\],\$w0\[0\]
+[0-9a-f]+ <[^>]*> 796f1059 insve\.h \$w1\[15\],\$w2\[0\]
+[0-9a-f]+ <[^>]*> 797020d9 insve\.w \$w3\[0\],\$w4\[0\]
+[0-9a-f]+ <[^>]*> 79773159 insve\.w \$w5\[7\],\$w6\[0\]
+[0-9a-f]+ <[^>]*> 797841d9 insve\.d \$w7\[0\],\$w8\[0\]
+[0-9a-f]+ <[^>]*> 797b5259 insve\.d \$w9\[3\],\$w10\[0\]
+[0-9a-f]+ <[^>]*> 478b8000 bnz\.b \$w11,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 478c7fff bnz\.b \$w12,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 478dfffb bnz\.b \$w13,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 478effff bnz\.b \$w14,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47af8000 bnz\.h \$w15,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47b07fff bnz\.h \$w16,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47b1fffb bnz\.h \$w17,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47b2ffff bnz\.h \$w18,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47d38000 bnz\.w \$w19,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47d47fff bnz\.w \$w20,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47d5fffb bnz\.w \$w21,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47d6ffff bnz\.w \$w22,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47f78000 bnz\.d \$w23,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47f87fff bnz\.d \$w24,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47f9fffb bnz\.d \$w25,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47faffff bnz\.d \$w26,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 471b8000 bz\.b \$w27,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 471c7fff bz\.b \$w28,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 471dfffb bz\.b \$w29,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 471effff bz\.b \$w30,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 473f8000 bz\.h \$w31,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47207fff bz\.h \$w0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4721fffb bz\.h \$w1,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4722ffff bz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47438000 bz\.w \$w3,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47447fff bz\.w \$w4,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4745fffb bz\.w \$w5,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4746ffff bz\.w \$w6,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47678000 bz\.d \$w7,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47687fff bz\.d \$w8,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4769fffb bz\.d \$w9,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 476affff bz\.d \$w10,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MIPS_PC16 external_label
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 7b1002c7 ldi\.b \$w11,-512
+[0-9a-f]+ <[^>]*> 7b0ffb07 ldi\.b \$w12,511
+[0-9a-f]+ <[^>]*> 7b300347 ldi\.h \$w13,-512
+[0-9a-f]+ <[^>]*> 7b2ffb87 ldi\.h \$w14,511
+[0-9a-f]+ <[^>]*> 7b5003c7 ldi\.w \$w15,-512
+[0-9a-f]+ <[^>]*> 7b4ffc07 ldi\.w \$w16,511
+[0-9a-f]+ <[^>]*> 7b700447 ldi\.d \$w17,-512
+[0-9a-f]+ <[^>]*> 7b6ffc87 ldi\.d \$w18,511
+[0-9a-f]+ <[^>]*> 7815a4da fcaf\.w \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7838bd9a fcaf\.d \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 785bd65a fcun\.w \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 787eef1a fcun\.d \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 788107da fceq\.w \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78a4189a fceq\.d \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78c7315a fcueq\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78ea4a1a fcueq\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 790d62da fclt\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 79307b9a fclt\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7953945a fcult\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7976ad1a fcult\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7999c5da fcle\.w \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79bcde9a fcle\.d \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 79dff75a fcule\.w \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 79e2081a fcule\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7a0520da fsaf\.w \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7a28399a fsaf\.d \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7a4b525a fsun\.w \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7a6e6b1a fsun\.d \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7a9183da fseq\.w \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7ab49c9a fseq\.d \$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7ad7b55a fsueq\.w \$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7aface1a fsueq\.d \$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b1de6da fslt\.w \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7b20ff9a fslt\.d \$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b43105a fsult\.w \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 7b66291a fsult\.d \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b8941da fsle\.w \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 7bac5a9a fsle\.d \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 7bcf735a fsule\.w \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 7bf28c1a fsule\.d \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7815a4db fadd\.w \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7838bd9b fadd\.d \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 785bd65b fsub\.w \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 787eef1b fsub\.d \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 788107db fmul\.w \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 78a4189b fmul\.d \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 78c7315b fdiv\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 78ea4a1b fdiv\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 790d62db fmadd\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 79307b9b fmadd\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7953945b fmsub\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7976ad1b fmsub\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 79d9c5db fexp2\.w \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 79fcde9b fexp2\.d \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7a1ff75b fexdo\.h \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7a22081b fexdo\.w \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7a8520db ftq\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7aa8399b ftq\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b0b525b fmin\.w \$w9,\$w10,\$w11
+[0-9a-f]+ <[^>]*> 7b2e6b1b fmin\.d \$w12,\$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b5183db fmin_a\.w \$w15,\$w16,\$w17
+[0-9a-f]+ <[^>]*> 7b749c9b fmin_a\.d \$w18,\$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b97b55b fmax\.w \$w21,\$w22,\$w23
+[0-9a-f]+ <[^>]*> 7bbace1b fmax\.d \$w24,\$w25,\$w26
+[0-9a-f]+ <[^>]*> 7bdde6db fmax_a\.w \$w27,\$w28,\$w29
+[0-9a-f]+ <[^>]*> 7be0ff9b fmax_a\.d \$w30,\$w31,\$w0
+[0-9a-f]+ <[^>]*> 7843105c fcor\.w \$w1,\$w2,\$w3
+[0-9a-f]+ <[^>]*> 7866291c fcor\.d \$w4,\$w5,\$w6
+[0-9a-f]+ <[^>]*> 788941dc fcune\.w \$w7,\$w8,\$w9
+[0-9a-f]+ <[^>]*> 78ac5a9c fcune\.d \$w10,\$w11,\$w12
+[0-9a-f]+ <[^>]*> 78cf735c fcne\.w \$w13,\$w14,\$w15
+[0-9a-f]+ <[^>]*> 78f28c1c fcne\.d \$w16,\$w17,\$w18
+[0-9a-f]+ <[^>]*> 7915a4dc mul_q\.h \$w19,\$w20,\$w21
+[0-9a-f]+ <[^>]*> 7938bd9c mul_q\.w \$w22,\$w23,\$w24
+[0-9a-f]+ <[^>]*> 795bd65c madd_q\.h \$w25,\$w26,\$w27
+[0-9a-f]+ <[^>]*> 797eef1c madd_q\.w \$w28,\$w29,\$w30
+[0-9a-f]+ <[^>]*> 798107dc msub_q\.h \$w31,\$w0,\$w1
+[0-9a-f]+ <[^>]*> 79a4189c msub_q\.w \$w2,\$w3,\$w4
+[0-9a-f]+ <[^>]*> 7a47315c fsor\.w \$w5,\$w6,\$w7
+[0-9a-f]+ <[^>]*> 7a6a4a1c fsor\.d \$w8,\$w9,\$w10
+[0-9a-f]+ <[^>]*> 7a8d62dc fsune\.w \$w11,\$w12,\$w13
+[0-9a-f]+ <[^>]*> 7ab07b9c fsune\.d \$w14,\$w15,\$w16
+[0-9a-f]+ <[^>]*> 7ad3945c fsne\.w \$w17,\$w18,\$w19
+[0-9a-f]+ <[^>]*> 7af6ad1c fsne\.d \$w20,\$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b19c5dc mulr_q\.h \$w23,\$w24,\$w25
+[0-9a-f]+ <[^>]*> 7b3cde9c mulr_q\.w \$w26,\$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b5ff75c maddr_q\.h \$w29,\$w30,\$w31
+[0-9a-f]+ <[^>]*> 7b62081c maddr_q\.w \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b8520dc msubr_q\.h \$w3,\$w4,\$w5
+[0-9a-f]+ <[^>]*> 7ba8399c msubr_q\.w \$w6,\$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b20525e fclass\.w \$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b2162de fclass\.d \$w11,\$w12
+[0-9a-f]+ <[^>]*> 7b22735e ftrunc_s\.w \$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b2383de ftrunc_s\.d \$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b24945e ftrunc_u\.w \$w17,\$w18
+[0-9a-f]+ <[^>]*> 7b25a4de ftrunc_u\.d \$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b26b55e fsqrt\.w \$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b27c5de fsqrt\.d \$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b28d65e frsqrt\.w \$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b29e6de frsqrt\.d \$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b2af75e frcp\.w \$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b2b07de frcp\.d \$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b2c105e frint\.w \$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b2d20de frint\.d \$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b2e315e flog2\.w \$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b2f41de flog2\.d \$w7,\$w8
+[0-9a-f]+ <[^>]*> 7b30525e fexupl\.w \$w9,\$w10
+[0-9a-f]+ <[^>]*> 7b3162de fexupl\.d \$w11,\$w12
+[0-9a-f]+ <[^>]*> 7b32735e fexupr\.w \$w13,\$w14
+[0-9a-f]+ <[^>]*> 7b3383de fexupr\.d \$w15,\$w16
+[0-9a-f]+ <[^>]*> 7b34945e ffql\.w \$w17,\$w18
+[0-9a-f]+ <[^>]*> 7b35a4de ffql\.d \$w19,\$w20
+[0-9a-f]+ <[^>]*> 7b36b55e ffqr\.w \$w21,\$w22
+[0-9a-f]+ <[^>]*> 7b37c5de ffqr\.d \$w23,\$w24
+[0-9a-f]+ <[^>]*> 7b38d65e ftint_s\.w \$w25,\$w26
+[0-9a-f]+ <[^>]*> 7b39e6de ftint_s\.d \$w27,\$w28
+[0-9a-f]+ <[^>]*> 7b3af75e ftint_u\.w \$w29,\$w30
+[0-9a-f]+ <[^>]*> 7b3b07de ftint_u\.d \$w31,\$w0
+[0-9a-f]+ <[^>]*> 7b3c105e ffint_s\.w \$w1,\$w2
+[0-9a-f]+ <[^>]*> 7b3d20de ffint_s\.d \$w3,\$w4
+[0-9a-f]+ <[^>]*> 7b3e315e ffint_u\.w \$w5,\$w6
+[0-9a-f]+ <[^>]*> 7b3f41de ffint_u\.d \$w7,\$w8
+[0-9a-f]+ <[^>]*> 783e4819 ctcmsa msa_ir,t1
+[0-9a-f]+ <[^>]*> 783e5059 ctcmsa msa_csr,t2
+[0-9a-f]+ <[^>]*> 783e5899 ctcmsa msa_access,t3
+[0-9a-f]+ <[^>]*> 783e60d9 ctcmsa msa_save,t4
+[0-9a-f]+ <[^>]*> 787e0359 cfcmsa t5,msa_ir
+[0-9a-f]+ <[^>]*> 787e0b99 cfcmsa t6,msa_csr
+[0-9a-f]+ <[^>]*> 787e13d9 cfcmsa t7,msa_access
+[0-9a-f]+ <[^>]*> 787e1c19 cfcmsa s0,msa_save
+[0-9a-f]+ <[^>]*> 78be9459 move\.v \$w17,\$w18
+[0-9a-f]+ <[^>]*> 02959805 lsa s3,s4,s5,0x1
+[0-9a-f]+ <[^>]*> 02f8b0c5 lsa s6,s7,t8,0x4
+ \.\.\.
Index: gas/testsuite/gas/mips/msa.s
===================================================================
RCS file: gas/testsuite/gas/mips/msa.s
diff -N gas/testsuite/gas/mips/msa.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa.s 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,758 @@
+ .text
+ .set noat
+ .set noreorder
+ .set nomacro
+test_msa:
+ sll.b $w0,$w1,$w2
+ sll.h $w3,$w4,$w5
+ sll.w $w6,$w7,$w8
+ sll.d $w9,$w10,$w11
+ slli.b $w12,$w13,0
+ slli.b $w14,$w15,7
+ slli.h $w16,$w17,0
+ slli.h $w18,$w19,15
+ slli.w $w20,$w21,0
+ slli.w $w22,$w23,31
+ slli.d $w24,$w25,0
+ slli.d $w26,$w27,63
+ sra.b $w28,$w29,$w30
+ sra.h $w31,$w0,$w1
+ sra.w $w2,$w3,$w4
+ sra.d $w5,$w6,$w7
+ srai.b $w8,$w9,0
+ srai.b $w10,$w11,7
+ srai.h $w12,$w13,0
+ srai.h $w14,$w15,15
+ srai.w $w16,$w17,0
+ srai.w $w18,$w19,31
+ srai.d $w20,$w21,0
+ srai.d $w22,$w23,63
+ srl.b $w24,$w25,$w26
+ srl.h $w27,$w28,$w29
+ srl.w $w30,$w31,$w0
+ srl.d $w1,$w2,$w3
+ srli.b $w4,$w5,0
+ srli.b $w6,$w7,7
+ srli.h $w8,$w9,0
+ srli.h $w10,$w11,15
+ srli.w $w12,$w13,0
+ srli.w $w14,$w15,31
+ srli.d $w16,$w17,0
+ srli.d $w18,$w19,63
+ bclr.b $w20,$w21,$w22
+ bclr.h $w23,$w24,$w25
+ bclr.w $w26,$w27,$w28
+ bclr.d $w29,$w30,$w31
+ bclri.b $w0,$w1,0
+ bclri.b $w2,$w3,7
+ bclri.h $w4,$w5,0
+ bclri.h $w6,$w7,15
+ bclri.w $w8,$w9,0
+ bclri.w $w10,$w11,31
+ bclri.d $w12,$w13,0
+ bclri.d $w14,$w15,63
+ bset.b $w16,$w17,$w18
+ bset.h $w19,$w20,$w21
+ bset.w $w22,$w23,$w24
+ bset.d $w25,$w26,$w27
+ bseti.b $w28,$w29,0
+ bseti.b $w30,$w31,7
+ bseti.h $w0,$w1,0
+ bseti.h $w2,$w3,15
+ bseti.w $w4,$w5,0
+ bseti.w $w6,$w7,31
+ bseti.d $w8,$w9,0
+ bseti.d $w10,$w11,63
+ bneg.b $w12,$w13,$w14
+ bneg.h $w15,$w16,$w17
+ bneg.w $w18,$w19,$w20
+ bneg.d $w21,$w22,$w23
+ bnegi.b $w24,$w25,0
+ bnegi.b $w26,$w27,7
+ bnegi.h $w28,$w29,0
+ bnegi.h $w30,$w31,15
+ bnegi.w $w0,$w1,0
+ bnegi.w $w2,$w3,31
+ bnegi.d $w4,$w5,0
+ bnegi.d $w6,$w7,63
+ binsl.b $w8,$w9,$w10
+ binsl.h $w11,$w12,$w13
+ binsl.w $w14,$w15,$w16
+ binsl.d $w17,$w18,$w19
+ binsli.b $w20,$w21,0
+ binsli.b $w22,$w23,7
+ binsli.h $w24,$w25,0
+ binsli.h $w26,$w27,15
+ binsli.w $w28,$w29,0
+ binsli.w $w30,$w31,31
+ binsli.d $w0,$w1,0
+ binsli.d $w2,$w3,63
+ binsr.b $w4,$w5,$w6
+ binsr.h $w7,$w8,$w9
+ binsr.w $w10,$w11,$w12
+ binsr.d $w13,$w14,$w15
+ binsri.b $w16,$w17,0
+ binsri.b $w18,$w19,7
+ binsri.h $w20,$w21,0
+ binsri.h $w22,$w23,15
+ binsri.w $w24,$w25,0
+ binsri.w $w26,$w27,31
+ binsri.d $w28,$w29,0
+ binsri.d $w30,$w31,63
+ addv.b $w0,$w1,$w2
+ addv.h $w3,$w4,$w5
+ addv.w $w6,$w7,$w8
+ addv.d $w9,$w10,$w11
+ addvi.b $w12,$w13,0
+ addvi.b $w14,$w15,31
+ addvi.h $w16,$w17,0
+ addvi.h $w18,$w19,31
+ addvi.w $w20,$w21,0
+ addvi.w $w22,$w23,31
+ addvi.d $w24,$w25,0
+ addvi.d $w26,$w27,31
+ subv.b $w28,$w29,$w30
+ subv.h $w31,$w0,$w1
+ subv.w $w2,$w3,$w4
+ subv.d $w5,$w6,$w7
+ subvi.b $w8,$w9,0
+ subvi.b $w10,$w11,31
+ subvi.h $w12,$w13,0
+ subvi.h $w14,$w15,31
+ subvi.w $w16,$w17,0
+ subvi.w $w18,$w19,31
+ subvi.d $w20,$w21,0
+ subvi.d $w22,$w23,31
+ max_s.b $w24,$w25,$w26
+ max_s.h $w27,$w28,$w29
+ max_s.w $w30,$w31,$w0
+ max_s.d $w1,$w2,$w3
+ maxi_s.b $w4,$w5,-16
+ maxi_s.b $w6,$w7,15
+ maxi_s.h $w8,$w9,-16
+ maxi_s.h $w10,$w11,15
+ maxi_s.w $w12,$w13,-16
+ maxi_s.w $w14,$w15,15
+ maxi_s.d $w16,$w17,-16
+ maxi_s.d $w18,$w19,15
+ max_u.b $w20,$w21,$w22
+ max_u.h $w23,$w24,$w25
+ max_u.w $w26,$w27,$w28
+ max_u.d $w29,$w30,$w31
+ maxi_u.b $w0,$w1,0
+ maxi_u.b $w2,$w3,31
+ maxi_u.h $w4,$w5,0
+ maxi_u.h $w6,$w7,31
+ maxi_u.w $w8,$w9,0
+ maxi_u.w $w10,$w11,31
+ maxi_u.d $w12,$w13,0
+ maxi_u.d $w14,$w15,31
+ min_s.b $w16,$w17,$w18
+ min_s.h $w19,$w20,$w21
+ min_s.w $w22,$w23,$w24
+ min_s.d $w25,$w26,$w27
+ mini_s.b $w28,$w29,-16
+ mini_s.b $w30,$w31,15
+ mini_s.h $w0,$w1,-16
+ mini_s.h $w2,$w3,15
+ mini_s.w $w4,$w5,-16
+ mini_s.w $w6,$w7,15
+ mini_s.d $w8,$w9,-16
+ mini_s.d $w10,$w11,15
+ min_u.b $w12,$w13,$w14
+ min_u.h $w15,$w16,$w17
+ min_u.w $w18,$w19,$w20
+ min_u.d $w21,$w22,$w23
+ mini_u.b $w24,$w25,0
+ mini_u.b $w26,$w27,31
+ mini_u.h $w28,$w29,0
+ mini_u.h $w30,$w31,31
+ mini_u.w $w0,$w1,0
+ mini_u.w $w2,$w3,31
+ mini_u.d $w4,$w5,0
+ mini_u.d $w6,$w7,31
+ max_a.b $w8,$w9,$w10
+ max_a.h $w11,$w12,$w13
+ max_a.w $w14,$w15,$w16
+ max_a.d $w17,$w18,$w19
+ min_a.b $w20,$w21,$w22
+ min_a.h $w23,$w24,$w25
+ min_a.w $w26,$w27,$w28
+ min_a.d $w29,$w30,$w31
+ ceq.b $w0,$w1,$w2
+ ceq.h $w3,$w4,$w5
+ ceq.w $w6,$w7,$w8
+ ceq.d $w9,$w10,$w11
+ ceqi.b $w12,$w13,-16
+ ceqi.b $w14,$w15,15
+ ceqi.h $w16,$w17,-16
+ ceqi.h $w18,$w19,15
+ ceqi.w $w20,$w21,-16
+ ceqi.w $w22,$w23,15
+ ceqi.d $w24,$w25,-16
+ ceqi.d $w26,$w27,15
+ clt_s.b $w28,$w29,$w30
+ clt_s.h $w31,$w0,$w1
+ clt_s.w $w2,$w3,$w4
+ clt_s.d $w5,$w6,$w7
+ clti_s.b $w8,$w9,-16
+ clti_s.b $w10,$w11,15
+ clti_s.h $w12,$w13,-16
+ clti_s.h $w14,$w15,15
+ clti_s.w $w16,$w17,-16
+ clti_s.w $w18,$w19,15
+ clti_s.d $w20,$w21,-16
+ clti_s.d $w22,$w23,15
+ clt_u.b $w24,$w25,$w26
+ clt_u.h $w27,$w28,$w29
+ clt_u.w $w30,$w31,$w0
+ clt_u.d $w1,$w2,$w3
+ clti_u.b $w4,$w5,0
+ clti_u.b $w6,$w7,31
+ clti_u.h $w8,$w9,0
+ clti_u.h $w10,$w11,31
+ clti_u.w $w12,$w13,0
+ clti_u.w $w14,$w15,31
+ clti_u.d $w16,$w17,0
+ clti_u.d $w18,$w19,31
+ cle_s.b $w20,$w21,$w22
+ cle_s.h $w23,$w24,$w25
+ cle_s.w $w26,$w27,$w28
+ cle_s.d $w29,$w30,$w31
+ clei_s.b $w0,$w1,-16
+ clei_s.b $w2,$w3,15
+ clei_s.h $w4,$w5,-16
+ clei_s.h $w6,$w7,15
+ clei_s.w $w8,$w9,-16
+ clei_s.w $w10,$w11,15
+ clei_s.d $w12,$w13,-16
+ clei_s.d $w14,$w15,15
+ cle_u.b $w16,$w17,$w18
+ cle_u.h $w19,$w20,$w21
+ cle_u.w $w22,$w23,$w24
+ cle_u.d $w25,$w26,$w27
+ clei_u.b $w28,$w29,0
+ clei_u.b $w30,$w31,31
+ clei_u.h $w0,$w1,0
+ clei_u.h $w2,$w3,31
+ clei_u.w $w4,$w5,0
+ clei_u.w $w6,$w7,31
+ clei_u.d $w8,$w9,0
+ clei_u.d $w10,$w11,31
+ ld.b $w12,-512($13)
+ ld.b $w14,511($15)
+ ld.h $w16,-1024($17)
+ ld.h $w18,1022($19)
+ ld.w $w20,-2048($21)
+ ld.w $w22,2044($23)
+ ld.d $w24,-4096($25)
+ ld.d $w26,4088($27)
+ st.b $w28,-512($29)
+ st.b $w30,511($31)
+ st.h $w0,-1024($1)
+ st.h $w2,1022($3)
+ st.w $w4,-2048($5)
+ st.w $w6,2044($7)
+ st.d $w8,-4096($9)
+ st.d $w10,4088($11)
+ sat_s.b $w12,$w13,0
+ sat_s.b $w14,$w15,7
+ sat_s.h $w16,$w17,0
+ sat_s.h $w18,$w19,15
+ sat_s.w $w20,$w21,0
+ sat_s.w $w22,$w23,31
+ sat_s.d $w24,$w25,0
+ sat_s.d $w26,$w27,63
+ sat_u.b $w28,$w29,0
+ sat_u.b $w30,$w31,7
+ sat_u.h $w0,$w1,0
+ sat_u.h $w2,$w3,15
+ sat_u.w $w4,$w5,0
+ sat_u.w $w6,$w7,31
+ sat_u.d $w8,$w9,0
+ sat_u.d $w10,$w11,63
+ add_a.b $w12,$w13,$w14
+ add_a.h $w15,$w16,$w17
+ add_a.w $w18,$w19,$w20
+ add_a.d $w21,$w22,$w23
+ adds_a.b $w24,$w25,$w26
+ adds_a.h $w27,$w28,$w29
+ adds_a.w $w30,$w31,$w0
+ adds_a.d $w1,$w2,$w3
+ adds_s.b $w4,$w5,$w6
+ adds_s.h $w7,$w8,$w9
+ adds_s.w $w10,$w11,$w12
+ adds_s.d $w13,$w14,$w15
+ adds_u.b $w16,$w17,$w18
+ adds_u.h $w19,$w20,$w21
+ adds_u.w $w22,$w23,$w24
+ adds_u.d $w25,$w26,$w27
+ ave_s.b $w28,$w29,$w30
+ ave_s.h $w31,$w0,$w1
+ ave_s.w $w2,$w3,$w4
+ ave_s.d $w5,$w6,$w7
+ ave_u.b $w8,$w9,$w10
+ ave_u.h $w11,$w12,$w13
+ ave_u.w $w14,$w15,$w16
+ ave_u.d $w17,$w18,$w19
+ aver_s.b $w20,$w21,$w22
+ aver_s.h $w23,$w24,$w25
+ aver_s.w $w26,$w27,$w28
+ aver_s.d $w29,$w30,$w31
+ aver_u.b $w0,$w1,$w2
+ aver_u.h $w3,$w4,$w5
+ aver_u.w $w6,$w7,$w8
+ aver_u.d $w9,$w10,$w11
+ subs_s.b $w12,$w13,$w14
+ subs_s.h $w15,$w16,$w17
+ subs_s.w $w18,$w19,$w20
+ subs_s.d $w21,$w22,$w23
+ subs_u.b $w24,$w25,$w26
+ subs_u.h $w27,$w28,$w29
+ subs_u.w $w30,$w31,$w0
+ subs_u.d $w1,$w2,$w3
+ subsus_u.b $w4,$w5,$w6
+ subsus_u.h $w7,$w8,$w9
+ subsus_u.w $w10,$w11,$w12
+ subsus_u.d $w13,$w14,$w15
+ subsuu_s.b $w16,$w17,$w18
+ subsuu_s.h $w19,$w20,$w21
+ subsuu_s.w $w22,$w23,$w24
+ subsuu_s.d $w25,$w26,$w27
+ asub_s.b $w28,$w29,$w30
+ asub_s.h $w31,$w0,$w1
+ asub_s.w $w2,$w3,$w4
+ asub_s.d $w5,$w6,$w7
+ asub_u.b $w8,$w9,$w10
+ asub_u.h $w11,$w12,$w13
+ asub_u.w $w14,$w15,$w16
+ asub_u.d $w17,$w18,$w19
+ mulv.b $w20,$w21,$w22
+ mulv.h $w23,$w24,$w25
+ mulv.w $w26,$w27,$w28
+ mulv.d $w29,$w30,$w31
+ maddv.b $w0,$w1,$w2
+ maddv.h $w3,$w4,$w5
+ maddv.w $w6,$w7,$w8
+ maddv.d $w9,$w10,$w11
+ msubv.b $w12,$w13,$w14
+ msubv.h $w15,$w16,$w17
+ msubv.w $w18,$w19,$w20
+ msubv.d $w21,$w22,$w23
+ div_s.b $w24,$w25,$w26
+ div_s.h $w27,$w28,$w29
+ div_s.w $w30,$w31,$w0
+ div_s.d $w1,$w2,$w3
+ div_u.b $w4,$w5,$w6
+ div_u.h $w7,$w8,$w9
+ div_u.w $w10,$w11,$w12
+ div_u.d $w13,$w14,$w15
+ mod_s.b $w16,$w17,$w18
+ mod_s.h $w19,$w20,$w21
+ mod_s.w $w22,$w23,$w24
+ mod_s.d $w25,$w26,$w27
+ mod_u.b $w28,$w29,$w30
+ mod_u.h $w31,$w0,$w1
+ mod_u.w $w2,$w3,$w4
+ mod_u.d $w5,$w6,$w7
+ dotp_s.h $w8,$w9,$w10
+ dotp_s.w $w11,$w12,$w13
+ dotp_s.d $w14,$w15,$w16
+ dotp_u.h $w17,$w18,$w19
+ dotp_u.w $w20,$w21,$w22
+ dotp_u.d $w23,$w24,$w25
+ dpadd_s.h $w26,$w27,$w28
+ dpadd_s.w $w29,$w30,$w31
+ dpadd_s.d $w0,$w1,$w2
+ dpadd_u.h $w3,$w4,$w5
+ dpadd_u.w $w6,$w7,$w8
+ dpadd_u.d $w9,$w10,$w11
+ dpsub_s.h $w12,$w13,$w14
+ dpsub_s.w $w15,$w16,$w17
+ dpsub_s.d $w18,$w19,$w20
+ dpsub_u.h $w21,$w22,$w23
+ dpsub_u.w $w24,$w25,$w26
+ dpsub_u.d $w27,$w28,$w29
+ sld.b $w30,$w31[$0]
+ sld.h $w1,$w2[$3]
+ sld.w $w4,$w5[$6]
+ sld.d $w7,$w8[$9]
+ sldi.b $w10,$w11[0]
+ sldi.b $w12,$w13[31]
+ sldi.h $w14,$w15[0]
+ sldi.h $w16,$w17[15]
+ sldi.w $w18,$w19[0]
+ sldi.w $w20,$w21[7]
+ sldi.d $w22,$w23[0]
+ sldi.d $w24,$w25[3]
+ splat.b $w26,$w27[$28]
+ splat.h $w29,$w30[$31]
+ splat.w $w0,$w1[$2]
+ splat.d $w3,$w4[$5]
+ splati.b $w6,$w7[0]
+ splati.b $w8,$w9[31]
+ splati.h $w10,$w11[0]
+ splati.h $w12,$w13[15]
+ splati.w $w14,$w15[0]
+ splati.w $w16,$w17[7]
+ splati.d $w18,$w19[0]
+ splati.d $w20,$w21[3]
+ pckev.b $w22,$w23,$w24
+ pckev.h $w25,$w26,$w27
+ pckev.w $w28,$w29,$w30
+ pckev.d $w31,$w0,$w1
+ pckod.b $w2,$w3,$w4
+ pckod.h $w5,$w6,$w7
+ pckod.w $w8,$w9,$w10
+ pckod.d $w11,$w12,$w13
+ ilvl.b $w14,$w15,$w16
+ ilvl.h $w17,$w18,$w19
+ ilvl.w $w20,$w21,$w22
+ ilvl.d $w23,$w24,$w25
+ ilvr.b $w26,$w27,$w28
+ ilvr.h $w29,$w30,$w31
+ ilvr.w $w0,$w1,$w2
+ ilvr.d $w3,$w4,$w5
+ ilvev.b $w6,$w7,$w8
+ ilvev.h $w9,$w10,$w11
+ ilvev.w $w12,$w13,$w14
+ ilvev.d $w15,$w16,$w17
+ ilvod.b $w18,$w19,$w20
+ ilvod.h $w21,$w22,$w23
+ ilvod.w $w24,$w25,$w26
+ ilvod.d $w27,$w28,$w29
+ vshf.b $w30,$w31,$w0
+ vshf.h $w1,$w2,$w3
+ vshf.w $w4,$w5,$w6
+ vshf.d $w7,$w8,$w9
+ srar.b $w10,$w11,$w12
+ srar.h $w13,$w14,$w15
+ srar.w $w16,$w17,$w18
+ srar.d $w19,$w20,$w21
+ srari.b $w22,$w23,0
+ srari.b $w24,$w25,7
+ srari.h $w26,$w27,0
+ srari.h $w28,$w29,15
+ srari.w $w30,$w31,0
+ srari.w $w0,$w1,31
+ srari.d $w2,$w3,0
+ srari.d $w4,$w5,63
+ srlr.b $w6,$w7,$w8
+ srlr.h $w9,$w10,$w11
+ srlr.w $w12,$w13,$w14
+ srlr.d $w15,$w16,$w17
+ srlri.b $w18,$w19,0
+ srlri.b $w20,$w21,7
+ srlri.h $w22,$w23,0
+ srlri.h $w24,$w25,15
+ srlri.w $w26,$w27,0
+ srlri.w $w28,$w29,31
+ srlri.d $w30,$w31,0
+ srlri.d $w0,$w1,63
+ hadd_s.h $w2,$w3,$w4
+ hadd_s.w $w5,$w6,$w7
+ hadd_s.d $w8,$w9,$w10
+ hadd_u.h $w11,$w12,$w13
+ hadd_u.w $w14,$w15,$w16
+ hadd_u.d $w17,$w18,$w19
+ hsub_s.h $w20,$w21,$w22
+ hsub_s.w $w23,$w24,$w25
+ hsub_s.d $w26,$w27,$w28
+ hsub_u.h $w29,$w30,$w31
+ hsub_u.w $w0,$w1,$w2
+ hsub_u.d $w3,$w4,$w5
+ and.v $w6,$w7,$w8
+ andi.b $w9,$w10,0
+ andi.b $w11,$w12,255
+ or.v $w13,$w14,$w15
+ ori.b $w16,$w17,0
+ ori.b $w18,$w19,255
+ nor.v $w20,$w21,$w22
+ nori.b $w23,$w24,0
+ nori.b $w25,$w26,255
+ xor.v $w27,$w28,$w29
+ xori.b $w30,$w31,0
+ xori.b $w0,$w1,255
+ bmnz.v $w2,$w3,$w4
+ bmnzi.b $w5,$w6,0
+ bmnzi.b $w7,$w8,255
+ bmz.v $w9,$w10,$w11
+ bmzi.b $w12,$w13,0
+ bmzi.b $w14,$w15,255
+ bsel.v $w16,$w17,$w18
+ bseli.b $w19,$w20,0
+ bseli.b $w21,$w22,255
+ shf.b $w23,$w24,0
+ shf.b $w25,$w26,255
+ shf.h $w27,$w28,0
+ shf.h $w29,$w30,255
+ shf.w $w31,$w0,0
+ shf.w $w1,$w2,255
+1:
+ bnz.v $w3,. + 4 + (-32768 << 2)
+ nop
+ bnz.v $w4,. + 4 + (32767 << 2)
+ nop
+ bnz.v $w5,1b
+ nop
+ bnz.v $w6,external_label
+ nop
+1:
+ bz.v $w7,. + 4 + (-32768 << 2)
+ nop
+ bz.v $w8,. + 4 + (32767 << 2)
+ nop
+ bz.v $w9,1b
+ nop
+ bz.v $w10,external_label
+ nop
+ fill.b $w11,$12
+ fill.h $w13,$14
+ fill.w $w15,$16
+ pcnt.b $w19,$w20
+ pcnt.h $w21,$w22
+ pcnt.w $w23,$w24
+ pcnt.d $w25,$w26
+ nloc.b $w27,$w28
+ nloc.h $w29,$w30
+ nloc.w $w31,$w0
+ nloc.d $w1,$w2
+ nlzc.b $w3,$w4
+ nlzc.h $w5,$w6
+ nlzc.w $w7,$w8
+ nlzc.d $w9,$w10
+ copy_s.b $11,$w12[0]
+ copy_s.b $13,$w14[31]
+ copy_s.h $15,$w16[0]
+ copy_s.h $17,$w18[15]
+ copy_s.w $19,$w20[0]
+ copy_s.w $21,$w22[7]
+ copy_u.b $27,$w28[0]
+ copy_u.b $29,$w30[31]
+ copy_u.h $31,$w0[0]
+ copy_u.h $1,$w2[15]
+ copy_u.w $3,$w4[0]
+ copy_u.w $5,$w6[7]
+ insert.b $w11[0],$12
+ insert.b $w13[31],$14
+ insert.h $w15[0],$16
+ insert.h $w17[15],$18
+ insert.w $w19[0],$20
+ insert.w $w21[7],$22
+ insve.b $w27[0],$w28[0]
+ insve.b $w29[31],$w30[0]
+ insve.h $w31[0],$w0[0]
+ insve.h $w1[15],$w2[0]
+ insve.w $w3[0],$w4[0]
+ insve.w $w5[7],$w6[0]
+ insve.d $w7[0],$w8[0]
+ insve.d $w9[3],$w10[0]
+1:
+ bnz.b $w11,. + 4 + (-32768 << 2)
+ nop
+ bnz.b $w12,. + 4 + (32767 << 2)
+ nop
+ bnz.b $w13,1b
+ nop
+ bnz.b $w14,external_label
+ nop
+1:
+ bnz.h $w15,. + 4 + (-32768 << 2)
+ nop
+ bnz.h $w16,. + 4 + (32767 << 2)
+ nop
+ bnz.h $w17,1b
+ nop
+ bnz.h $w18,external_label
+ nop
+1:
+ bnz.w $w19,. + 4 + (-32768 << 2)
+ nop
+ bnz.w $w20,. + 4 + (32767 << 2)
+ nop
+ bnz.w $w21,1b
+ nop
+ bnz.w $w22,external_label
+ nop
+1:
+ bnz.d $w23,. + 4 + (-32768 << 2)
+ nop
+ bnz.d $w24,. + 4 + (32767 << 2)
+ nop
+ bnz.d $w25,1b
+ nop
+ bnz.d $w26,external_label
+ nop
+1:
+ bz.b $w27,. + 4 + (-32768 << 2)
+ nop
+ bz.b $w28,. + 4 + (32767 << 2)
+ nop
+ bz.b $w29,1b
+ nop
+ bz.b $w30,external_label
+ nop
+1:
+ bz.h $w31,. + 4 + (-32768 << 2)
+ nop
+ bz.h $w0,. + 4 + (32767 << 2)
+ nop
+ bz.h $w1,1b
+ nop
+ bz.h $w2,external_label
+ nop
+1:
+ bz.w $w3,. + 4 + (-32768 << 2)
+ nop
+ bz.w $w4,. + 4 + (32767 << 2)
+ nop
+ bz.w $w5,1b
+ nop
+ bz.w $w6,external_label
+ nop
+1:
+ bz.d $w7,. + 4 + (-32768 << 2)
+ nop
+ bz.d $w8,. + 4 + (32767 << 2)
+ nop
+ bz.d $w9,1b
+ nop
+ bz.d $w10,external_label
+ nop
+ ldi.b $w11,-512
+ ldi.b $w12,511
+ ldi.h $w13,-512
+ ldi.h $w14,511
+ ldi.w $w15,-512
+ ldi.w $w16,511
+ ldi.d $w17,-512
+ ldi.d $w18,511
+ fcaf.w $w19,$w20,$w21
+ fcaf.d $w22,$w23,$w24
+ fcun.w $w25,$w26,$w27
+ fcun.d $w28,$w29,$w30
+ fceq.w $w31,$w0,$w1
+ fceq.d $w2,$w3,$w4
+ fcueq.w $w5,$w6,$w7
+ fcueq.d $w8,$w9,$w10
+ fclt.w $w11,$w12,$w13
+ fclt.d $w14,$w15,$w16
+ fcult.w $w17,$w18,$w19
+ fcult.d $w20,$w21,$w22
+ fcle.w $w23,$w24,$w25
+ fcle.d $w26,$w27,$w28
+ fcule.w $w29,$w30,$w31
+ fcule.d $w0,$w1,$w2
+ fsaf.w $w3,$w4,$w5
+ fsaf.d $w6,$w7,$w8
+ fsun.w $w9,$w10,$w11
+ fsun.d $w12,$w13,$w14
+ fseq.w $w15,$w16,$w17
+ fseq.d $w18,$w19,$w20
+ fsueq.w $w21,$w22,$w23
+ fsueq.d $w24,$w25,$w26
+ fslt.w $w27,$w28,$w29
+ fslt.d $w30,$w31,$w0
+ fsult.w $w1,$w2,$w3
+ fsult.d $w4,$w5,$w6
+ fsle.w $w7,$w8,$w9
+ fsle.d $w10,$w11,$w12
+ fsule.w $w13,$w14,$w15
+ fsule.d $w16,$w17,$w18
+ fadd.w $w19,$w20,$w21
+ fadd.d $w22,$w23,$w24
+ fsub.w $w25,$w26,$w27
+ fsub.d $w28,$w29,$w30
+ fmul.w $w31,$w0,$w1
+ fmul.d $w2,$w3,$w4
+ fdiv.w $w5,$w6,$w7
+ fdiv.d $w8,$w9,$w10
+ fmadd.w $w11,$w12,$w13
+ fmadd.d $w14,$w15,$w16
+ fmsub.w $w17,$w18,$w19
+ fmsub.d $w20,$w21,$w22
+ fexp2.w $w23,$w24,$w25
+ fexp2.d $w26,$w27,$w28
+ fexdo.h $w29,$w30,$w31
+ fexdo.w $w0,$w1,$w2
+ ftq.h $w3,$w4,$w5
+ ftq.w $w6,$w7,$w8
+ fmin.w $w9,$w10,$w11
+ fmin.d $w12,$w13,$w14
+ fmin_a.w $w15,$w16,$w17
+ fmin_a.d $w18,$w19,$w20
+ fmax.w $w21,$w22,$w23
+ fmax.d $w24,$w25,$w26
+ fmax_a.w $w27,$w28,$w29
+ fmax_a.d $w30,$w31,$w0
+ fcor.w $w1,$w2,$w3
+ fcor.d $w4,$w5,$w6
+ fcune.w $w7,$w8,$w9
+ fcune.d $w10,$w11,$w12
+ fcne.w $w13,$w14,$w15
+ fcne.d $w16,$w17,$w18
+ mul_q.h $w19,$w20,$w21
+ mul_q.w $w22,$w23,$w24
+ madd_q.h $w25,$w26,$w27
+ madd_q.w $w28,$w29,$w30
+ msub_q.h $w31,$w0,$w1
+ msub_q.w $w2,$w3,$w4
+ fsor.w $w5,$w6,$w7
+ fsor.d $w8,$w9,$w10
+ fsune.w $w11,$w12,$w13
+ fsune.d $w14,$w15,$w16
+ fsne.w $w17,$w18,$w19
+ fsne.d $w20,$w21,$w22
+ mulr_q.h $w23,$w24,$w25
+ mulr_q.w $w26,$w27,$w28
+ maddr_q.h $w29,$w30,$w31
+ maddr_q.w $w0,$w1,$w2
+ msubr_q.h $w3,$w4,$w5
+ msubr_q.w $w6,$w7,$w8
+ fclass.w $w9,$w10
+ fclass.d $w11,$w12
+ ftrunc_s.w $w13,$w14
+ ftrunc_s.d $w15,$w16
+ ftrunc_u.w $w17,$w18
+ ftrunc_u.d $w19,$w20
+ fsqrt.w $w21,$w22
+ fsqrt.d $w23,$w24
+ frsqrt.w $w25,$w26
+ frsqrt.d $w27,$w28
+ frcp.w $w29,$w30
+ frcp.d $w31,$w0
+ frint.w $w1,$w2
+ frint.d $w3,$w4
+ flog2.w $w5,$w6
+ flog2.d $w7,$w8
+ fexupl.w $w9,$w10
+ fexupl.d $w11,$w12
+ fexupr.w $w13,$w14
+ fexupr.d $w15,$w16
+ ffql.w $w17,$w18
+ ffql.d $w19,$w20
+ ffqr.w $w21,$w22
+ ffqr.d $w23,$w24
+ ftint_s.w $w25,$w26
+ ftint_s.d $w27,$w28
+ ftint_u.w $w29,$w30
+ ftint_u.d $w31,$w0
+ ffint_s.w $w1,$w2
+ ffint_s.d $w3,$w4
+ ffint_u.w $w5,$w6
+ ffint_u.d $w7,$w8
+ ctcmsa $0,$9
+ ctcmsa $1,$10
+ ctcmsa $2,$11
+ ctcmsa $3,$12
+ cfcmsa $13,$0
+ cfcmsa $14,$1
+ cfcmsa $15,$2
+ cfcmsa $16,$3
+ move.v $w17,$w18
+ lsa $19,$20,$21,1
+ lsa $22,$23,$24,4
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
Index: gas/testsuite/gas/mips/msa64.d
===================================================================
RCS file: gas/testsuite/gas/mips/msa64.d
diff -N gas/testsuite/gas/mips/msa64.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa64.d 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,17 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA64 instructions
+#as: -64 -mmsa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7b03945e fill\.d \$w17,s2
+[0-9a-f]+ <[^>]*> 78b8c5d9 copy_s\.d s7,\$w24\[0\]
+[0-9a-f]+ <[^>]*> 78bbd659 copy_s\.d t9,\$w26\[3\]
+[0-9a-f]+ <[^>]*> 78f841d9 copy_u\.d a3,\$w8\[0\]
+[0-9a-f]+ <[^>]*> 78fb5259 copy_u\.d a5,\$w10\[3\]
+[0-9a-f]+ <[^>]*> 7938c5d9 insert\.d \$w23\[0\],t8
+[0-9a-f]+ <[^>]*> 793bd659 insert\.d \$w25\[3\],k0
+[0-9a-f]+ <[^>]*> 035bc815 dlsa t9,k0,k1,0x1
+[0-9a-f]+ <[^>]*> 03bee0d5 dlsa gp,sp,s8,0x4
+ \.\.\.
Index: gas/testsuite/gas/mips/msa64.s
===================================================================
RCS file: gas/testsuite/gas/mips/msa64.s
diff -N gas/testsuite/gas/mips/msa64.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/msa64.s 9 Oct 2013 23:42:54 -0000
@@ -0,0 +1,15 @@
+ .text
+test_msa64:
+ fill.d $w17,$18
+ copy_s.d $23,$w24[0]
+ copy_s.d $25,$w26[3]
+ copy_u.d $7,$w8[0]
+ copy_u.d $9,$w10[3]
+ insert.d $w23[0],$24
+ insert.d $w25[3],$26
+ dlsa $25,$26,$27,1
+ dlsa $28,$29,$30,4
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.55
diff -u -p -r1.55 mips.h
--- include/elf/mips.h 17 Sep 2013 21:05:49 -0000 1.55
+++ include/elf/mips.h 9 Oct 2013 23:42:58 -0000
@@ -1135,6 +1135,9 @@ enum
/* Floating-point ABI used by this object file. */
Tag_GNU_MIPS_ABI_FP = 4,
+
+ /* MSA ABI used by this object file. */
+ Tag_GNU_MIPS_ABI_MSA = 8,
};
/* Object attribute values. */
@@ -1158,4 +1161,16 @@ enum
Val_GNU_MIPS_ABI_FP_64 = 4,
};
+/* Object attribute values. */
+enum
+{
+ /* Values defined for Tag_GNU_MIPS_ABI_MSA. */
+
+ /* Not tagged or not using any ABIs affected by the differences. */
+ Val_GNU_MIPS_ABI_MSA_ANY = 0,
+
+ /* Using 128-bit MSA. */
+ Val_GNU_MIPS_ABI_MSA_128 = 1,
+};
+
#endif /* _ELF_MIPS_H */
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.109
diff -u -p -r1.109 mips.h
--- include/opcode/mips.h 19 Aug 2013 19:56:44 -0000 1.109
+++ include/opcode/mips.h 9 Oct 2013 23:42:58 -0000
@@ -413,7 +413,13 @@ enum mips_operand_type {
/* Like OP_VU0_SUFFIX, but used when the operand's value has already
been set. Any suffix used here must match the previous value. */
- OP_VU0_MATCH_SUFFIX
+ OP_VU0_MATCH_SUFFIX,
+
+ /* An index selected by an integer, e.g. [1]. */
+ OP_IMM_INDEX,
+
+ /* An index selected by a register, e.g. [$2]. */
+ OP_REG_INDEX
};
/* Enumerates the types of MIPS register. */
@@ -454,7 +460,13 @@ enum mips_reg_operand_type {
OP_REG_R5900_I,
OP_REG_R5900_Q,
OP_REG_R5900_R,
- OP_REG_R5900_ACC
+ OP_REG_R5900_ACC,
+
+ /* MSA registers $w0-$w31. */
+ OP_REG_MSA,
+
+ /* MSA control registers. */
+ OP_REG_MSA_CTRL
};
/* Base class for all operands. */
@@ -891,6 +903,32 @@ struct mips_opcode
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 5-bit vector element index at bit 16
+ "+u" 4-bit vector element index at bit 16
+ "+v" 3-bit vector element index at bit 16
+ "+w" 2-bit vector element index at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -905,8 +943,9 @@ struct mips_opcode
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
- "ABCEFGHJKLMNPQSXZ"
- "abcfgijmpqrstxyz"
+ "~!@#$%^&*|"
+ "ABCEFGHJKLMNPQSTUVWXZ"
+ "abcdefghijklmnopqrstuvwxyz"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -1115,6 +1154,9 @@ static const unsigned int mips_isa_table
/* Virtualization ASE */
#define ASE_VIRT 0x00000200
#define ASE_VIRT64 0x00000400
+/* MSA Extension */
+#define ASE_MSA 0x00000800
+#define ASE_MSA64 0x00001000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -2044,6 +2086,33 @@ extern const int bfd_mips16_num_opcodes;
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 5-bit vector element index at bit 16
+ "+u" 4-bit vector element index at bit 16
+ "+v" 3-bit vector element index at bit 16
+ "+w" 2-bit vector element index at bit 16
+ "+x" 5-bit shift amount at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -2059,9 +2128,9 @@ extern const int bfd_mips16_num_opcodes;
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
- ""
- "ABCEFGH"
- "ij"
+ "~!@#$%^&*|"
+ "ABCEFGHTUVW"
+ "dehijklnouvwx"
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-0.s
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-0.s
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-0.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-0.s 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1 @@
+.gnu_attribute 8,0
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-00.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-00.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-00.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-00.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,6 @@
+#source: attr-gnu-8-0.s
+#source: attr-gnu-8-0.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-01.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-01.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-01.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-01.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-0.s
+#source: attr-gnu-8-1.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: 128-bit MSA
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-02.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-02.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-02.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-02.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-0.s
+#source: attr-gnu-8-2.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\)
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-1.s
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-1.s
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-1.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-1.s 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1 @@
+.gnu_attribute 8,1
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-10.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-10.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-10.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-10.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-1.s
+#source: attr-gnu-8-0.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: 128-bit MSA
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-11.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-11.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-11.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-11.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-1.s
+#source: attr-gnu-8-1.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: 128-bit MSA
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-12.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-12.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-12.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-12.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,5 @@
+#source: attr-gnu-8-1.s
+#source: attr-gnu-8-2.s
+#ld: -r
+#warning: Warning: .* uses -mmsa \(set by .*\), .* uses unknown MSA ABI 2
+#target: mips*-*-*
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-2.s
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-2.s
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-2.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-2.s 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1 @@
+.gnu_attribute 8,2
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-20.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-20.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-20.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-20.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-2.s
+#source: attr-gnu-8-0.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\)
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-21.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-21.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-21.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-21.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,5 @@
+#source: attr-gnu-8-2.s
+#source: attr-gnu-8-1.s
+#ld: -r
+#warning: Warning: .* uses unknown MSA ABI 2 \(set by .*\), .* uses -mmsa
+#target: mips*-*-*
Index: ld/testsuite/ld-mips-elf/attr-gnu-8-22.d
===================================================================
RCS file: ld/testsuite/ld-mips-elf/attr-gnu-8-22.d
diff -N ld/testsuite/ld-mips-elf/attr-gnu-8-22.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-mips-elf/attr-gnu-8-22.d 9 Oct 2013 23:42:59 -0000
@@ -0,0 +1,9 @@
+#source: attr-gnu-8-2.s
+#source: attr-gnu-8-2.s
+#ld: -r
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+ Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\)
Index: ld/testsuite/ld-mips-elf/mips-elf.exp
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-mips-elf/mips-elf.exp,v
retrieving revision 1.82
diff -u -p -r1.82 mips-elf.exp
--- ld/testsuite/ld-mips-elf/mips-elf.exp 24 Sep 2013 22:15:38 -0000 1.82
+++ ld/testsuite/ld-mips-elf/mips-elf.exp 9 Oct 2013 23:43:00 -0000
@@ -751,3 +751,13 @@ foreach { abi } $abis {
[list "objdump -d jalr3.dd"] \
"jalr3-${abi}"]]
}
+
+run_dump_test "attr-gnu-8-00"
+run_dump_test "attr-gnu-8-01"
+run_dump_test "attr-gnu-8-02"
+run_dump_test "attr-gnu-8-10"
+run_dump_test "attr-gnu-8-11"
+run_dump_test "attr-gnu-8-12"
+run_dump_test "attr-gnu-8-20"
+run_dump_test "attr-gnu-8-21"
+run_dump_test "attr-gnu-8-22"
Index: opcodes/micromips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/micromips-opc.c,v
retrieving revision 1.27
diff -u -p -r1.27 micromips-opc.c
--- opcodes/micromips-opc.c 7 Oct 2013 18:02:47 -0000 1.27
+++ opcodes/micromips-opc.c 9 Oct 2013 23:43:03 -0000
@@ -107,9 +107,35 @@ decode_micromips_operand (const char *p)
case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */
case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
-
+ case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
+ case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
+ case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
+ case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */
+
+ case 'd': REG (5, 6, MSA);
+ case 'e': REG (5, 11, MSA);
+ case 'h': REG (5, 16, MSA);
case 'i': JALX (26, 0, 2);
case 'j': SINT (9, 0);
+ case 'k': REG (5, 6, GP);
+ case 'l': REG (5, 6, MSA_CTRL);
+ case 'n': REG (5, 11, MSA_CTRL);
+ case 'o': SPECIAL (5, 16, IMM_INDEX);
+ case 'u': SPECIAL (4, 16, IMM_INDEX);
+ case 'v': SPECIAL (3, 16, IMM_INDEX);
+ case 'w': SPECIAL (2, 16, IMM_INDEX);
+ case 'x': BIT (5, 16, 0); /* (0 .. 31) */
+
+ case '~': BIT (2, 6, 1); /* (1 .. 4) */
+ case '!': BIT (3, 16, 0); /* (0 .. 7) */
+ case '@': BIT (4, 16, 0); /* (0 .. 15) */
+ case '#': BIT (6, 16, 0); /* (0 .. 63) */
+ case '$': UINT (5, 16); /* (0 .. 31) */
+ case '%': SINT (5, 16); /* (-16 .. 15) */
+ case '^': SINT (10, 11); /* (-512 .. 511) */
+ case '&': SPECIAL (0, 0, IMM_INDEX);
+ case '*': SPECIAL (5, 16, REG_INDEX);
+ case '|': BIT (8, 16, 0); /* (0 .. 255) */
}
break;
@@ -246,6 +272,10 @@ decode_micromips_operand (const char *p)
#define IVIRT ASE_VIRT
#define IVIRT64 ASE_VIRT64
+/* MSA support. */
+#define MSA ASE_MSA
+#define MSA64 ASE_MSA64
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
@@ -1287,6 +1317,539 @@ const struct mips_opcode micromips_opcod
{"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
{"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
{"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 },
+/* MSA Extension. */
+{"sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"slli.b", "+d,+e,+!", 0x58700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.h", "+d,+e,+@", 0x58600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.w", "+d,+e,+x", 0x58400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.d", "+d,+e,+#", 0x58000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sra.b", "+d,+e,+h", 0x5880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.h", "+d,+e,+h", 0x58a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.w", "+d,+e,+h", 0x58c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.d", "+d,+e,+h", 0x58e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srai.b", "+d,+e,+!", 0x58f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.h", "+d,+e,+@", 0x58e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.w", "+d,+e,+x", 0x58c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.d", "+d,+e,+#", 0x58800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srl.b", "+d,+e,+h", 0x5900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.h", "+d,+e,+h", 0x5920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.w", "+d,+e,+h", 0x5940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.d", "+d,+e,+h", 0x5960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srli.b", "+d,+e,+!", 0x59700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.h", "+d,+e,+@", 0x59600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.w", "+d,+e,+x", 0x59400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.d", "+d,+e,+#", 0x59000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclr.b", "+d,+e,+h", 0x5980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.h", "+d,+e,+h", 0x59a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.w", "+d,+e,+h", 0x59c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.d", "+d,+e,+h", 0x59e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclri.b", "+d,+e,+!", 0x59f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.h", "+d,+e,+@", 0x59e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.w", "+d,+e,+x", 0x59c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.d", "+d,+e,+#", 0x59800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bset.b", "+d,+e,+h", 0x5a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.h", "+d,+e,+h", 0x5a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.w", "+d,+e,+h", 0x5a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.d", "+d,+e,+h", 0x5a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bseti.b", "+d,+e,+!", 0x5a700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.h", "+d,+e,+@", 0x5a600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.w", "+d,+e,+x", 0x5a400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.d", "+d,+e,+#", 0x5a000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bneg.b", "+d,+e,+h", 0x5a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.h", "+d,+e,+h", 0x5aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.w", "+d,+e,+h", 0x5ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.d", "+d,+e,+h", 0x5ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bnegi.b", "+d,+e,+!", 0x5af00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.h", "+d,+e,+@", 0x5ae00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.w", "+d,+e,+x", 0x5ac00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.d", "+d,+e,+#", 0x5a800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"binsl.b", "+d,+e,+h", 0x5b00001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.h", "+d,+e,+h", 0x5b20001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.w", "+d,+e,+h", 0x5b40001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.d", "+d,+e,+h", 0x5b60001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsli.b", "+d,+e,+!", 0x5b700012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.h", "+d,+e,+@", 0x5b600012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.w", "+d,+e,+x", 0x5b400012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.d", "+d,+e,+#", 0x5b000012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsr.b", "+d,+e,+h", 0x5b80001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.h", "+d,+e,+h", 0x5ba0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.w", "+d,+e,+h", 0x5bc0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.d", "+d,+e,+h", 0x5be0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsri.b", "+d,+e,+!", 0x5bf00012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.h", "+d,+e,+@", 0x5be00012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.w", "+d,+e,+x", 0x5bc00012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.d", "+d,+e,+#", 0x5b800012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"addv.b", "+d,+e,+h", 0x5800002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.h", "+d,+e,+h", 0x5820002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.w", "+d,+e,+h", 0x5840002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.d", "+d,+e,+h", 0x5860002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addvi.b", "+d,+e,+$", 0x58000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.h", "+d,+e,+$", 0x58200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.w", "+d,+e,+$", 0x58400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.d", "+d,+e,+$", 0x58600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subv.b", "+d,+e,+h", 0x5880002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.h", "+d,+e,+h", 0x58a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.w", "+d,+e,+h", 0x58c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.d", "+d,+e,+h", 0x58e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subvi.b", "+d,+e,+$", 0x58800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.h", "+d,+e,+$", 0x58a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.w", "+d,+e,+$", 0x58c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.d", "+d,+e,+$", 0x58e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_s.b", "+d,+e,+h", 0x5900002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.h", "+d,+e,+h", 0x5920002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.w", "+d,+e,+h", 0x5940002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.d", "+d,+e,+h", 0x5960002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maxi_s.b", "+d,+e,+%", 0x59000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.h", "+d,+e,+%", 0x59200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.w", "+d,+e,+%", 0x59400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.d", "+d,+e,+%", 0x59600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_u.b", "+d,+e,+h", 0x5980002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.h", "+d,+e,+h", 0x59a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.w", "+d,+e,+h", 0x59c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.d", "+d,+e,+h", 0x59e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maxi_u.b", "+d,+e,+$", 0x59800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.h", "+d,+e,+$", 0x59a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.w", "+d,+e,+$", 0x59c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.d", "+d,+e,+$", 0x59e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"min_s.b", "+d,+e,+h", 0x5a00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.h", "+d,+e,+h", 0x5a20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.w", "+d,+e,+h", 0x5a40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.d", "+d,+e,+h", 0x5a60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mini_s.b", "+d,+e,+%", 0x5a000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.h", "+d,+e,+%", 0x5a200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.w", "+d,+e,+%", 0x5a400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.d", "+d,+e,+%", 0x5a600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"min_u.b", "+d,+e,+h", 0x5a80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.h", "+d,+e,+h", 0x5aa0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.w", "+d,+e,+h", 0x5ac0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.d", "+d,+e,+h", 0x5ae0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mini_u.b", "+d,+e,+$", 0x5a800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.h", "+d,+e,+$", 0x5aa00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.w", "+d,+e,+$", 0x5ac00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.d", "+d,+e,+$", 0x5ae00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_a.b", "+d,+e,+h", 0x5b00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.h", "+d,+e,+h", 0x5b20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.w", "+d,+e,+h", 0x5b40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.d", "+d,+e,+h", 0x5b60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.b", "+d,+e,+h", 0x5b80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.h", "+d,+e,+h", 0x5ba0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.w", "+d,+e,+h", 0x5bc0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.d", "+d,+e,+h", 0x5be0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.b", "+d,+e,+h", 0x5800003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.h", "+d,+e,+h", 0x5820003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.w", "+d,+e,+h", 0x5840003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.d", "+d,+e,+h", 0x5860003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceqi.b", "+d,+e,+%", 0x58000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.h", "+d,+e,+%", 0x58200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.w", "+d,+e,+%", 0x58400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.d", "+d,+e,+%", 0x58600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clt_s.b", "+d,+e,+h", 0x5900003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.h", "+d,+e,+h", 0x5920003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.w", "+d,+e,+h", 0x5940003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.d", "+d,+e,+h", 0x5960003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clti_s.b", "+d,+e,+%", 0x59000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.h", "+d,+e,+%", 0x59200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.w", "+d,+e,+%", 0x59400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.d", "+d,+e,+%", 0x59600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clt_u.b", "+d,+e,+h", 0x5980003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.h", "+d,+e,+h", 0x59a0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.w", "+d,+e,+h", 0x59c0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.d", "+d,+e,+h", 0x59e0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clti_u.b", "+d,+e,+$", 0x59800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.h", "+d,+e,+$", 0x59a00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.w", "+d,+e,+$", 0x59c00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.d", "+d,+e,+$", 0x59e00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"cle_s.b", "+d,+e,+h", 0x5a00003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.h", "+d,+e,+h", 0x5a20003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.w", "+d,+e,+h", 0x5a40003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.d", "+d,+e,+h", 0x5a60003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clei_s.b", "+d,+e,+%", 0x5a000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.h", "+d,+e,+%", 0x5a200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.w", "+d,+e,+%", 0x5a400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.d", "+d,+e,+%", 0x5a600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"cle_u.b", "+d,+e,+h", 0x5a80003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.h", "+d,+e,+h", 0x5aa0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.w", "+d,+e,+h", 0x5ac0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.d", "+d,+e,+h", 0x5ae0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clei_u.b", "+d,+e,+$", 0x5a800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 },
+{"ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 },
+{"ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 },
+{"ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3, 0, 0, MSA, 0 },
+{"st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.d", "+d,+W(d)", 0x5800003f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"sat_s.b", "+d,+e,+!", 0x58700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.h", "+d,+e,+@", 0x58600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.w", "+d,+e,+x", 0x58400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.d", "+d,+e,+#", 0x58000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.b", "+d,+e,+!", 0x58f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.h", "+d,+e,+@", 0x58e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.w", "+d,+e,+x", 0x58c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.d", "+d,+e,+#", 0x58800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"add_a.b", "+d,+e,+h", 0x58000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.h", "+d,+e,+h", 0x58200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.w", "+d,+e,+h", 0x58400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.d", "+d,+e,+h", 0x58600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.b", "+d,+e,+h", 0x58800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.h", "+d,+e,+h", 0x58a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.w", "+d,+e,+h", 0x58c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.d", "+d,+e,+h", 0x58e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.b", "+d,+e,+h", 0x59000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.h", "+d,+e,+h", 0x59200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.w", "+d,+e,+h", 0x59400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.d", "+d,+e,+h", 0x59600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.b", "+d,+e,+h", 0x59800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.h", "+d,+e,+h", 0x59a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.w", "+d,+e,+h", 0x59c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.d", "+d,+e,+h", 0x59e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.b", "+d,+e,+h", 0x5a000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.h", "+d,+e,+h", 0x5a200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.w", "+d,+e,+h", 0x5a400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.d", "+d,+e,+h", 0x5a600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.b", "+d,+e,+h", 0x5a800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.h", "+d,+e,+h", 0x5aa00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.w", "+d,+e,+h", 0x5ac00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.d", "+d,+e,+h", 0x5ae00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.b", "+d,+e,+h", 0x5b000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.h", "+d,+e,+h", 0x5b200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.w", "+d,+e,+h", 0x5b400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.d", "+d,+e,+h", 0x5b600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.b", "+d,+e,+h", 0x5b800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.h", "+d,+e,+h", 0x5ba00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.w", "+d,+e,+h", 0x5bc00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.d", "+d,+e,+h", 0x5be00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.b", "+d,+e,+h", 0x58000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.h", "+d,+e,+h", 0x58200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.w", "+d,+e,+h", 0x58400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.d", "+d,+e,+h", 0x58600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.b", "+d,+e,+h", 0x58800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.h", "+d,+e,+h", 0x58a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.w", "+d,+e,+h", 0x58c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.d", "+d,+e,+h", 0x58e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.b", "+d,+e,+h", 0x59000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.h", "+d,+e,+h", 0x59200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.w", "+d,+e,+h", 0x59400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.d", "+d,+e,+h", 0x59600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.b", "+d,+e,+h", 0x59800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.h", "+d,+e,+h", 0x59a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.w", "+d,+e,+h", 0x59c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.d", "+d,+e,+h", 0x59e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.b", "+d,+e,+h", 0x5a000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.h", "+d,+e,+h", 0x5a200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.w", "+d,+e,+h", 0x5a400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.d", "+d,+e,+h", 0x5a600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.b", "+d,+e,+h", 0x5a800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.h", "+d,+e,+h", 0x5aa00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.w", "+d,+e,+h", 0x5ac00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.d", "+d,+e,+h", 0x5ae00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.b", "+d,+e,+h", 0x58000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.h", "+d,+e,+h", 0x58200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.w", "+d,+e,+h", 0x58400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.d", "+d,+e,+h", 0x58600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.b", "+d,+e,+h", 0x58800023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.h", "+d,+e,+h", 0x58a00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.w", "+d,+e,+h", 0x58c00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.d", "+d,+e,+h", 0x58e00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.b", "+d,+e,+h", 0x59000023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.h", "+d,+e,+h", 0x59200023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.w", "+d,+e,+h", 0x59400023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.d", "+d,+e,+h", 0x59600023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.b", "+d,+e,+h", 0x5a000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.h", "+d,+e,+h", 0x5a200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.w", "+d,+e,+h", 0x5a400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.d", "+d,+e,+h", 0x5a600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.b", "+d,+e,+h", 0x5a800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.h", "+d,+e,+h", 0x5aa00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.w", "+d,+e,+h", 0x5ac00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.d", "+d,+e,+h", 0x5ae00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.b", "+d,+e,+h", 0x5b000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.h", "+d,+e,+h", 0x5b200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.w", "+d,+e,+h", 0x5b400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.d", "+d,+e,+h", 0x5b600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.b", "+d,+e,+h", 0x5b800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.h", "+d,+e,+h", 0x5ba00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.w", "+d,+e,+h", 0x5bc00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.d", "+d,+e,+h", 0x5be00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.h", "+d,+e,+h", 0x58200033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.w", "+d,+e,+h", 0x58400033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.d", "+d,+e,+h", 0x58600033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.h", "+d,+e,+h", 0x58a00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.w", "+d,+e,+h", 0x58c00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.d", "+d,+e,+h", 0x58e00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.h", "+d,+e,+h", 0x59200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.w", "+d,+e,+h", 0x59400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.d", "+d,+e,+h", 0x59600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.h", "+d,+e,+h", 0x59a00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.w", "+d,+e,+h", 0x59c00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.d", "+d,+e,+h", 0x59e00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.h", "+d,+e,+h", 0x5a200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.w", "+d,+e,+h", 0x5a400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.d", "+d,+e,+h", 0x5a600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.h", "+d,+e,+h", 0x5aa00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.w", "+d,+e,+h", 0x5ac00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.d", "+d,+e,+h", 0x5ae00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.b", "+d,+e+*", 0x5800000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.h", "+d,+e+*", 0x5820000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.w", "+d,+e+*", 0x5840000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.d", "+d,+e+*", 0x5860000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sldi.b", "+d,+e+o", 0x58000016, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.h", "+d,+e+u", 0x58200016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.w", "+d,+e+v", 0x58300016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.d", "+d,+e+w", 0x58380016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"splat.b", "+d,+e+*", 0x5880000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.h", "+d,+e+*", 0x58a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.w", "+d,+e+*", 0x58c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.d", "+d,+e+*", 0x58e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splati.b", "+d,+e+o", 0x58400016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.h", "+d,+e+u", 0x58600016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.w", "+d,+e+v", 0x58700016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.d", "+d,+e+w", 0x58780016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pckev.b", "+d,+e,+h", 0x5900000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.h", "+d,+e,+h", 0x5920000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.w", "+d,+e,+h", 0x5940000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.d", "+d,+e,+h", 0x5960000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.b", "+d,+e,+h", 0x5980000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.h", "+d,+e,+h", 0x59a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.w", "+d,+e,+h", 0x59c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.d", "+d,+e,+h", 0x59e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.b", "+d,+e,+h", 0x5a00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.h", "+d,+e,+h", 0x5a20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.w", "+d,+e,+h", 0x5a40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.d", "+d,+e,+h", 0x5a60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.b", "+d,+e,+h", 0x5a80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.h", "+d,+e,+h", 0x5aa0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.w", "+d,+e,+h", 0x5ac0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.d", "+d,+e,+h", 0x5ae0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.b", "+d,+e,+h", 0x5b00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.h", "+d,+e,+h", 0x5b20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.w", "+d,+e,+h", 0x5b40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.d", "+d,+e,+h", 0x5b60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.b", "+d,+e,+h", 0x5b80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.h", "+d,+e,+h", 0x5ba0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.w", "+d,+e,+h", 0x5bc0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.d", "+d,+e,+h", 0x5be0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.b", "+d,+e,+h", 0x5800001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.h", "+d,+e,+h", 0x5820001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.w", "+d,+e,+h", 0x5840001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.d", "+d,+e,+h", 0x5860001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.b", "+d,+e,+h", 0x5880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.h", "+d,+e,+h", 0x58a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.w", "+d,+e,+h", 0x58c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.d", "+d,+e,+h", 0x58e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srari.b", "+d,+e,+!", 0x59700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.h", "+d,+e,+@", 0x59600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.w", "+d,+e,+x", 0x59400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.d", "+d,+e,+#", 0x59000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlr.b", "+d,+e,+h", 0x5900001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.h", "+d,+e,+h", 0x5920001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.w", "+d,+e,+h", 0x5940001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.d", "+d,+e,+h", 0x5960001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlri.b", "+d,+e,+!", 0x59f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.h", "+d,+e,+@", 0x59e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.w", "+d,+e,+x", 0x59c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.d", "+d,+e,+#", 0x59800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"hadd_s.h", "+d,+e,+h", 0x5a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_s.w", "+d,+e,+h", 0x5a40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_s.d", "+d,+e,+h", 0x5a60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.h", "+d,+e,+h", 0x5aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.w", "+d,+e,+h", 0x5ac0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.d", "+d,+e,+h", 0x5ae0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.h", "+d,+e,+h", 0x5b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.w", "+d,+e,+h", 0x5b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.d", "+d,+e,+h", 0x5b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.h", "+d,+e,+h", 0x5ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.w", "+d,+e,+h", 0x5bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.d", "+d,+e,+h", 0x5be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"and.v", "+d,+e,+h", 0x5800002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"andi.b", "+d,+e,+|", 0x58000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"or.v", "+d,+e,+h", 0x5820002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ori.b", "+d,+e,+|", 0x59000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nor.v", "+d,+e,+h", 0x5840002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"nori.b", "+d,+e,+|", 0x5a000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"xor.v", "+d,+e,+h", 0x5860002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"xori.b", "+d,+e,+|", 0x5b000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bmnz.v", "+d,+e,+h", 0x5880002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bmnzi.b", "+d,+e,+|", 0x58000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"bmz.v", "+d,+e,+h", 0x58a0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bmzi.b", "+d,+e,+|", 0x59000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"bsel.v", "+d,+e,+h", 0x58c0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bseli.b", "+d,+e,+|", 0x5a000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"shf.b", "+d,+e,+|", 0x58000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"shf.h", "+d,+e,+|", 0x59000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"shf.w", "+d,+e,+|", 0x5a000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnz.v", "+h,p", 0x81e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"fill.b", "+d,d", 0x5b00002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.h", "+d,d", 0x5b01002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.w", "+d,d", 0x5b02002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.d", "+d,d", 0x5b03002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"pcnt.b", "+d,+e", 0x5b04002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.h", "+d,+e", 0x5b05002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.w", "+d,+e", 0x5b06002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.d", "+d,+e", 0x5b07002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.b", "+d,+e", 0x5b08002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.h", "+d,+e", 0x5b09002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.w", "+d,+e", 0x5b0a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.d", "+d,+e", 0x5b0b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.b", "+d,+e", 0x5b0c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.h", "+d,+e", 0x5b0d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.w", "+d,+e", 0x5b0e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.d", "+d,+e", 0x5b0f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.b", "+k,+e+o", 0x58800016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.h", "+k,+e+u", 0x58a00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.w", "+k,+e+v", 0x58b00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.d", "+k,+e+w", 0x58b80016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"copy_u.b", "+k,+e+o", 0x58c00016, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.h", "+k,+e+u", 0x58e00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.w", "+k,+e+v", 0x58f00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.d", "+k,+e+w", 0x58f80016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"insert.b", "+d+o,d", 0x59000016, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.h", "+d+u,d", 0x59200016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.w", "+d+v,d", 0x59300016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.d", "+d+w,d", 0x59380016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA64, 0 },
+{"insve.b", "+d+o,+e+&", 0x59400016, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.h", "+d+u,+e+&", 0x59600016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.w", "+d+v,+e+&", 0x59700016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.d", "+d+w,+e+&", 0x59780016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"bnz.b", "+h,p", 0x83800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.h", "+h,p", 0x83a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.w", "+h,p", 0x83c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.d", "+h,p", 0x83e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.b", "+h,p", 0x83000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.h", "+h,p", 0x83200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.w", "+h,p", 0x83400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.d", "+h,p", 0x83600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"fcaf.w", "+d,+e,+h", 0x58000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcaf.d", "+d,+e,+h", 0x58200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcun.w", "+d,+e,+h", 0x58400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcun.d", "+d,+e,+h", 0x58600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fceq.w", "+d,+e,+h", 0x58800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fceq.d", "+d,+e,+h", 0x58a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcueq.w", "+d,+e,+h", 0x58c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcueq.d", "+d,+e,+h", 0x58e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclt.w", "+d,+e,+h", 0x59000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclt.d", "+d,+e,+h", 0x59200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcult.w", "+d,+e,+h", 0x59400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcult.d", "+d,+e,+h", 0x59600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcle.w", "+d,+e,+h", 0x59800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcle.d", "+d,+e,+h", 0x59a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcule.w", "+d,+e,+h", 0x59c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcule.d", "+d,+e,+h", 0x59e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsaf.w", "+d,+e,+h", 0x5a000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsaf.d", "+d,+e,+h", 0x5a200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsun.w", "+d,+e,+h", 0x5a400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsun.d", "+d,+e,+h", 0x5a600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fseq.w", "+d,+e,+h", 0x5a800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fseq.d", "+d,+e,+h", 0x5aa00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsueq.w", "+d,+e,+h", 0x5ac00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsueq.d", "+d,+e,+h", 0x5ae00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fslt.w", "+d,+e,+h", 0x5b000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fslt.d", "+d,+e,+h", 0x5b200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsult.w", "+d,+e,+h", 0x5b400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsult.d", "+d,+e,+h", 0x5b600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsle.w", "+d,+e,+h", 0x5b800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsle.d", "+d,+e,+h", 0x5ba00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsule.w", "+d,+e,+h", 0x5bc00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsule.d", "+d,+e,+h", 0x5be00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fadd.w", "+d,+e,+h", 0x58000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fadd.d", "+d,+e,+h", 0x58200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsub.w", "+d,+e,+h", 0x58400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsub.d", "+d,+e,+h", 0x58600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmul.w", "+d,+e,+h", 0x58800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmul.d", "+d,+e,+h", 0x58a00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fdiv.w", "+d,+e,+h", 0x58c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fdiv.d", "+d,+e,+h", 0x58e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmadd.w", "+d,+e,+h", 0x59000036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmadd.d", "+d,+e,+h", 0x59200036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmsub.w", "+d,+e,+h", 0x59400036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmsub.d", "+d,+e,+h", 0x59600036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexp2.w", "+d,+e,+h", 0x59c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexp2.d", "+d,+e,+h", 0x59e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexdo.h", "+d,+e,+h", 0x5a000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexdo.w", "+d,+e,+h", 0x5a200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ftq.h", "+d,+e,+h", 0x5a800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ftq.w", "+d,+e,+h", 0x5aa00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin.w", "+d,+e,+h", 0x5b000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin.d", "+d,+e,+h", 0x5b200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin_a.w", "+d,+e,+h", 0x5b400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin_a.d", "+d,+e,+h", 0x5b600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax.w", "+d,+e,+h", 0x5b800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax.d", "+d,+e,+h", 0x5ba00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax_a.w", "+d,+e,+h", 0x5bc00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax_a.d", "+d,+e,+h", 0x5be00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcor.w", "+d,+e,+h", 0x5840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcor.d", "+d,+e,+h", 0x5860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcune.w", "+d,+e,+h", 0x5880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcune.d", "+d,+e,+h", 0x58a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcne.w", "+d,+e,+h", 0x58c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcne.d", "+d,+e,+h", 0x58e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mul_q.h", "+d,+e,+h", 0x5900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mul_q.w", "+d,+e,+h", 0x5920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"madd_q.h", "+d,+e,+h", 0x5940000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"madd_q.w", "+d,+e,+h", 0x5960000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msub_q.h", "+d,+e,+h", 0x5980000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msub_q.w", "+d,+e,+h", 0x59a0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsor.w", "+d,+e,+h", 0x5a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsor.d", "+d,+e,+h", 0x5a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsune.w", "+d,+e,+h", 0x5a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsune.d", "+d,+e,+h", 0x5aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsne.w", "+d,+e,+h", 0x5ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsne.d", "+d,+e,+h", 0x5ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulr_q.h", "+d,+e,+h", 0x5b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulr_q.w", "+d,+e,+h", 0x5b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddr_q.h", "+d,+e,+h", 0x5b40000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddr_q.w", "+d,+e,+h", 0x5b60000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubr_q.h", "+d,+e,+h", 0x5b80000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubr_q.w", "+d,+e,+h", 0x5ba0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclass.w", "+d,+e", 0x5b20002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fclass.d", "+d,+e", 0x5b21002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_s.w", "+d,+e", 0x5b22002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_s.d", "+d,+e", 0x5b23002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_u.w", "+d,+e", 0x5b24002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_u.d", "+d,+e", 0x5b25002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fsqrt.w", "+d,+e", 0x5b26002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fsqrt.d", "+d,+e", 0x5b27002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frsqrt.w", "+d,+e", 0x5b28002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frsqrt.d", "+d,+e", 0x5b29002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frcp.w", "+d,+e", 0x5b2a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frcp.d", "+d,+e", 0x5b2b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frint.w", "+d,+e", 0x5b2c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frint.d", "+d,+e", 0x5b2d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"flog2.w", "+d,+e", 0x5b2e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"flog2.d", "+d,+e", 0x5b2f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupl.w", "+d,+e", 0x5b30002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupl.d", "+d,+e", 0x5b31002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupr.w", "+d,+e", 0x5b32002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupr.d", "+d,+e", 0x5b33002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffql.w", "+d,+e", 0x5b34002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffql.d", "+d,+e", 0x5b35002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffqr.w", "+d,+e", 0x5b36002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffqr.d", "+d,+e", 0x5b37002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_s.w", "+d,+e", 0x5b38002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_s.d", "+d,+e", 0x5b39002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_u.w", "+d,+e", 0x5b3a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_u.d", "+d,+e", 0x5b3b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_s.w", "+d,+e", 0x5b3c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_s.d", "+d,+e", 0x5b3d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_u.w", "+d,+e", 0x5b3e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_u.d", "+d,+e", 0x5b3f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
+{"cfcmsa", "+k,+n", 0x587e0016, 0xffff003f, WR_1, 0, 0, MSA, 0 },
+{"move.v", "+d,+e", 0x58be0016, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 },
};
const int bfd_micromips_num_opcodes =
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.116
diff -u -p -r1.116 mips-dis.c
--- opcodes/mips-dis.c 19 Aug 2013 18:56:59 -0000 1.116
+++ opcodes/mips-dis.c 9 Oct 2013 23:43:04 -0000
@@ -401,6 +401,15 @@ static const char * const mips_hwr_names
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
+static const char * const msa_control_names[32] =
+{
+ "msa_ir", "msa_csr", "msa_access", "msa_save",
+ "msa_modify", "msa_request", "msa_map", "msa_unmap",
+ "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
+ "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
+ "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
+};
+
struct mips_abi_choice
{
const char * name;
@@ -498,7 +507,7 @@ const struct mips_arch_choice mips_arch_
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2,
(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
- | ASE_MT | ASE_MCU | ASE_VIRT),
+ | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -513,7 +522,7 @@ const struct mips_arch_choice mips_arch_
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
ISA_MIPS64R2,
(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
- | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64),
+ | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -738,6 +747,18 @@ parse_mips_dis_option (const char *optio
return;
}
+ if (CONST_STRNEQ (option, "msa"))
+ {
+ mips_ase |= ASE_MSA;
+ if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2)
+ {
+ mips_ase |= ASE_MSA64;
+ /* Disable ASE_MDMX, because of opcode conflicts. */
+ mips_ase &= ~ASE_MDMX;
+ }
+ return;
+ }
+
if (CONST_STRNEQ (option, "virt"))
{
mips_ase |= ASE_VIRT;
@@ -941,6 +962,15 @@ print_reg (struct disassemble_info *info
case OP_REG_R5900_ACC:
info->fprintf_func (info->stream, "$ACC");
break;
+
+ case OP_REG_MSA:
+ info->fprintf_func (info->stream, "$w%d", regno);
+ break;
+
+ case OP_REG_MSA_CTRL:
+ info->fprintf_func (info->stream, "%s", msa_control_names[regno]);
+ break;
+
}
}
@@ -1250,6 +1280,16 @@ print_insn_arg (struct disassemble_info
case OP_VU0_MATCH_SUFFIX:
print_vu0_channel (info, operand, uval);
break;
+
+ case OP_IMM_INDEX:
+ infprintf (is, "[%d]", uval);
+ break;
+
+ case OP_REG_INDEX:
+ infprintf (is, "[" );
+ print_reg (info, opcode, OP_REG_GP, uval);
+ infprintf (is, "]" );
+ break;
}
}
@@ -2094,6 +2134,9 @@ The following MIPS specific disassembler
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
+ msa Recognize MSA instructions.\n"));
+
+ fprintf (stream, _("\n\
virt Recognize the virtualization ASE instructions.\n"));
fprintf (stream, _("\n\
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.116
diff -u -p -r1.116 mips-opc.c
--- opcodes/mips-opc.c 19 Aug 2013 19:54:40 -0000 1.116
+++ opcodes/mips-opc.c 9 Oct 2013 23:43:04 -0000
@@ -71,25 +71,50 @@ decode_mips_operand (const char *p)
case 'P': BIT (5, 6, 32); /* (32 .. 63) */
case 'Q': SINT (10, 6);
case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */
+ case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
+ case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
+ case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */
+ case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */
case 'X': BIT (5, 16, 32); /* (32 .. 63) */
case 'Z': REG (5, 0, FP);
case 'a': SINT (8, 6);
case 'b': SINT (8, 3);
case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */
+ case 'd': REG (5, 6, MSA);
+ case 'e': REG (5, 11, MSA);
case 'f': INT_ADJ (15, 6, 32767, 3, TRUE);
case 'g': SINT (5, 6);
+ case 'h': REG (5, 16, MSA);
case 'i': JALX (26, 0, 2);
case 'j': SINT (9, 7);
+ case 'k': REG (5, 6, GP);
+ case 'l': REG (5, 6, MSA_CTRL);
case 'm': REG (0, 0, R5900_ACC);
+ case 'n': REG (5, 11, MSA_CTRL);
+ case 'o': SPECIAL (5, 16, IMM_INDEX);
case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */
case 'q': REG (0, 0, R5900_Q);
case 'r': REG (0, 0, R5900_R);
case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */
case 't': REG (5, 16, COPRO);
+ case 'u': SPECIAL (4, 16, IMM_INDEX);
+ case 'v': SPECIAL (3, 16, IMM_INDEX);
+ case 'w': SPECIAL (2, 16, IMM_INDEX);
case 'x': BIT (5, 16, 0); /* (0 .. 31) */
case 'y': REG (0, 0, R5900_I);
case 'z': REG (5, 0, GP);
+
+ case '~': BIT (2, 6, 1); /* (1 .. 4) */
+ case '!': BIT (3, 16, 0); /* (0 .. 7) */
+ case '@': BIT (4, 16, 0); /* (0 .. 15) */
+ case '#': BIT (6, 16, 0); /* (0 .. 63) */
+ case '$': UINT (5, 16); /* (0 .. 31) */
+ case '%': SINT (5, 16); /* (-16 .. 15) */
+ case '^': SINT (10, 11); /* (-512 .. 511) */
+ case '&': SPECIAL (0, 0, IMM_INDEX);
+ case '*': SPECIAL (5, 16, REG_INDEX);
+ case '|': BIT (8, 16, 0); /* (0 .. 255) */
}
break;
@@ -332,6 +357,10 @@ decode_mips_operand (const char *p)
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
+/* MSA support. */
+#define MSA ASE_MSA
+#define MSA64 ASE_MSA64
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -2541,6 +2570,539 @@ const struct mips_opcode mips_builtin_op
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 },
{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3, 0, 0, EVA, 0 },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+/* MSA Extension. */
+{"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"slli.b", "+d,+e,+!", 0x78700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.h", "+d,+e,+@", 0x78600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.w", "+d,+e,+x", 0x78400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"slli.d", "+d,+e,+#", 0x78000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sra.b", "+d,+e,+h", 0x7880000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.h", "+d,+e,+h", 0x78a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.w", "+d,+e,+h", 0x78c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sra.d", "+d,+e,+h", 0x78e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srai.b", "+d,+e,+!", 0x78f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.h", "+d,+e,+@", 0x78e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.w", "+d,+e,+x", 0x78c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srai.d", "+d,+e,+#", 0x78800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srl.b", "+d,+e,+h", 0x7900000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.h", "+d,+e,+h", 0x7920000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.w", "+d,+e,+h", 0x7940000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srl.d", "+d,+e,+h", 0x7960000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srli.b", "+d,+e,+!", 0x79700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.h", "+d,+e,+@", 0x79600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.w", "+d,+e,+x", 0x79400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srli.d", "+d,+e,+#", 0x79000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclr.b", "+d,+e,+h", 0x7980000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.h", "+d,+e,+h", 0x79a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.w", "+d,+e,+h", 0x79c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclr.d", "+d,+e,+h", 0x79e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bclri.b", "+d,+e,+!", 0x79f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.h", "+d,+e,+@", 0x79e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.w", "+d,+e,+x", 0x79c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bclri.d", "+d,+e,+#", 0x79800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bset.b", "+d,+e,+h", 0x7a00000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.h", "+d,+e,+h", 0x7a20000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.w", "+d,+e,+h", 0x7a40000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bset.d", "+d,+e,+h", 0x7a60000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bseti.b", "+d,+e,+!", 0x7a700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.h", "+d,+e,+@", 0x7a600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.w", "+d,+e,+x", 0x7a400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bseti.d", "+d,+e,+#", 0x7a000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bneg.b", "+d,+e,+h", 0x7a80000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.h", "+d,+e,+h", 0x7aa0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.w", "+d,+e,+h", 0x7ac0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bneg.d", "+d,+e,+h", 0x7ae0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bnegi.b", "+d,+e,+!", 0x7af00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.h", "+d,+e,+@", 0x7ae00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.w", "+d,+e,+x", 0x7ac00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnegi.d", "+d,+e,+#", 0x7a800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"binsl.b", "+d,+e,+h", 0x7b00000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.h", "+d,+e,+h", 0x7b20000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.w", "+d,+e,+h", 0x7b40000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsl.d", "+d,+e,+h", 0x7b60000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsli.b", "+d,+e,+!", 0x7b700009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.h", "+d,+e,+@", 0x7b600009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.w", "+d,+e,+x", 0x7b400009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsli.d", "+d,+e,+#", 0x7b000009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsr.b", "+d,+e,+h", 0x7b80000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.h", "+d,+e,+h", 0x7ba0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.w", "+d,+e,+h", 0x7bc0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsr.d", "+d,+e,+h", 0x7be0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"binsri.b", "+d,+e,+!", 0x7bf00009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.h", "+d,+e,+@", 0x7be00009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.w", "+d,+e,+x", 0x7bc00009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"binsri.d", "+d,+e,+#", 0x7b800009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"addv.b", "+d,+e,+h", 0x7800000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.h", "+d,+e,+h", 0x7820000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.w", "+d,+e,+h", 0x7840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addv.d", "+d,+e,+h", 0x7860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"addvi.b", "+d,+e,+$", 0x78000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.h", "+d,+e,+$", 0x78200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.w", "+d,+e,+$", 0x78400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"addvi.d", "+d,+e,+$", 0x78600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subv.b", "+d,+e,+h", 0x7880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.h", "+d,+e,+h", 0x78a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.w", "+d,+e,+h", 0x78c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subv.d", "+d,+e,+h", 0x78e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subvi.b", "+d,+e,+$", 0x78800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.h", "+d,+e,+$", 0x78a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.w", "+d,+e,+$", 0x78c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"subvi.d", "+d,+e,+$", 0x78e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_s.b", "+d,+e,+h", 0x7900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.h", "+d,+e,+h", 0x7920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.w", "+d,+e,+h", 0x7940000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_s.d", "+d,+e,+h", 0x7960000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maxi_s.b", "+d,+e,+%", 0x79000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.h", "+d,+e,+%", 0x79200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.w", "+d,+e,+%", 0x79400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_s.d", "+d,+e,+%", 0x79600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_u.b", "+d,+e,+h", 0x7980000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.h", "+d,+e,+h", 0x79a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.w", "+d,+e,+h", 0x79c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_u.d", "+d,+e,+h", 0x79e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maxi_u.b", "+d,+e,+$", 0x79800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.h", "+d,+e,+$", 0x79a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.w", "+d,+e,+$", 0x79c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"maxi_u.d", "+d,+e,+$", 0x79e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"min_s.b", "+d,+e,+h", 0x7a00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.h", "+d,+e,+h", 0x7a20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.w", "+d,+e,+h", 0x7a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_s.d", "+d,+e,+h", 0x7a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mini_s.b", "+d,+e,+%", 0x7a000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.h", "+d,+e,+%", 0x7a200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.w", "+d,+e,+%", 0x7a400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_s.d", "+d,+e,+%", 0x7a600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"min_u.b", "+d,+e,+h", 0x7a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.h", "+d,+e,+h", 0x7aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.w", "+d,+e,+h", 0x7ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_u.d", "+d,+e,+h", 0x7ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mini_u.b", "+d,+e,+$", 0x7a800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.h", "+d,+e,+$", 0x7aa00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.w", "+d,+e,+$", 0x7ac00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"mini_u.d", "+d,+e,+$", 0x7ae00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"max_a.b", "+d,+e,+h", 0x7b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.h", "+d,+e,+h", 0x7b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.w", "+d,+e,+h", 0x7b40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"max_a.d", "+d,+e,+h", 0x7b60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.b", "+d,+e,+h", 0x7b80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.h", "+d,+e,+h", 0x7ba0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.w", "+d,+e,+h", 0x7bc0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"min_a.d", "+d,+e,+h", 0x7be0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.b", "+d,+e,+h", 0x7800000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.h", "+d,+e,+h", 0x7820000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.w", "+d,+e,+h", 0x7840000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceq.d", "+d,+e,+h", 0x7860000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ceqi.b", "+d,+e,+%", 0x78000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.h", "+d,+e,+%", 0x78200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.w", "+d,+e,+%", 0x78400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ceqi.d", "+d,+e,+%", 0x78600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clt_s.b", "+d,+e,+h", 0x7900000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.h", "+d,+e,+h", 0x7920000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.w", "+d,+e,+h", 0x7940000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_s.d", "+d,+e,+h", 0x7960000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clti_s.b", "+d,+e,+%", 0x79000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.h", "+d,+e,+%", 0x79200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.w", "+d,+e,+%", 0x79400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_s.d", "+d,+e,+%", 0x79600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clt_u.b", "+d,+e,+h", 0x7980000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.h", "+d,+e,+h", 0x79a0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.w", "+d,+e,+h", 0x79c0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clt_u.d", "+d,+e,+h", 0x79e0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clti_u.b", "+d,+e,+$", 0x79800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.h", "+d,+e,+$", 0x79a00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.w", "+d,+e,+$", 0x79c00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clti_u.d", "+d,+e,+$", 0x79e00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"cle_s.b", "+d,+e,+h", 0x7a00000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.h", "+d,+e,+h", 0x7a20000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.w", "+d,+e,+h", 0x7a40000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_s.d", "+d,+e,+h", 0x7a60000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clei_s.b", "+d,+e,+%", 0x7a000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.h", "+d,+e,+%", 0x7a200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.w", "+d,+e,+%", 0x7a400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_s.d", "+d,+e,+%", 0x7a600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"cle_u.b", "+d,+e,+h", 0x7a80000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.h", "+d,+e,+h", 0x7aa0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.w", "+d,+e,+h", 0x7ac0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"cle_u.d", "+d,+e,+h", 0x7ae0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"clei_u.b", "+d,+e,+$", 0x7a800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.h", "+d,+e,+$", 0x7aa00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.w", "+d,+e,+$", 0x7ac00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"clei_u.d", "+d,+e,+$", 0x7ae00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ld.b", "+d,+T(d)", 0x78000020, 0xfc00003f, WR_1|RD_3|LDD, 0, 0, MSA, 0 },
+{"ld.h", "+d,+U(d)", 0x78000021, 0xfc00003f, WR_1|RD_3|LDD, 0, 0, MSA, 0 },
+{"ld.w", "+d,+V(d)", 0x78000022, 0xfc00003f, WR_1|RD_3|LDD, 0, 0, MSA, 0 },
+{"ld.d", "+d,+W(d)", 0x78000023, 0xfc00003f, WR_1|RD_3|LDD, 0, 0, MSA, 0 },
+{"st.b", "+d,+T(d)", 0x78000024, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.h", "+d,+U(d)", 0x78000025, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.w", "+d,+V(d)", 0x78000026, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"st.d", "+d,+W(d)", 0x78000027, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 },
+{"sat_s.b", "+d,+e,+!", 0x7870000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.h", "+d,+e,+@", 0x7860000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.w", "+d,+e,+x", 0x7840000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_s.d", "+d,+e,+#", 0x7800000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.b", "+d,+e,+!", 0x78f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.h", "+d,+e,+@", 0x78e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.w", "+d,+e,+x", 0x78c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"sat_u.d", "+d,+e,+#", 0x7880000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"add_a.b", "+d,+e,+h", 0x78000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.h", "+d,+e,+h", 0x78200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.w", "+d,+e,+h", 0x78400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"add_a.d", "+d,+e,+h", 0x78600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.b", "+d,+e,+h", 0x78800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.h", "+d,+e,+h", 0x78a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.w", "+d,+e,+h", 0x78c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_a.d", "+d,+e,+h", 0x78e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.b", "+d,+e,+h", 0x79000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.h", "+d,+e,+h", 0x79200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.w", "+d,+e,+h", 0x79400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_s.d", "+d,+e,+h", 0x79600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.b", "+d,+e,+h", 0x79800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.h", "+d,+e,+h", 0x79a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.w", "+d,+e,+h", 0x79c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"adds_u.d", "+d,+e,+h", 0x79e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.b", "+d,+e,+h", 0x7a000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.h", "+d,+e,+h", 0x7a200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.w", "+d,+e,+h", 0x7a400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_s.d", "+d,+e,+h", 0x7a600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.b", "+d,+e,+h", 0x7a800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.h", "+d,+e,+h", 0x7aa00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.w", "+d,+e,+h", 0x7ac00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ave_u.d", "+d,+e,+h", 0x7ae00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.b", "+d,+e,+h", 0x7b000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.h", "+d,+e,+h", 0x7b200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.w", "+d,+e,+h", 0x7b400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_s.d", "+d,+e,+h", 0x7b600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.b", "+d,+e,+h", 0x7b800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.h", "+d,+e,+h", 0x7ba00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.w", "+d,+e,+h", 0x7bc00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"aver_u.d", "+d,+e,+h", 0x7be00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.b", "+d,+e,+h", 0x78000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.h", "+d,+e,+h", 0x78200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.w", "+d,+e,+h", 0x78400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_s.d", "+d,+e,+h", 0x78600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.b", "+d,+e,+h", 0x78800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.h", "+d,+e,+h", 0x78a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.w", "+d,+e,+h", 0x78c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subs_u.d", "+d,+e,+h", 0x78e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.b", "+d,+e,+h", 0x79000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.h", "+d,+e,+h", 0x79200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.w", "+d,+e,+h", 0x79400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsus_u.d", "+d,+e,+h", 0x79600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.b", "+d,+e,+h", 0x79800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.h", "+d,+e,+h", 0x79a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.w", "+d,+e,+h", 0x79c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"subsuu_s.d", "+d,+e,+h", 0x79e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.b", "+d,+e,+h", 0x7a000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.h", "+d,+e,+h", 0x7a200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.w", "+d,+e,+h", 0x7a400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_s.d", "+d,+e,+h", 0x7a600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.b", "+d,+e,+h", 0x7a800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.h", "+d,+e,+h", 0x7aa00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.w", "+d,+e,+h", 0x7ac00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"asub_u.d", "+d,+e,+h", 0x7ae00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.b", "+d,+e,+h", 0x78000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.h", "+d,+e,+h", 0x78200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.w", "+d,+e,+h", 0x78400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulv.d", "+d,+e,+h", 0x78600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.b", "+d,+e,+h", 0x78800012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.h", "+d,+e,+h", 0x78a00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.w", "+d,+e,+h", 0x78c00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddv.d", "+d,+e,+h", 0x78e00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.b", "+d,+e,+h", 0x79000012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.h", "+d,+e,+h", 0x79200012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.w", "+d,+e,+h", 0x79400012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubv.d", "+d,+e,+h", 0x79600012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.b", "+d,+e,+h", 0x7a000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.h", "+d,+e,+h", 0x7a200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.w", "+d,+e,+h", 0x7a400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_s.d", "+d,+e,+h", 0x7a600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.b", "+d,+e,+h", 0x7a800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.h", "+d,+e,+h", 0x7aa00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.w", "+d,+e,+h", 0x7ac00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"div_u.d", "+d,+e,+h", 0x7ae00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.b", "+d,+e,+h", 0x7b000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.h", "+d,+e,+h", 0x7b200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.w", "+d,+e,+h", 0x7b400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_s.d", "+d,+e,+h", 0x7b600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.b", "+d,+e,+h", 0x7b800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.h", "+d,+e,+h", 0x7ba00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.w", "+d,+e,+h", 0x7bc00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mod_u.d", "+d,+e,+h", 0x7be00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.h", "+d,+e,+h", 0x78200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.w", "+d,+e,+h", 0x78400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_s.d", "+d,+e,+h", 0x78600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.h", "+d,+e,+h", 0x78a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.w", "+d,+e,+h", 0x78c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dotp_u.d", "+d,+e,+h", 0x78e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.h", "+d,+e,+h", 0x79200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.w", "+d,+e,+h", 0x79400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_s.d", "+d,+e,+h", 0x79600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.h", "+d,+e,+h", 0x79a00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.w", "+d,+e,+h", 0x79c00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpadd_u.d", "+d,+e,+h", 0x79e00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.h", "+d,+e,+h", 0x7a200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.w", "+d,+e,+h", 0x7a400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_s.d", "+d,+e,+h", 0x7a600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.h", "+d,+e,+h", 0x7aa00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.w", "+d,+e,+h", 0x7ac00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dpsub_u.d", "+d,+e,+h", 0x7ae00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.b", "+d,+e+*", 0x78000014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.h", "+d,+e+*", 0x78200014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.w", "+d,+e+*", 0x78400014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sld.d", "+d,+e+*", 0x78600014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"sldi.b", "+d,+e+o", 0x78000019, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.h", "+d,+e+u", 0x78200019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.w", "+d,+e+v", 0x78300019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"sldi.d", "+d,+e+w", 0x78380019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"splat.b", "+d,+e+*", 0x78800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.h", "+d,+e+*", 0x78a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.w", "+d,+e+*", 0x78c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splat.d", "+d,+e+*", 0x78e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"splati.b", "+d,+e+o", 0x78400019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.h", "+d,+e+u", 0x78600019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.w", "+d,+e+v", 0x78700019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"splati.d", "+d,+e+w", 0x78780019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pckev.b", "+d,+e,+h", 0x79000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.h", "+d,+e,+h", 0x79200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.w", "+d,+e,+h", 0x79400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckev.d", "+d,+e,+h", 0x79600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.b", "+d,+e,+h", 0x79800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.h", "+d,+e,+h", 0x79a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.w", "+d,+e,+h", 0x79c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"pckod.d", "+d,+e,+h", 0x79e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.b", "+d,+e,+h", 0x7a000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.h", "+d,+e,+h", 0x7a200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.w", "+d,+e,+h", 0x7a400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvl.d", "+d,+e,+h", 0x7a600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.b", "+d,+e,+h", 0x7a800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.h", "+d,+e,+h", 0x7aa00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.w", "+d,+e,+h", 0x7ac00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvr.d", "+d,+e,+h", 0x7ae00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.b", "+d,+e,+h", 0x7b000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.h", "+d,+e,+h", 0x7b200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.w", "+d,+e,+h", 0x7b400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvev.d", "+d,+e,+h", 0x7b600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.b", "+d,+e,+h", 0x7b800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.h", "+d,+e,+h", 0x7ba00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.w", "+d,+e,+h", 0x7bc00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ilvod.d", "+d,+e,+h", 0x7be00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.b", "+d,+e,+h", 0x78000015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.h", "+d,+e,+h", 0x78200015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.w", "+d,+e,+h", 0x78400015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"vshf.d", "+d,+e,+h", 0x78600015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.b", "+d,+e,+h", 0x78800015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.h", "+d,+e,+h", 0x78a00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.w", "+d,+e,+h", 0x78c00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srar.d", "+d,+e,+h", 0x78e00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srari.b", "+d,+e,+!", 0x7970000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.h", "+d,+e,+@", 0x7960000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.w", "+d,+e,+x", 0x7940000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srari.d", "+d,+e,+#", 0x7900000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlr.b", "+d,+e,+h", 0x79000015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.h", "+d,+e,+h", 0x79200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.w", "+d,+e,+h", 0x79400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlr.d", "+d,+e,+h", 0x79600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"srlri.b", "+d,+e,+!", 0x79f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.h", "+d,+e,+@", 0x79e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.w", "+d,+e,+x", 0x79c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"srlri.d", "+d,+e,+#", 0x7980000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"hadd_s.h", "+d,+e,+h", 0x7a200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_s.w", "+d,+e,+h", 0x7a400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_s.d", "+d,+e,+h", 0x7a600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.h", "+d,+e,+h", 0x7aa00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.w", "+d,+e,+h", 0x7ac00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hadd_u.d", "+d,+e,+h", 0x7ae00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.h", "+d,+e,+h", 0x7b200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.w", "+d,+e,+h", 0x7b400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_s.d", "+d,+e,+h", 0x7b600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.h", "+d,+e,+h", 0x7ba00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.w", "+d,+e,+h", 0x7bc00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"hsub_u.d", "+d,+e,+h", 0x7be00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"and.v", "+d,+e,+h", 0x7800001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"andi.b", "+d,+e,+|", 0x78000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"or.v", "+d,+e,+h", 0x7820001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ori.b", "+d,+e,+|", 0x79000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nor.v", "+d,+e,+h", 0x7840001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"nori.b", "+d,+e,+|", 0x7a000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"xor.v", "+d,+e,+h", 0x7860001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"xori.b", "+d,+e,+|", 0x7b000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bmnz.v", "+d,+e,+h", 0x7880001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bmnzi.b", "+d,+e,+|", 0x78000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"bmz.v", "+d,+e,+h", 0x78a0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bmzi.b", "+d,+e,+|", 0x79000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"bsel.v", "+d,+e,+h", 0x78c0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"bseli.b", "+d,+e,+|", 0x7a000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 },
+{"shf.b", "+d,+e,+|", 0x78000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"shf.h", "+d,+e,+|", 0x79000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"shf.w", "+d,+e,+|", 0x7a000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"bnz.v", "+h,p", 0x45e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.v", "+h,p", 0x45600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.b", "+k,+e+o", 0x78800019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.h", "+k,+e+u", 0x78a00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.w", "+k,+e+v", 0x78b00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"copy_u.b", "+k,+e+o", 0x78c00019, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"copy_u.d", "+k,+e+w", 0x78f80019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA64, 0 },
+{"insert.b", "+d+o,d", 0x79000019, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.h", "+d+u,d", 0x79200019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.w", "+d+v,d", 0x79300019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insert.d", "+d+w,d", 0x79380019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA64, 0 },
+{"insve.b", "+d+o,+e+&", 0x79400019, 0xffe0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.h", "+d+u,+e+&", 0x79600019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.w", "+d+v,+e+&", 0x79700019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"insve.d", "+d+w,+e+&", 0x79780019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 },
+{"bnz.b", "+h,p", 0x47800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.h", "+h,p", 0x47a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.w", "+h,p", 0x47c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bnz.d", "+h,p", 0x47e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.b", "+h,p", 0x47000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.h", "+h,p", 0x47200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.w", "+h,p", 0x47400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"bz.d", "+h,p", 0x47600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
+{"ldi.b", "+d,+^", 0x7b000007, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.h", "+d,+^", 0x7b200007, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.w", "+d,+^", 0x7b400007, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"ldi.d", "+d,+^", 0x7b600007, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
+{"fcaf.w", "+d,+e,+h", 0x7800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcaf.d", "+d,+e,+h", 0x7820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcun.w", "+d,+e,+h", 0x7840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcun.d", "+d,+e,+h", 0x7860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fceq.w", "+d,+e,+h", 0x7880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fceq.d", "+d,+e,+h", 0x78a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcueq.w", "+d,+e,+h", 0x78c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcueq.d", "+d,+e,+h", 0x78e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclt.w", "+d,+e,+h", 0x7900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclt.d", "+d,+e,+h", 0x7920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcult.w", "+d,+e,+h", 0x7940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcult.d", "+d,+e,+h", 0x7960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcle.w", "+d,+e,+h", 0x7980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcle.d", "+d,+e,+h", 0x79a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcule.w", "+d,+e,+h", 0x79c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcule.d", "+d,+e,+h", 0x79e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsaf.w", "+d,+e,+h", 0x7a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsaf.d", "+d,+e,+h", 0x7a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsun.w", "+d,+e,+h", 0x7a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsun.d", "+d,+e,+h", 0x7a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fseq.w", "+d,+e,+h", 0x7a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fseq.d", "+d,+e,+h", 0x7aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsueq.w", "+d,+e,+h", 0x7ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsueq.d", "+d,+e,+h", 0x7ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fslt.w", "+d,+e,+h", 0x7b00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fslt.d", "+d,+e,+h", 0x7b20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsult.w", "+d,+e,+h", 0x7b40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsult.d", "+d,+e,+h", 0x7b60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsle.w", "+d,+e,+h", 0x7b80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsle.d", "+d,+e,+h", 0x7ba0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsule.w", "+d,+e,+h", 0x7bc0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsule.d", "+d,+e,+h", 0x7be0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fadd.w", "+d,+e,+h", 0x7800001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fadd.d", "+d,+e,+h", 0x7820001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsub.w", "+d,+e,+h", 0x7840001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsub.d", "+d,+e,+h", 0x7860001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmul.w", "+d,+e,+h", 0x7880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmul.d", "+d,+e,+h", 0x78a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fdiv.w", "+d,+e,+h", 0x78c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fdiv.d", "+d,+e,+h", 0x78e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmadd.w", "+d,+e,+h", 0x7900001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmadd.d", "+d,+e,+h", 0x7920001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmsub.w", "+d,+e,+h", 0x7940001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmsub.d", "+d,+e,+h", 0x7960001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexp2.w", "+d,+e,+h", 0x79c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexp2.d", "+d,+e,+h", 0x79e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexdo.h", "+d,+e,+h", 0x7a00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fexdo.w", "+d,+e,+h", 0x7a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ftq.h", "+d,+e,+h", 0x7a80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"ftq.w", "+d,+e,+h", 0x7aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin.w", "+d,+e,+h", 0x7b00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin.d", "+d,+e,+h", 0x7b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin_a.w", "+d,+e,+h", 0x7b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmin_a.d", "+d,+e,+h", 0x7b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax.w", "+d,+e,+h", 0x7b80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax.d", "+d,+e,+h", 0x7ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax_a.w", "+d,+e,+h", 0x7bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fmax_a.d", "+d,+e,+h", 0x7be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcor.w", "+d,+e,+h", 0x7840001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcor.d", "+d,+e,+h", 0x7860001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcune.w", "+d,+e,+h", 0x7880001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcune.d", "+d,+e,+h", 0x78a0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcne.w", "+d,+e,+h", 0x78c0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fcne.d", "+d,+e,+h", 0x78e0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mul_q.h", "+d,+e,+h", 0x7900001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mul_q.w", "+d,+e,+h", 0x7920001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"madd_q.h", "+d,+e,+h", 0x7940001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"madd_q.w", "+d,+e,+h", 0x7960001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msub_q.h", "+d,+e,+h", 0x7980001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msub_q.w", "+d,+e,+h", 0x79a0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsor.w", "+d,+e,+h", 0x7a40001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsor.d", "+d,+e,+h", 0x7a60001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsune.w", "+d,+e,+h", 0x7a80001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsune.d", "+d,+e,+h", 0x7aa0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsne.w", "+d,+e,+h", 0x7ac0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fsne.d", "+d,+e,+h", 0x7ae0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulr_q.h", "+d,+e,+h", 0x7b00001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"mulr_q.w", "+d,+e,+h", 0x7b20001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddr_q.h", "+d,+e,+h", 0x7b40001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"maddr_q.w", "+d,+e,+h", 0x7b60001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubr_q.h", "+d,+e,+h", 0x7b80001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"msubr_q.w", "+d,+e,+h", 0x7ba0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_s.w", "+d,+e", 0x7b22001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_s.d", "+d,+e", 0x7b23001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_u.w", "+d,+e", 0x7b24001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftrunc_u.d", "+d,+e", 0x7b25001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"ctcmsa", "+l,d", 0x783e0019, 0xffff003f, RD_2|COD, 0, 0, MSA, 0 },
+{"cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|COD, 0, 0, MSA, 0 },
+{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
+{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
+{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the