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Re: [x86-64 psABI] RFC: Extend x86-64 PLT entry to support MPX
- From: Ian Lance Taylor <iant at google dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: GNU C Library <libc-alpha at sourceware dot org>, GCC Development <gcc at gcc dot gnu dot org>, Binutils <binutils at sourceware dot org>, "Girkar, Milind" <milind dot girkar at intel dot com>, "Kreitzer, David L" <david dot l dot kreitzer at intel dot com>
- Date: Wed, 24 Jul 2013 09:45:40 -0700
- Subject: Re: [x86-64 psABI] RFC: Extend x86-64 PLT entry to support MPX
- References: <CAMe9rOp=1v38F_aV-pbv50YOGSEr_ju+byZP1L_G_h4bm5Ad3w at mail dot gmail dot com>
On Tue, Jul 23, 2013 at 12:49 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>
> http://software.intel.com/sites/default/files/319433-015.pdf
>
> introduces 4 bound registers, which will be used for parameter passing
> in x86-64. Bound registers are cleared by branch instructions. Branch
> instructions with BND prefix will keep bound register contents.
I took a very quick look at the doc. Why shouldn't we run the kernel
with BNDPRESERVE = 1, to avoid this behaviour of clearing the bound
registers on branch instructions? That would let us avoid these
issues.
> I prefer the note section solution. Any suggestions, comments?
I concur, but why not use the ELF attributes support rather than a new
note section?
Ian