Re: [committed] Remove MIPS +D and +T operands

["Maciej W. Rozycki" <macro at codesourcery dot com>]

On Mon, 8 Jul 2013, Richard Sandiford wrote:

> >> This patch removes the "+D" and "+T" entries and gets the disassembler to
> >> look directly for ",H".  It also uses a "0" at the end of the opcode
> >> name to distinguish coprocessor 0 instructions; this showed that the
> >> MIPS I LWC0 instruction wasn't being treated as coprocessor 0.
> >
> >  But why do we support things like LWC0 or SWC0 in the first place?  
> > There are no such instructions.
> 
> No idea, sorry.  Maybe a processor-specific extension?

 I think the only plausible explanation is that older ISA manuals 
listed/grouped the instructions as LWCz/SWCz rather than individually and 
their major opcodes as 1100xx/1110xx respectively, and whoever added LWC0 
and SWC0 didn't notice the z != 0 constraint.  This hypothesis is further 
backed up by the opcodes being marked as MIPS I in our opcode table rather 
than for a specific processor.

 As of the MIPS II ISA the opcodes LWC0 and SWC0 could use were taken for 
the LL and SC instruction respectively.  Therefore to find out whether 
they really existed anywhere only the original MIPS I ISA can be 
considered.  Regrettably the original MIPS I/R2000 manual is not available 
online (I only saw a hard copy once and I can't say for sure how the 
entries for LWCz/SWCz looked like there), but the MIPS II/R6000 manual is 
and does not include LWC0 or SWC0 in its list of removed instructions even 
though LL and SC took their places.  So this is one reference one can 
infer from they were not present in MIPS I/R2000.

 Then "IDT R30xx Family Software Reference Manual", that I happen to have 
handy, in its Appendix A uses the usual LWCz/SWCz and 1100xx/1110xx format 
with "This instruction is not valid for use with CP0." mentioned in the 
full descriptions only.  That book includes this note: "Appendices A & B 
contain material that is (C)1994 by Mips Technology, Inc." on its title 
page so I trust the descriptions truly come from the architecture 
designers.  Also the book makes it explicit that the IDT processors 
concerned are full MIPS I implementations, e.g. in Chapter 1: "In the case 
of the R30xx family, all devices implement the MIPS-1 ISA."

 Searching the Internet for LWC0 or SWC0 does make several references turn 
up, however none appears authoritative.  I think these instructions should 
be removed to stop confusion from spreading.  And likewise CFC0/CTC0.

  Maciej