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[committed] Make MIPS VR5400 opcodes more like MDMX
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: binutils at sourceware dot org
- Date: Sun, 07 Jul 2013 11:15:55 +0100
- Subject: [committed] Make MIPS VR5400 opcodes more like MDMX
The VR5400 has MDMX-like vector instructions, but with different opcode
assignments. In both cases the final operand can be (a) a full vector
register, (b) a broadcast of one vector element, or (c) a broadcast of an
immediate value. In the MDMX case these three alternatives were wrapped
up in the single operand type "Q", but for the VR5400 they were spelled
out as separate opcode entries.
One reason for the difference might have been that, in the VR5400 form,
SLL.OB and SRL.OB do not accept (a) and RZU.OB requires (c).
However, the format of these instructions in the architecture manual
is the same as for other OB instructions; the restrictions are given
in the description instead. This seems more like the limitations on
the performance register field (to take one example) rather than
something that should be handled directly in the opcode table.
This patch therefore uses "Q" for the VR5400 enries too and raises
specific errors for the invalid cases. This also means that "[" and "]"
no longer appear in opcode strings.
Applied.
Richard
include/opcode/
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
Index: include/opcode/mips.h
===================================================================
--- include/opcode/mips.h 2013-07-07 11:00:15.243623257 +0100
+++ include/opcode/mips.h 2013-07-07 11:11:51.886715822 +0100
@@ -387,7 +387,6 @@ struct mips_opcode
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
- Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
@@ -446,7 +445,6 @@ struct mips_opcode
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
- see also "k" above
Macro instructions:
"A" General 32 bit expression
@@ -457,13 +455,14 @@ struct mips_opcode
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
- MDMX instruction operands (note that while these use the FP register
- fields, they accept both $fN and $vN names for the registers):
- "O" MDMX alignment offset (OP_*_ALN)
- "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
- "X" MDMX destination register (OP_*_FD)
- "Y" MDMX source register (OP_*_FS)
- "Z" MDMX source register (OP_*_FT)
+ MDMX and VR5400 instruction operands (note that while these use the
+ FP register fields, the MDMX instructions accept both $fN and $vN names
+ for the registers):
+ "O" alignment offset (OP_*_ALN)
+ "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+ "X" destination register (OP_*_FD)
+ "Y" source register (OP_*_FS)
+ "Z" source register (OP_*_FT)
DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
@@ -526,7 +525,6 @@ struct mips_opcode
Other:
"()" parens surrounding optional value
"," separates operands
- "[]" brackets around index for vector-op scalar operand specifier (vr5400)
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
Index: opcodes/mips-opc.c
===================================================================
--- opcodes/mips-opc.c 2013-07-07 11:00:15.246623283 +0100
+++ opcodes/mips-opc.c 2013-07-07 11:11:51.889715849 +0100
@@ -309,9 +309,7 @@ const struct mips_opcode mips_builtin_op
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF },
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F },
{"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E },
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
@@ -338,9 +336,7 @@ const struct mips_opcode mips_builtin_op
{"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC },
@@ -448,9 +444,7 @@ const struct mips_opcode mips_builtin_op
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F },
{"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 },
@@ -524,9 +518,7 @@ const struct mips_opcode mips_builtin_op
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE },
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F },
{"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 },
@@ -544,9 +536,7 @@ const struct mips_opcode mips_builtin_op
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1, 0, EE },
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 },
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F },
{"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 },
@@ -989,9 +979,7 @@ const struct mips_opcode mips_builtin_op
{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"max.s", "D,S,T", 0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE },
{"mfbpc", "t", 0x4000c000, 0xffe0ffff, LCD|WR_t|RD_C0, 0, EE },
@@ -1042,9 +1030,7 @@ const struct mips_opcode mips_builtin_op
{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR },
{"mfsa", "d", 0x00000028, 0xffff07ff, WR_d, 0, EE },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"min.s", "D,S,T", 0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, EE },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1, 0, SF },
@@ -1164,9 +1150,7 @@ const struct mips_opcode mips_builtin_op
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F },
{"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E },
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
@@ -1175,17 +1159,13 @@ const struct mips_opcode mips_builtin_op
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX },
-{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX },
{"mula.s", "V,T", 0x4600001a, 0xffe007ff, RD_S|RD_T|FP_S, 0, EE },
{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX },
-{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"mull.ob", "S,Q", 0x48000433, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
@@ -1197,14 +1177,10 @@ const struct mips_opcode mips_builtin_op
{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX },
-{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"muls.ob", "S,Q", 0x48000032, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX },
{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1, MX },
-{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
-{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
+{"mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, WR_CC|RD_S|RD_T, 0, N54 },
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, 0, MX },
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, 0, D32 },
@@ -1248,9 +1224,7 @@ const struct mips_opcode mips_builtin_op
{"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"nor.ob", "D,S,Q", 0x4800000f, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
@@ -1258,9 +1232,7 @@ const struct mips_opcode mips_builtin_op
{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
@@ -1301,14 +1273,10 @@ const struct mips_opcode mips_builtin_op
{"phmadh", "d,s,t", 0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI },
{"phmsbh", "d,s,t", 0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, MMI },
{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"pickf.ob", "D,S,Q", 0x48000002, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"pickt.ob", "D,S,Q", 0x48000003, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI },
{"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t, 0, MMI },
@@ -1427,7 +1395,7 @@ const struct mips_opcode mips_builtin_op
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, 0, M3D },
{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX },
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX },
-{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
+{"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX },
{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP },
{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
@@ -1514,8 +1482,7 @@ const struct mips_opcode mips_builtin_op
{"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"sll.ob", "D,S,Q", 0x48000010, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
@@ -1550,8 +1517,7 @@ const struct mips_opcode mips_builtin_op
{"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"srl.ob", "D,S,Q", 0x48000012, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
/* ssnop is at the start of the table. */
{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
@@ -1562,9 +1528,7 @@ const struct mips_opcode mips_builtin_op
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1, 0, SF },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F },
{"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E },
{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
@@ -1705,9 +1669,7 @@ const struct mips_opcode mips_builtin_op
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1, MX },
-{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
-{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
-{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
+{"xor.ob", "D,S,Q", 0x4800000d, 0xfc20003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, 0, MT32 },
Index: opcodes/mips-dis.c
===================================================================
--- opcodes/mips-dis.c 2013-07-07 11:00:15.245623274 +0100
+++ opcodes/mips-dis.c 2013-07-07 11:11:51.887715831 +0100
@@ -992,8 +992,6 @@ #define GET_OP_S(insn, field) \
case ',':
case '(':
case ')':
- case '[':
- case ']':
infprintf (is, "%c", *d);
break;
@@ -1396,7 +1394,9 @@ #define GET_OP_S(insn, field) \
case 'Q':
{
unsigned int vsel = GET_OP (l, VSEL);
+ char prefix;
+ prefix = opp->membership & INSN_5400 ? 'f' : 'v';
if ((vsel & 0x10) == 0)
{
int fmt;
@@ -1405,11 +1405,11 @@ #define GET_OP_S(insn, field) \
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
- infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
+ infprintf (is, "$%c%d[%d]", prefix, GET_OP (l, FT), vsel >> 1);
}
else if ((vsel & 0x08) == 0)
{
- infprintf (is, "$v%d", GET_OP (l, FT));
+ infprintf (is, "$%c%d", prefix, GET_OP (l, FT));
}
else
{
Index: gas/config/tc-mips.c
===================================================================
--- gas/config/tc-mips.c 2013-07-07 11:00:15.252623335 +0100
+++ gas/config/tc-mips.c 2013-07-07 11:11:51.884715805 +0100
@@ -10972,8 +10972,6 @@ #define USE_BITS(mask,shift) (used_bits
USE_BITS (OP_MASK_RT, OP_SH_RT); break;
case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
- case '[': break;
- case ']': break;
case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
@@ -11785,13 +11783,6 @@ mips_ip (char *str, struct mips_cl_insn
continue;
break;
- case '[': /* These must match exactly. */
- case ']':
- gas_assert (!mips_opts.micromips);
- if (*s++ == *args)
- continue;
- break;
-
case '+': /* Opcode extension character. */
switch (*++args)
{
@@ -12656,7 +12647,7 @@ mips_ip (char *str, struct mips_cl_insn
case 'X': /* MDMX destination register. */
case 'Y': /* MDMX source register. */
case 'Z': /* MDMX target register. */
- is_mdmx = 1;
+ is_mdmx = !(insn->membership & INSN_5400);
case 'W':
gas_assert (!mips_opts.micromips);
case 'D': /* Floating point destination register. */
@@ -12712,6 +12703,11 @@ mips_ip (char *str, struct mips_cl_insn
/* This is like 'Z', but also needs to fix the MDMX
vector/scalar select bits. Note that the
scalar immediate case is handled above. */
+ if ((ip->insn_mo->membership & INSN_5400)
+ && strcmp (insn->name, "rzu.ob") == 0)
+ as_bad (_("Operand %d of `%s' must be an immediate"),
+ argnum, ip->insn_mo->name);
+
if (*s == '[')
{
int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
@@ -12734,7 +12730,13 @@ mips_ip (char *str, struct mips_cl_insn
s++;
}
else
- {
+ {
+ if ((ip->insn_mo->membership & INSN_5400)
+ && (strcmp (insn->name, "sll.ob") == 0
+ || strcmp (insn->name, "srl.ob") == 0))
+ as_bad (_("Operand %d of `%s' must be scalar"),
+ argnum, ip->insn_mo->name);
+
if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
<< OP_SH_VSEL);
Index: gas/testsuite/gas/mips/vr5400-ill.s
===================================================================
--- /dev/null 2013-07-07 08:24:27.294569946 +0100
+++ gas/testsuite/gas/mips/vr5400-ill.s 2013-07-07 11:11:51.889715849 +0100
@@ -0,0 +1,23 @@
+ sll.ob $f2,$f4,4
+ sll.ob $f2,$f4,$f6[1]
+ sll.ob $f2,$f4,$f6
+
+ srl.ob $f2,$f4,4
+ srl.ob $f2,$f4,$f6[1]
+ srl.ob $f2,$f4,$f6
+
+ rzu.ob $f2,4
+ rzu.ob $f2,$f6[1]
+ rzu.ob $f2,$f6
+
+ add.ob $f2,$f4,$f6
+ add.ob $v2,$f4,$f6
+ add.ob $f2,$v4,$f6
+ add.ob $f2,$f4,$v6
+ add.ob $v2,$v4,$v6
+
+ add.ob $f2,$f4,$f6[1]
+ add.ob $v2,$f4,$f6[1]
+ add.ob $f2,$v4,$f6[1]
+ add.ob $f2,$f4,$v6[1]
+ add.ob $v2,$v4,$v6[1]
Index: gas/testsuite/gas/mips/vr5400-ill.l
===================================================================
--- /dev/null 2013-07-07 08:24:27.294569946 +0100
+++ gas/testsuite/gas/mips/vr5400-ill.l 2013-07-07 11:11:51.889715849 +0100
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*:3: Error: Operand 3 of `sll.ob' must be scalar
+.*:7: Error: Operand 3 of `srl.ob' must be scalar
+.*:10: Error: Operand 2 of `rzu.ob' must be an immediate
+.*:11: Error: Operand 2 of `rzu.ob' must be an immediate
+.*:14: Error: Illegal operands `add.ob \$v2,\$f4,\$f6'
+.*:15: Error: Illegal operands `add.ob \$f2,\$v4,\$f6'
+.*:16: Error: Illegal operands `add.ob \$f2,\$f4,\$v6'
+.*:17: Error: Illegal operands `add.ob \$v2,\$v4,\$v6'
+.*:20: Error: Illegal operands `add.ob \$v2,\$f4,\$f6\[1\]'
+.*:21: Error: Illegal operands `add.ob \$f2,\$v4,\$f6\[1\]'
+.*:22: Error: Illegal operands `add.ob \$f2,\$f4,\$v6\[1\]'
+.*:23: Error: Illegal operands `add.ob \$v2,\$v4,\$v6\[1\]'
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
--- gas/testsuite/gas/mips/mips.exp 2013-07-07 10:31:51.795205850 +0100
+++ gas/testsuite/gas/mips/mips.exp 2013-07-07 11:11:51.890715857 +0100
@@ -707,6 +707,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "vr4120-2"
run_dump_test "vr4130"
run_dump_test "vr5400"
+ run_list_test "vr5400-ill" "-march=vr5400"
run_dump_test "vr5500"
run_dump_test "rm7000"
run_dump_test "perfcount"