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Re: [PATCH] MIPS EVA ASE Support
- From: Andrew Pinski <andrew dot pinski at caviumnetworks dot com>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: David Daney <ddaney dot cavm at gmail dot com>, Richard Sandiford <rdsandiford at googlemail dot com>, "Moore, Catherine" <Catherine_Moore at mentor dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Mon, 10 Jun 2013 17:14:17 -0700
- Subject: Re: [PATCH] MIPS EVA ASE Support
- References: <FD3DCEAC5B03E9408544A1E416F11242F8FC6EE7 at NA-MBX-01 dot mgc dot mentorg dot com> <87fvwz9hsg dot fsf at talisman dot default> <FD3DCEAC5B03E9408544A1E416F11242F8FC9639 at NA-MBX-01 dot mgc dot mentorg dot com> <87bo7g99yn dot fsf at talisman dot default> <FD3DCEAC5B03E9408544A1E416F11242F8FC9A3B at NA-MBX-01 dot mgc dot mentorg dot com> <87ip1l7oz9 dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1306102316550 dot 16287 at tp dot orcam dot me dot uk> <51B65EA9 dot 7000300 at gmail dot com> <alpine dot DEB dot 1 dot 10 dot 1306110056560 dot 16287 at tp dot orcam dot me dot uk>
On Mon, Jun 10, 2013 at 5:10 PM, Maciej W. Rozycki
<macro@codesourcery.com> wrote:
> On Tue, 11 Jun 2013, David Daney wrote:
>
>> > So overall I think we want to have another knob, perhaps just -mtlbinv
>> > (name to be agreed upon), to control these instructions in addition to
>> > -meva rather than to enable them for from what would have to be
>> > -mips32r3/-mips64r3 (yes, we're at rev. 3 already in case someone missed
>> > it ;) ). I don't think we've had a precedent where optional instructions
>> > are enabled unconditionally for a sufficiently high ISA level to possibly
>> > support them.
>>
>> Rev. 5 is the most recent as far as I can tell (rev. 4 was skipped).
>
> Well, I have seen rev. 5 mentioned recently, but I have yet to see actual
> architecture documentation. So for FSF projects such as binutils that
> rely on (require) public documentation rev. 3 is the most recent.
>
>> I guess -mtlbinv would also be implied as part of the various -mcpu=xxxx
>> options. I think you also need to be able to control it via ".set tlbinv" in
>> the source code too.
>
> Yes, of course, all the usual infrastructure implied.
>
>> It would be nice to give floating point instructions the same treatment..
>
> I'm not sure what you mean -- paired-single support? I think this is the
> only optional part of the FPU instruction set that we have not subsetted
> correctly -- the MIPS V ISA has never been implemented by itself and its
> added instruction set became optional with the MIPS64r1/MIPS32r2 ISA.
> Then we've got the MIPS-3D ASE instructions correctly covered and the
> remaining FPU instructions are tied to the respective ISAs they have been
> introduced with. Have I missed anything?
I think the problem David is mentioning is only an issue with Cavium's
version of gas and does not show up on the FSF version of gas. The
issue is that Cavium's gas defaults to soft-float which disables the
use of the fpu instructions fully and errors out about them. David
wants a way to turn them back on.
Thanks,
Andrew