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Re: further behavioral issues with ARM assembler
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: "paul at codesourcery dot com" <paul at codesourcery dot com>, "nickc at redhat dot com" <nickc at redhat dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 09 Apr 2013 15:15:10 +0100
- Subject: Re: further behavioral issues with ARM assembler
- References: <5162F8EA02000078000CB605 at nat28 dot tlf dot novell dot com>
On 08/04/13 16:05, Jan Beulich wrote:
All,
alongside the fixes I sent during the day, I've also got questions on
whether to other aspects are intentional or bugs:
The first is the fact that ".arch all" doesn't work. The code specifically
suppresses this, but it doesn't become clear why. Obviously it would
be nice to have a way to return to this command line specifiable
mode via some directive.
It's tricky because of the potential interaction with the attributes
marking on object files. The whole code in this area could do with an
overhaul; I'm not sure that tinkering at the edges is going to solve the
problems. Part of the problem is that we've got overlapping
incompatible extensions in the co-processor instruction space.
Further there are several instructions where the specification says
PC-relative addresses are okay, yet the assembler rejects them. A
likely incomplete list is
Re-ordering your list slightly.
ldrd r0, r1, [r15, r2]
ldrh r0, [r15, r0]
> strd r0, r1, [r15, r2]
> strh r0, [r15, r0]
On first inspection, these appear to be errors in GAS.
smlad r0, r0, r0, r15
SMLAD with Ra=15 isn't permitted, if you read the pseudo code carefully,
you'll see that if Ra = 15, then the instruction encodes SMUAD.
smmla r0, r0, r0, r15
Similarly this encodes SMMUL.
vld1.8 {d0}, [r15]
Section A7.7.1 "Advanced SIMD addressing mode" bans Rn=15 for all simd
addresses.
R.
Is this discrepancy intentional?
Thanks, Jan