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[PATCH v2 08/12] opcodes/ * microblaze-opc.h: Add support for clz insn
- From: david dot holsgrove at xilinx dot com
- To: binutils at sourceware dot org
- Cc: eager at eagercon dot com, edgar dot iglesias at gmail dot com, joseph at codesourcery dot com, john dot williams at xilinx dot com, vidhumouli dot hunsigida at xilinx dot com, nagaraju dot mekala at xilinx dot com, David Holsgrove <david dot holsgrove at xilinx dot com>
- Date: Thu, 11 Oct 2012 17:17:10 +1000
- Subject: [PATCH v2 08/12] opcodes/ * microblaze-opc.h: Add support for clz insn
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Add count leading zeros (clz) instruction.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
opcodes/ChangeLog | 5 +++++
opcodes/microblaze-opc.h | 3 ++-
opcodes/microblaze-opcm.h | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 36b00f3..0f06683 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
+ * microblaze-opc.h: Add support for clz insn
+ * microblaze-opcm.h: Likewise
+
+2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
+
* microblaze-opc.h: Add load/store byte reverse insns
* microblaze-opcm.h: Likewise
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 20ddaeb..18480f6 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -96,7 +96,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 284
+#define MAX_OPCODES 285
struct op_code_struct
{
@@ -394,6 +394,7 @@ struct op_code_struct
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
+ {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
};
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 522d9a8..661d836 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -25,7 +25,7 @@
enum microblaze_instr
{
- add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
+ add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
--
1.7.0.4